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@ -89,6 +89,7 @@ |
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| CFG_CMD_PING \
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| CFG_CMD_DHCP \
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| CFG_CMD_IMMAP \
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| CFG_CMD_I2C \
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| CFG_CMD_MII) |
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/* & ~( CFG_CMD_NET)) */ |
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@ -197,9 +198,30 @@ |
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* I2C configuration |
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*/ |
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#if (CONFIG_COMMANDS & CFG_CMD_I2C) |
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ |
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#define CFG_I2C_SLAVE 0x7F |
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/* enable I2C and select the hardware/software driver */ |
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#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
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#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ |
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#define CFG_I2C_SLAVE 0xFE |
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#ifdef CONFIG_SOFT_I2C |
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/*
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* Software (bit-bang) I2C driver configuration |
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*/ |
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#define PB_SCL 0x00000020 /* PB 26 */ |
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#define PB_SDA 0x00000010 /* PB 27 */ |
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
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else immr->im_cpm.cp_pbdat &= ~PB_SDA |
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
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else immr->im_cpm.cp_pbdat &= ~PB_SCL |
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#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
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#endif /* CONFIG_SOFT_I2C */ |
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#endif |
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/*-----------------------------------------------------------------------
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