x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards

It looks that x86 chipset always contains a host bridge at pci b.d.f 0.0.0, so enable this for all boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years ago · 3ff2f001c2
parent c80ff56034
commit 3ff2f001c2
5 changed files with 1 additions and 4 deletions
--- a/include/configs/bayleybay.h
+++ b/include/configs/bayleybay.h
@ -16,7 +16,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(1 << 20)
 #define CONFIG_ARCH_MISC_INIT

-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP

--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@ -31,7 +31,6 @@
 #define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE		0xe000

-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP

--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@ -19,7 +19,6 @@

 #define CONFIG_SMSC_LPC47M

-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
 #define CONFIG_RTL8169
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@ -28,7 +28,6 @@
 #define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE		0xe000

-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 #define CONFIG_PCI_PNP

 #define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,vga\0" \
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@ -192,6 +192,7 @@
 * PCI configuration
 */
 #define CONFIG_PCI
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE

 /*-----------------------------------------------------------------------
 * USB configuration