|
|
|
@ -135,8 +135,8 @@ |
|
|
|
|
#size-cells = <1>; |
|
|
|
|
/* NOR, NAND Flashes and FPGA on board */ |
|
|
|
|
ranges = <0x0 0x0 0x0 0x60000000 0x08000000 |
|
|
|
|
0x2 0x0 0x0 0x7e800000 0x00010000 |
|
|
|
|
0x3 0x0 0x0 0x7fb00000 0x00000100>; |
|
|
|
|
0x1 0x0 0x0 0x7e800000 0x00010000 |
|
|
|
|
0x2 0x0 0x0 0x7fb00000 0x00000100>; |
|
|
|
|
status = "okay"; |
|
|
|
|
|
|
|
|
|
nor@0,0 { |
|
|
|
@ -148,21 +148,21 @@ |
|
|
|
|
device-width = <1>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
nand@2,0 { |
|
|
|
|
nand@1,0 { |
|
|
|
|
compatible = "fsl,ifc-nand"; |
|
|
|
|
#address-cells = <1>; |
|
|
|
|
#size-cells = <1>; |
|
|
|
|
reg = <0x1 0x0 0x10000>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
fpga: board-control@3,0 { |
|
|
|
|
fpga: board-control@2,0 { |
|
|
|
|
#address-cells = <1>; |
|
|
|
|
#size-cells = <1>; |
|
|
|
|
compatible = "simple-bus"; |
|
|
|
|
reg = <0x3 0x0 0x0000100>; |
|
|
|
|
reg = <0x2 0x0 0x0000100>; |
|
|
|
|
bank-width = <1>; |
|
|
|
|
device-width = <1>; |
|
|
|
|
ranges = <0 3 0 0x100>; |
|
|
|
|
ranges = <0 2 0 0x100>; |
|
|
|
|
}; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|