Wolfgang Denk
18 years ago
commit
40750952c7
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#
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# (C) Copyright 2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o cpr.o memory.o
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SOBJS =
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,152 @@ |
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/*
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/processor.h> |
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extern void board_pll_init_f(void); |
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/* Some specific Acadia Defines */ |
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#define CPLD_BASE 0x80000000 |
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void liveoak_gpio_init(void) |
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{ |
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/*
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* GPIO0 setup (select GPIO or alternate function) |
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*/ |
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out32(GPIO0_OSRL, CFG_GPIO0_OSRL); |
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out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ |
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out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); |
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out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ |
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out32(GPIO0_TSRL, CFG_GPIO0_TSRL); |
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out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ |
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out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ |
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/*
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* Ultra (405EZ) was nice enough to add another GPIO controller |
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*/ |
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out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */ |
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out32(GPIO1_OSRL, CFG_GPIO1_OSRL); |
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out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */ |
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out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L); |
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out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */ |
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out32(GPIO1_TSRL, CFG_GPIO1_TSRL); |
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out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */ |
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} |
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#if 0 /* test-only: not called at all??? */
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void ext_bus_cntlr_init(void) |
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{ |
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#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) |
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mtebc(pb4ap, EBC_PB4AP); |
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mtebc(pb4cr, EBC_PB4CR); |
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#endif |
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} |
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#endif |
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int board_early_init_f(void) |
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{ |
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unsigned int reg; |
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#if 0 /* test-only */
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/*
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* If CRAM memory and SPI/NAND boot, and if the CRAM memory is |
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* already initialized by the pre-loader then we can't reinitialize |
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* CPR registers, GPIO registers and EBC registers as this will |
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* have the effect of un-initializing CRAM. |
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*/ |
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spr_reg = (volatile unsigned long) mfspr(SPRG7); |
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if (spr_reg != LOAK_CRAM) { /* != CRAM */ |
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board_pll_init_f(); |
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liveoak_gpio_init(); |
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ext_bus_cntlr_init(); |
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mtebc(pb1ap, CFG_EBC_PB1AP); |
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mtebc(pb1cr, CFG_EBC_PB1CR); |
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mtebc(pb2ap, CFG_EBC_PB2AP); |
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mtebc(pb2cr, CFG_EBC_PB2CR); |
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} |
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#else |
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board_pll_init_f(); |
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liveoak_gpio_init(); |
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/* ext_bus_cntlr_init(); */ |
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#endif |
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#if 0 /* test-only (orig) */
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/*
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* If we boot from NAND Flash, we are running in |
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* RAM, so disable the EBC_CS0 so that it goes back |
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* to the NOR Flash. It will be enabled later |
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* for the NAND Flash on EBC_CS1 |
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*/ |
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mfsdr(sdrultra0, reg); |
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mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0); |
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#endif |
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#if 0 /* test-only */
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/* configure for NAND */ |
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mfsdr(sdrultra0, reg); |
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reg &= ~SDR_ULTRA0_CSN_MASK; |
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reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS; |
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mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0); |
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#endif |
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/* USB Host core needs this bit set */ |
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mfsdr(sdrultra1, reg); |
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mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE); |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr(uicer, 0x00000000); /* disable all ints */ |
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mtdcr(uiccr, 0x00000010); |
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mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */ |
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mtdcr(uictr, 0x00000010); /* set int trigger levels */ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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return 0; |
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} |
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int misc_init_f(void) |
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{ |
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/* Set EPLD to take PHY out of reset */ |
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out8(CPLD_BASE + 0x05, 0x00); |
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udelay(100000); |
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return 0; |
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} |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard(void) |
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{ |
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char *s = getenv("serial#"); |
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printf("Board: Acadia - AMCC PPC405EZ Evaluation Board"); |
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if (s != NULL) { |
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puts(", serial# "); |
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puts(s); |
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} |
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putc('\n'); |
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return (0); |
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} |
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@ -0,0 +1,41 @@ |
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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sinclude $(TOPDIR)/board/amcc/liveoak/config.tmp |
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ifndef TEXT_BASE |
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TEXT_BASE = 0xFFFC0000
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endif |
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ifeq ($(CONFIG_NAND_U_BOOT),y) |
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LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
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endif |
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ifeq ($(CONFIG_SPI_U_BOOT),y) |
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LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds
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PAD_TO = 0x00840000
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endif |
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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@ -0,0 +1,195 @@ |
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/*
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#include <ppc405.h> |
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/* test-only: move into cpu directory!!! */ |
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#if defined(PLLMR0_200_133_66) |
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void board_pll_init_f(void) |
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{ |
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/*
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* set PLL clocks based on input sysclk is 33M |
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* |
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* ---------------------------------- |
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* | CLK | FREQ (MHz) | DIV RATIO | |
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* ---------------------------------- |
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* | CPU | 200.0 | 4 (0x02)| |
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* | PLB | 133.3 | 6 (0x06)| |
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* | OPB | 66.6 | 12 (0x0C)| |
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* | EBC | 66.6 | 12 (0x0C)| |
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* | SPI | 66.6 | 12 (0x0C)| |
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* | UART0 | 10.0 | 40 (0x28)| |
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* | UART1 | 10.0 | 40 (0x28)| |
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* | DAC | 2.0 | 200 (0xC8)| |
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* | ADC | 2.0 | 200 (0xC8)| |
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* | PWM | 100.0 | 4 (0x04)| |
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* | EMAC | 25.0 | 16 (0x10)| |
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* ----------------------------------- |
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*/ |
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/* Initialize PLL */ |
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mtcpr(cprpllc, 0x0000033c); |
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mtcpr(cprplld, 0x0c010200); |
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mtcpr(cprprimad, 0x04060c0c); |
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mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ |
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mtcpr(cprclkupd, 0x40000000); |
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} |
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#elif defined(PLLMR0_266_160_80) |
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void board_pll_init_f(void) |
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{ |
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/*
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* set PLL clocks based on input sysclk is 33M |
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* |
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* ---------------------------------- |
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* | CLK | FREQ (MHz) | DIV RATIO | |
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* ---------------------------------- |
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* | CPU | 266.64 | 3 | |
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* | PLB | 159.98 | 5 (0x05)| |
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* | OPB | 79.99 | 10 (0x0A)| |
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* | EBC | 79.99 | 10 (0x0A)| |
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* | SPI | 79.99 | 10 (0x0A)| |
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* | UART0 | 28.57 | 7 (0x07)| |
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* | UART1 | 28.57 | 7 (0x07)| |
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* | DAC | 28.57 | 7 (0xA7)| |
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* | ADC | 4 | 50 (0x32)| |
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* | PWM | 28.57 | 7 (0x07)| |
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* | EMAC | 4 | 50 (0x32)| |
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* ----------------------------------- |
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*/ |
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/* Initialize PLL */ |
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mtcpr(cprpllc, 0x20000238); |
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mtcpr(cprplld, 0x03010400); |
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mtcpr(cprprimad, 0x03050a0a); |
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mtcpr(cprperc0, 0x00000000); |
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mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ |
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mtcpr(cprperd1, 0x07323200); |
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mtcpr(cprclkupd, 0x40000000); |
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} |
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#elif defined(PLLMR0_333_166_83) |
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void board_pll_init_f(void) |
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{ |
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/*
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* set PLL clocks based on input sysclk is 33M |
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* |
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* ---------------------------------- |
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* | CLK | FREQ (MHz) | DIV RATIO | |
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* ---------------------------------- |
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* | CPU | 333.33 | 2 | |
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* | PLB | 166.66 | 4 (0x04)| |
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* | OPB | 83.33 | 8 (0x08)| |
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* | EBC | 83.33 | 8 (0x08)| |
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* | SPI | 83.33 | 8 (0x08)| |
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* | UART0 | 16.66 | 5 (0x05)| |
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* | UART1 | 16.66 | 5 (0x05)| |
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* | DAC | ???? | 166 (0xA6)| |
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* | ADC | ???? | 166 (0xA6)| |
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* | PWM | 41.66 | 3 (0x03)| |
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* | EMAC | ???? | 3 (0x03)| |
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* ----------------------------------- |
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*/ |
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/* Initialize PLL */ |
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mtcpr(cprpllc, 0x0000033C); |
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mtcpr(cprplld, 0x0a010000); |
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mtcpr(cprprimad, 0x02040808); |
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mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ |
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mtcpr(cprperd1, 0xA6A60300); |
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mtcpr(cprclkupd, 0x40000000); |
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} |
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#elif defined(PLLMR0_100_100_12) |
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void board_pll_init_f(void) |
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{ |
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/*
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* set PLL clocks based on input sysclk is 33M |
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* |
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* ---------------------- |
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* | CLK | FREQ (MHz) | |
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* ---------------------- |
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* | CPU | 100.00 | |
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* | PLB | 100.00 | |
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* | OPB | 12.00 | |
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* | EBC | 49.00 | |
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* ---------------------- |
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*/ |
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|
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/* Initialize PLL */ |
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mtcpr(cprpllc, 0x000003BC); |
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mtcpr(cprplld, 0x06060600); |
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mtcpr(cprprimad, 0x02020004); |
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mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ |
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mtcpr(cprperd1, 0xC8C81600); |
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mtcpr(cprclkupd, 0x40000000); |
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} |
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#endif /* CPU_<speed>_405EZ */ |
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#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) |
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/*
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* Get timebase clock frequency |
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*/ |
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unsigned long get_tbclk (void) |
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{ |
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unsigned long cpr_plld; |
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unsigned long cpr_primad; |
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unsigned long primad_cpudv; |
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unsigned long pllFbkDiv; |
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unsigned long freqProcessor; |
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|
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/*
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* Read PLL Mode registers |
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*/ |
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mfcpr(cprplld, cpr_plld); |
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|
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/*
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* Read CPR_PRIMAD register |
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*/ |
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mfcpr(cprprimad, cpr_primad); |
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|
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/*
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* Determine CPU clock frequency |
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*/ |
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primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); |
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if (primad_cpudv == 0) |
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primad_cpudv = 16; |
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|
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/*
|
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* Determine FBK_DIV. |
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*/ |
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pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); |
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if (pllFbkDiv == 0) |
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pllFbkDiv = 256; |
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|
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freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; |
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|
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return (freqProcessor); |
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} |
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#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,564 @@ |
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/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
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#include <common.h> |
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#include <asm/processor.h> |
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|
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#define CRAM_BANK0_BASE 0x0 |
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#define CRAM_DIDR 0x00100000 |
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#define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43 |
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#define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343 |
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#define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */ |
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#define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */ |
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#define CRAM_DEVID_NOT_SUPPORTED 0x00000000 |
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|
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#define PSRAM_PASS 0x50415353 /* "PASS" */ |
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#define PSRAM_FAIL 0x4641494C /* "FAIL" */ |
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|
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static u32 is_cram_inited(void); |
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static u32 is_cram(void); |
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static long int cram_init(u32); |
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static void cram_bcr_write(u32); |
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void udelay (unsigned long); |
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|
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void sdram_init(void) |
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{ |
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volatile unsigned long spr_reg; |
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|
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/*
|
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* If CRAM not initialized or CRAM looks initialized because this |
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* is after a warm reboot then set SPRG7 to indicate CRAM needs |
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* initialization. Note that CRAM is initialized by the SPI and |
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* NAND preloader. |
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*/ |
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spr_reg = (volatile unsigned long) mfspr(SPRG6); |
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if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) { |
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mtspr(SPRG7, LOAK_NONE); /* "NONE" */ |
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} |
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|
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#if 1 |
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/*
|
||||
* When running the NAND SPL, the normal EBC configuration is not |
||||
* done, so We need to enable EPLD access on EBC_CS_2 and the memory |
||||
* on EBC_CS_3 |
||||
*/ |
||||
|
||||
/* Enable CPLD - Needed for PSRAM Access */ |
||||
|
||||
|
||||
/* Init SDRAM by setting EBC Bank 3 for PSRAM */ |
||||
mtebc(pb1ap, CFG_EBC_PB1AP); |
||||
mtebc(pb1cr, CFG_EBC_PB1CR); |
||||
|
||||
mtebc(pb2ap, CFG_EBC_PB2AP); |
||||
mtebc(pb2cr, CFG_EBC_PB2CR); |
||||
|
||||
/* pre-boot loader code: we are in OCM */ |
||||
mtspr(SPRG6, LOAK_SPL); /* "SPL " */ |
||||
mtspr(SPRG7, LOAK_OCM); /* "OCM " */ |
||||
#endif |
||||
|
||||
return; |
||||
} |
||||
|
||||
static void cram_bcr_write(u32 wr_val) |
||||
{ |
||||
u32 tmp_reg; |
||||
u32 val; |
||||
volatile u32 gpio_reg; |
||||
|
||||
/* # Program CRAM write */ |
||||
|
||||
/*
|
||||
* set CRAM_CRE = 0x1 |
||||
* set wr_val = wr_val << 2 |
||||
*/ |
||||
gpio_reg = in32(GPIO1_OR); |
||||
out32(GPIO1_OR, gpio_reg | 0x00000400); |
||||
wr_val = wr_val << 2; |
||||
/* wr_val = 0x1c048; */ |
||||
|
||||
|
||||
/*
|
||||
* # stop PLL clock before programming CRAM |
||||
* set EPLD0_MUX_CTL.OESPR3 = 1 |
||||
* delay 2 |
||||
*/ |
||||
|
||||
|
||||
/*
|
||||
* # CS1 |
||||
* read 0x00200000 |
||||
* #shift 2 bit left before write |
||||
* set val = wr_val + 0x00200000 |
||||
* write dmem val 0 |
||||
* read 0x00200000 val |
||||
* print val/8x |
||||
*/ |
||||
tmp_reg = in32(0x00200000); |
||||
val = wr_val + 0x00200000; |
||||
/* val = 0x0021c048; */ |
||||
out32(val, 0x0000); |
||||
udelay(100000); |
||||
val = in32(0x00200000); |
||||
|
||||
debug("CRAM VAL: %x for CS1 ", val); |
||||
|
||||
/*
|
||||
* # CS2 |
||||
* read 0x02200000 |
||||
* #shift 2 bit left before write |
||||
* set val = wr_val + 0x02200000 |
||||
* write dmem val 0 |
||||
* read 0x02200000 val |
||||
* print val/8x |
||||
*/ |
||||
tmp_reg = in32(0x02200000); |
||||
val = wr_val + 0x02200000; |
||||
/* val = 0x0221c048; */ |
||||
out32(val, 0x0000); |
||||
udelay(100000); |
||||
val = in32(0x02200000); |
||||
|
||||
debug("CRAM VAL: %x for CS2 ", val); |
||||
|
||||
/*
|
||||
* # Start PLL clock before programming CRAM |
||||
* set EPLD0_MUX_CTL.OESPR3 = 0 |
||||
*/ |
||||
|
||||
|
||||
/*
|
||||
* set CRAMCR = 0x1 |
||||
*/ |
||||
gpio_reg = in32(GPIO1_OR); |
||||
out32(GPIO1_OR, gpio_reg | 0x00000400); |
||||
|
||||
/*
|
||||
* # read CRAM config BCR ( bit19:18 = 10b ) |
||||
* #read 0x00200000 |
||||
* # 1001_1001_0001_1111 ( 991f ) => |
||||
* #10_0110_0100_0111_1100 => 2647c => 0022647c |
||||
* #0011_0010_0011_1110 (323e) |
||||
* # |
||||
*/ |
||||
|
||||
/*
|
||||
* set EPLD0_MUX_CTL.CRAMCR = 0x0 |
||||
*/ |
||||
gpio_reg = in32(GPIO1_OR); |
||||
out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF); |
||||
return; |
||||
} |
||||
|
||||
static u32 is_cram_inited() |
||||
{ |
||||
volatile unsigned long spr_reg; |
||||
|
||||
/*
|
||||
* If CRAM is initialized already, then don't reinitialize it again. |
||||
* In the case of NAND boot and SPI boot, CRAM will already be |
||||
* initialized by the pre-loader |
||||
*/ |
||||
spr_reg = (volatile unsigned long) mfspr(SPRG7); |
||||
if (spr_reg == LOAK_CRAM) { |
||||
return 1; |
||||
} else { |
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
/******
|
||||
* return 0 if not CRAM |
||||
* return 1 if CRAM and it's already inited by preloader |
||||
* else return cram_id (CRAM Device Identification Register) |
||||
******/ |
||||
static u32 is_cram(void) |
||||
{ |
||||
u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L; |
||||
volatile u32 gpio_reg; |
||||
volatile u32 cram_id = 0; |
||||
|
||||
if (is_cram_inited() == 1) { |
||||
/* this is CRAM and it is already inited (by preloader) */ |
||||
cram_id = 1; |
||||
} else { |
||||
/*
|
||||
* # CRAM CLOCK |
||||
* set GPIO0_TCR.G8 = 1 |
||||
* set GPIO0_OSRL.G8 = 0 |
||||
* set GPIO0_OR.G8 = 0 |
||||
*/ |
||||
gpio_reg = in32(GPIO0_TCR); |
||||
gpio_TCR = gpio_reg; |
||||
out32(GPIO0_TCR, gpio_reg | 0x00800000); |
||||
gpio_reg = in32(GPIO0_OSRL); |
||||
gpio_OSRL = gpio_reg; |
||||
out32(GPIO0_OSRL, gpio_reg & 0xffffbfff); |
||||
gpio_reg = in32(GPIO0_OR); |
||||
gpio_OR = gpio_reg; |
||||
out32(GPIO0_OR, gpio_reg & 0xff7fffff); |
||||
|
||||
/*
|
||||
* # CRAM Addreaa Valid |
||||
* set GPIO0_TCR.G10 = 1 |
||||
* set GPIO0_OSRL.G10 = 0 |
||||
* set GPIO0_OR.G10 = 0 |
||||
*/ |
||||
gpio_reg = in32(GPIO0_TCR); |
||||
out32(GPIO0_TCR, gpio_reg | 0x00200000); |
||||
gpio_reg = in32(GPIO0_OSRL); |
||||
out32(GPIO0_OSRL, gpio_reg & 0xfffffbff); |
||||
gpio_reg = in32(GPIO0_OR); |
||||
out32(GPIO0_OR, gpio_reg & 0xffdfffff); |
||||
|
||||
/*
|
||||
* # config input (EBC_WAIT) |
||||
* set GPIO0_ISR1L.G9 = 1 |
||||
* set GPIO0_TCR.G9 = 0 |
||||
*/ |
||||
gpio_reg = in32(GPIO0_ISR1L); |
||||
gpio_ISR1L = gpio_reg; |
||||
out32(GPIO0_ISR1L, gpio_reg | 0x00001000); |
||||
gpio_reg = in32(GPIO0_TCR); |
||||
out32(GPIO0_TCR, gpio_reg & 0xffbfffff); |
||||
|
||||
/*
|
||||
* Enable CRE to read Registers |
||||
* set GPIO0_TCR.21 = 1 |
||||
* set GPIO1_OR.21 = 1 |
||||
*/ |
||||
gpio_reg = in32(GPIO1_TCR); |
||||
out32(GPIO1_TCR, gpio_reg | 0x00000400); |
||||
|
||||
gpio_reg = in32(GPIO1_OR); |
||||
out32(GPIO1_OR, gpio_reg | 0x00000400); |
||||
|
||||
|
||||
|
||||
|
||||
/* Read Version ID */ |
||||
cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR); |
||||
udelay(100000); |
||||
|
||||
asm volatile(" sync"); |
||||
asm volatile(" eieio"); |
||||
|
||||
debug("Cram ID: %X ", cram_id); |
||||
|
||||
switch (cram_id) { |
||||
case MICRON_MT45W8MW16BGX_CRAM_ID: |
||||
case MICRON_MT45W8MW16BGX_CRAM_ID2: |
||||
/* supported CRAM vendor/part */ |
||||
break; |
||||
case CRAM_DEVID_NOT_SUPPORTED: |
||||
default: |
||||
/* check for DIDR Vendor ID of Micron */ |
||||
if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) == |
||||
MICRON_DIDR_VENDOR_ID) |
||||
{ |
||||
/* supported CRAM vendor */ |
||||
break; |
||||
} |
||||
/* this is not CRAM or not supported CRAM vendor/part */ |
||||
cram_id = 0; |
||||
/*
|
||||
* reset the GPIO registers to the values that were |
||||
* there before this routine |
||||
*/ |
||||
out32(GPIO0_TCR, gpio_TCR); |
||||
out32(GPIO0_OSRL, gpio_OSRL); |
||||
out32(GPIO0_OR, gpio_OR); |
||||
out32(GPIO0_ISR1L, gpio_ISR1L); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
return cram_id; |
||||
} |
||||
|
||||
static long int cram_init(u32 already_inited) |
||||
{ |
||||
volatile u32 tmp_reg; |
||||
u32 cram_wr_val; |
||||
|
||||
if (already_inited == 0) return 0; |
||||
|
||||
/*
|
||||
* If CRAM is initialized already, then don't reinitialize it again. |
||||
* In the case of NAND boot and SPI boot, CRAM will already be |
||||
* initialized by the pre-loader |
||||
*/ |
||||
if (already_inited != 1) |
||||
{ |
||||
/*
|
||||
* #o CRAM Card |
||||
* # - CRAMCRE @reg16 = 1; for CRAM to use |
||||
* # - CRAMCRE @reg16 = 0; for CRAM to program |
||||
* |
||||
* # enable CRAM SEL, move from setEPLD.cmd |
||||
* set EPLD0_MUX_CTL.OECRAM = 0 |
||||
* set EPLD0_MUX_CTL.CRAMCR = 1 |
||||
* set EPLD0_ETHRSTBOOT.SLCRAM = 0 |
||||
* #end |
||||
*/ |
||||
|
||||
|
||||
/*
|
||||
* #1. EBC need to program READY, CLK, ADV for ASync mode |
||||
* # config output |
||||
*/ |
||||
|
||||
/*
|
||||
* # CRAM CLOCK |
||||
* set GPIO0_TCR.G8 = 1 |
||||
* set GPIO0_OSRL.G8 = 0 |
||||
* set GPIO0_OR.G8 = 0 |
||||
*/ |
||||
tmp_reg = in32(GPIO0_TCR); |
||||
out32(GPIO0_TCR, tmp_reg | 0x00800000); |
||||
tmp_reg = in32(GPIO0_OSRL); |
||||
out32(GPIO0_OSRL, tmp_reg & 0xffffbfff); |
||||
tmp_reg = in32(GPIO0_OR); |
||||
out32(GPIO0_OR, tmp_reg & 0xff7fffff); |
||||
|
||||
/*
|
||||
* # CRAM Addreaa Valid |
||||
* set GPIO0_TCR.G10 = 1 |
||||
* set GPIO0_OSRL.G10 = 0 |
||||
* set GPIO0_OR.G10 = 0 |
||||
*/ |
||||
tmp_reg = in32(GPIO0_TCR); |
||||
out32(GPIO0_TCR, tmp_reg | 0x00200000); |
||||
tmp_reg = in32(GPIO0_OSRL); |
||||
out32(GPIO0_OSRL, tmp_reg & 0xfffffbff); |
||||
tmp_reg = in32(GPIO0_OR); |
||||
out32(GPIO0_OR, tmp_reg & 0xffdfffff); |
||||
|
||||
/*
|
||||
* # config input (EBC_WAIT) |
||||
* set GPIO0_ISR1L.G9 = 1 |
||||
* set GPIO0_TCR.G9 = 0 |
||||
*/ |
||||
tmp_reg = in32(GPIO0_ISR1L); |
||||
out32(GPIO0_ISR1L, tmp_reg | 0x00001000); |
||||
tmp_reg = in32(GPIO0_TCR); |
||||
out32(GPIO0_TCR, tmp_reg & 0xffbfffff); |
||||
|
||||
/*
|
||||
* # config CS4 from GPIO |
||||
* set GPIO0_TCR.G0 = 1 |
||||
* set GPIO0_OSRL.G0 = 1 |
||||
*/ |
||||
tmp_reg = in32(GPIO0_TCR); |
||||
out32(GPIO0_TCR, tmp_reg | 0x80000000); |
||||
tmp_reg = in32(GPIO0_OSRL); |
||||
out32(GPIO0_OSRL, tmp_reg | 0x40000000); |
||||
|
||||
/*
|
||||
* #2. EBC in Async mode |
||||
* # set EBC0_PB1AP = 0x078f0ec0 |
||||
* set EBC0_PB1AP = 0x078f1ec0 |
||||
* set EBC0_PB2AP = 0x078f1ec0 |
||||
*/ |
||||
mtebc(pb1ap, 0x078F1EC0); |
||||
mtebc(pb2ap, 0x078F1EC0); |
||||
|
||||
/*
|
||||
* #set EBC0_PB1CR = 0x000bc000 |
||||
* #enable CS2 for CRAM |
||||
* set EBC0_PB2CR = 0x020bc000 |
||||
*/ |
||||
mtebc(pb1cr, 0x000BC000); |
||||
mtebc(pb2cr, 0x020BC000); |
||||
|
||||
/*
|
||||
* #3. set CRAM in Sync mode |
||||
* #exec cm_bcr_write.cmd { 0x701f } |
||||
* #3. set CRAM in Sync mode (full drv strength) |
||||
* exec cm_bcr_write.cmd { 0x701F } |
||||
*/ |
||||
cram_wr_val = 0x7012; /* CRAM burst setting */ |
||||
cram_bcr_write(cram_wr_val); |
||||
|
||||
/*
|
||||
* #4. EBC in Sync mode |
||||
* #set EBC0_PB1AP = 0x9f800fc0 |
||||
* #set EBC0_PB1AP = 0x900001c0 |
||||
* set EBC0_PB2AP = 0x9C0201c0 |
||||
* set EBC0_PB2AP = 0x9C0201c0 |
||||
*/ |
||||
mtebc(pb1ap, 0x9C0201C0); |
||||
mtebc(pb2ap, 0x9C0201C0); |
||||
|
||||
/*
|
||||
* #5. EBC need to program READY, CLK, ADV for Sync mode |
||||
* # config output |
||||
* set GPIO0_TCR.G8 = 1 |
||||
* set GPIO0_OSRL.G8 = 1 |
||||
* set GPIO0_TCR.G10 = 1 |
||||
* set GPIO0_OSRL.G10 = 1 |
||||
*/ |
||||
tmp_reg = in32(GPIO0_TCR); |
||||
out32(GPIO0_TCR, tmp_reg | 0x00800000); |
||||
tmp_reg = in32(GPIO0_OSRL); |
||||
out32(GPIO0_OSRL, tmp_reg | 0x00004000); |
||||
tmp_reg = in32(GPIO0_TCR); |
||||
out32(GPIO0_TCR, tmp_reg | 0x00200000); |
||||
tmp_reg = in32(GPIO0_OSRL); |
||||
out32(GPIO0_OSRL, tmp_reg | 0x00000400); |
||||
|
||||
/*
|
||||
* # config input |
||||
* set GPIO0_ISR1L.G9 = 1 |
||||
* set GPIO0_TCR.G9 = 0 |
||||
*/ |
||||
tmp_reg = in32(GPIO0_ISR1L); |
||||
out32(GPIO0_ISR1L, tmp_reg | 0x00001000); |
||||
tmp_reg = in32(GPIO0_TCR); |
||||
out32(GPIO0_TCR, tmp_reg & 0xffbfffff); |
||||
|
||||
/*
|
||||
* # config EBC to use RDY |
||||
* set SDR0_ULTRA0.EBCREN = 1 |
||||
*/ |
||||
mfsdr(sdrultra0, tmp_reg); |
||||
mtsdr(sdrultra0, tmp_reg | 0x04000000); |
||||
|
||||
/*
|
||||
* set EPLD0_MUX_CTL.OESPR3 = 0 |
||||
*/ |
||||
|
||||
|
||||
mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */ |
||||
} /* if (already_inited != 1) */ |
||||
|
||||
return (64 * 1024 * 1024); |
||||
} |
||||
|
||||
/******
|
||||
* return 0 if not PSRAM |
||||
* return 1 if is PSRAM |
||||
******/ |
||||
static int is_psram(u32 addr) |
||||
{ |
||||
u32 test_pattern = 0xdeadbeef; |
||||
volatile u32 readback; |
||||
|
||||
if (addr == CFG_SDRAM_BASE) { |
||||
/* This is to temp enable OE for PSRAM */ |
||||
out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f); |
||||
udelay(10000); |
||||
} |
||||
|
||||
out32(addr, test_pattern); |
||||
asm volatile(" sync"); |
||||
asm volatile(" eieio"); |
||||
|
||||
readback = (volatile u32) in32(addr); |
||||
asm volatile(" sync"); |
||||
asm volatile(" eieio"); |
||||
if (readback == test_pattern) { |
||||
return 1; |
||||
} else { |
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
static long int psram_init(void) |
||||
{ |
||||
u32 readback; |
||||
long psramsize = 0; |
||||
int i; |
||||
|
||||
/* This is to temp enable OE for PSRAM */ |
||||
out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f); |
||||
udelay(10000); |
||||
|
||||
/*
|
||||
* PSRAM bank 1: read then write to address 0x00000000 |
||||
*/ |
||||
for (i = 0; i < 100; i++) { |
||||
if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) { |
||||
readback = PSRAM_PASS; |
||||
} else { |
||||
readback = PSRAM_FAIL; |
||||
break; |
||||
} |
||||
} |
||||
if (readback == PSRAM_PASS) { |
||||
debug("psram_init(bank0): pass\n"); |
||||
psramsize = (16 * 1024 * 1024); |
||||
} else { |
||||
debug("psram_init(bank0): fail\n"); |
||||
return 0; |
||||
} |
||||
|
||||
#if 0 |
||||
/*
|
||||
* PSRAM bank 1: read then write to address 0x01000000 |
||||
*/ |
||||
for (i = 0; i < 100; i++) { |
||||
if (is_psram((1 << 24) + (i*256)) == 1) { |
||||
readback = PSRAM_PASS; |
||||
} else { |
||||
readback = PSRAM_FAIL; |
||||
break; |
||||
} |
||||
} |
||||
if (readback == PSRAM_PASS) { |
||||
debug("psram_init(bank1): pass\n"); |
||||
psramsize = psramsize + (16 * 1024 * 1024); |
||||
} |
||||
#endif |
||||
|
||||
mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */ |
||||
|
||||
return psramsize; |
||||
} |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
long int sram_size; |
||||
u32 cram_inited; |
||||
|
||||
/* Determine Attached Memory Expansion Card*/ |
||||
cram_inited = is_cram(); |
||||
if (cram_inited != 0) { /* CRAM */ |
||||
debug("CRAM Expansion Card attached\n"); |
||||
sram_size = cram_init(cram_inited); |
||||
} else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */ |
||||
debug("PSRAM Expansion Card attached\n"); |
||||
sram_size = psram_init(); |
||||
} else { /* no SRAM */ |
||||
debug("No Memory Card Attached!!\n"); |
||||
sram_size = 0; |
||||
} |
||||
|
||||
return sram_size; |
||||
} |
||||
|
||||
int testdram(void) |
||||
{ |
||||
return (0); |
||||
} |
||||
@ -0,0 +1,150 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* . = env_offset;*/ |
||||
/* common/environment.o(.text)*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,424 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* acadia.h - configuration for AMCC Acadia (405EZ) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_ACADIA 1 /* Board is Acadia */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ |
||||
#undef CFG_DRAM_TEST /* Disable-takes long time */ |
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
||||
|
||||
#define CONFIG_NO_SERIAL_EEPROM |
||||
/*#undef CONFIG_NO_SERIAL_EEPROM*/ |
||||
|
||||
#ifdef CONFIG_NO_SERIAL_EEPROM |
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, |
||||
* assuming a 66MHz input clock to the 405EZ. |
||||
*---------------------------------------------------------------------------*/ |
||||
/* #define PLLMR0_100_100_12 */ |
||||
#define PLLMR0_200_133_66 |
||||
/* #define PLLMR0_266_160_80 */ |
||||
/* #define PLLMR0_333_166_83 */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFE000000 |
||||
#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ |
||||
|
||||
/*
|
||||
* Define here the location of the environment variables (FLASH). |
||||
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only |
||||
* supported for backward compatibility. |
||||
*/ |
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
#else |
||||
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
||||
#endif |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"hostname=acadia\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=acadia/uImage\0" \
|
||||
"kernel_addr=fff10000\0" \
|
||||
"ramdisk_addr=fff20000\0" \
|
||||
"initrd_high=30000000\0" \
|
||||
"load=tftp 200000 acadia/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b ${fileaddr} fffc0000 ${filesize};" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"kozio=bootm ffc60000\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */ |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */ |
||||
|
||||
#define CONFIG_USB_OHCI |
||||
#define CONFIG_USB_STORAGE |
||||
|
||||
#if 0 /* test-only */
|
||||
#define TEST_ONLY_NAND |
||||
#endif |
||||
|
||||
#ifdef TEST_ONLY_NAND |
||||
#define CMD_NAND CFG_CMD_NAND |
||||
#else |
||||
#define CMD_NAND 0 |
||||
#endif |
||||
|
||||
/* Partitions */ |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_ISO_PARTITION |
||||
|
||||
#define CONFIG_SUPPORT_VFAT |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CMD_NAND | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SDRAM | \
|
||||
CFG_CMD_USB) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
||||
#define CFG_BASE_BAUD 691200 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_MULTI_EEPROMS |
||||
#define CFG_I2C_EEPROM_ADDR (0xa8>>1) |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
||||
#define CONFIG_DTT_AD7414 1 /* use AD7414 */ |
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ |
||||
#define CFG_DTT_MAX_TEMP 70 |
||||
#define CFG_DTT_LOW_TEMP -30 |
||||
#define CFG_DTT_HYSTERESIS 3 |
||||
|
||||
#if 0 /* test-only... */
|
||||
/*-----------------------------------------------------------------------
|
||||
* SPI stuff - Define to include SPI control |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SPI |
||||
#endif |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
|
||||
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} |
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
#endif |
||||
|
||||
#ifdef TEST_ONLY_NAND |
||||
/*-----------------------------------------------------------------------
|
||||
* NAND FLASH |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS) |
||||
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CFG_OCM_DATA_ADDR 0xF8000000 |
||||
#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ |
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ |
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
#define CFG_NAND 0xd0000000 |
||||
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ |
||||
|
||||
/* Memory Bank 0 (Flash) initialization */ |
||||
#define CFG_EBC_PB0AP 0x03337200 |
||||
#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */ |
||||
|
||||
/* Memory Bank 1 (CRAM) initialization */ |
||||
#define CFG_EBC_PB1AP 0x030400c0 |
||||
#define CFG_EBC_PB1CR 0x000bc000 |
||||
|
||||
/* Memory Bank 2 (CRAM) initialization */ |
||||
#define CFG_EBC_PB2AP 0x030400c0 |
||||
#define CFG_EBC_PB2CR 0x020bc000 |
||||
|
||||
/* Memory Bank 3 (NAND-FLASH) initialization */ |
||||
#define CFG_EBC_PB3AP 0x018003c0 |
||||
#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) |
||||
|
||||
/* Memory Bank 4 (CPLD) initialization */ |
||||
#define CFG_EBC_PB4AP 0x04006000 |
||||
#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */ |
||||
|
||||
#define CFG_EBC_CFG 0xf8400000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO_0 setup (PPC405EZ specific) |
||||
* |
||||
* GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs |
||||
* GPIO0[4] - External Bus Controller Hold Input |
||||
* GPIO0[5] - External Bus Controller Priority Input |
||||
* GPIO0[6] - External Bus Controller HLDA Output |
||||
* GPIO0[7] - External Bus Controller Bus Request Output |
||||
* GPIO0[8] - CRAM Clk Output |
||||
* GPIO0[9] - External Bus Controller Ready Input |
||||
* GPIO0[10] - CRAM Adv Output |
||||
* GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled |
||||
* GPIO0[25] - External DMA Request Input |
||||
* GPIO0[26] - External DMA EOT I/O |
||||
* GPIO0[25] - External DMA Ack_n Output |
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
||||
* GPIO0[28-30] - Trace Outputs / PWM Inputs |
||||
* GPIO0[31] - PWM_8 I/O |
||||
*/ |
||||
#define CFG_GPIO0_TCR 0xC0000000 |
||||
#define CFG_GPIO0_OSRL 0x50000000 |
||||
#define CFG_GPIO0_OSRH 0x00000055 |
||||
#define CFG_GPIO0_ISR1L 0x00000000 |
||||
#define CFG_GPIO0_ISR1H 0x00000055 |
||||
#define CFG_GPIO0_TSRL 0x00000000 |
||||
#define CFG_GPIO0_TSRH 0x00000055 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO_1 setup (PPC405EZ specific) |
||||
* |
||||
* GPIO1[0-6] - PWM_9 to PWM_15 I/O |
||||
* GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input |
||||
* GPIO1[8] - TS5 Output / DAC_IP_TRIG Input |
||||
* GPIO1[9] - TS6 Output / ADC_IP_TRIG Input |
||||
* GPIO1[10-12] - UART0 Control Inputs |
||||
* GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input |
||||
* GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output |
||||
* GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input |
||||
* GPIO1[16] - SPI_SS_1_N Output |
||||
* GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs |
||||
*/ |
||||
#define CFG_GPIO1_OSRH 0x55455555 |
||||
#define CFG_GPIO1_OSRL 0x40000110 |
||||
#define CFG_GPIO1_ISR1H 0x00000000 |
||||
#define CFG_GPIO1_ISR1L 0x15555445 |
||||
#define CFG_GPIO1_TSRH 0x00000000 |
||||
#define CFG_GPIO1_TSRL 0x00000000 |
||||
#define CFG_GPIO1_TCR 0xFFFF8014 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* EPLD Regs. |
||||
*/ |
||||
#define EPLD_BASE 0x80000000 |
||||
#define EPLD_ETHRSTBOOT 0x10 |
||||
#define EPLD_CTRL 0x14 |
||||
#define EPLD_MUXOE 0x16 |
||||
|
||||
/*
|
||||
* State definations |
||||
*/ |
||||
#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */ |
||||
#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */ |
||||
#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */ |
||||
#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */ |
||||
#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */ |
||||
#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */ |
||||
#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue