These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Klaus Heydeck <heydeck@kieback-peter.de>master
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/*
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* (C) Copyright 2000-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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#ifndef CONFIG_ENV_ADDR |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
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#endif |
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#define CONFIG_FLASH_16BIT |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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unsigned long size_b0; |
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int i; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0<<20); |
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} |
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/* Remap FLASH according to real size */ |
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memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); |
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memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; |
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/* Re-do sizing to get full correct info */ |
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size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, |
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&flash_info[0]); |
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#endif |
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#ifdef CONFIG_ENV_IS_IN_FLASH |
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/* ENV protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, |
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&flash_info[0]); |
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#endif |
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flash_info[0].size = size_b0; |
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return (size_b0); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_AMD: printf ("AMD "); break; |
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
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default: printf ("Unknown Vendor "); break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); |
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break; |
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default: printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " " |
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); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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/*-----------------------------------------------------------------------
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*/ |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
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{ |
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short i; |
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ulong value; |
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ulong base = (ulong)addr; |
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/* Write auto select command: read Manufacturer ID */ |
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vu_short *s_addr=(vu_short*)addr; |
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s_addr[0x5555] = 0x00AA; |
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s_addr[0x2AAA] = 0x0055; |
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s_addr[0x5555] = 0x0090; |
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value = s_addr[0]; |
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value = value|(value<<16); |
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switch (value) { |
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case AMD_MANUFACT: |
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info->flash_id = FLASH_MAN_AMD; |
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break; |
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case FUJ_MANUFACT: |
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info->flash_id = FLASH_MAN_FUJ; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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} |
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value = s_addr[1]; |
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value = value|(value<<16); |
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switch (value) { |
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case FUJI_ID_29F800BA: |
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info->flash_id += FLASH_AM400T; |
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info->sector_count = 19; |
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info->size = 0x00100000; |
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break; /* => 1 MB */ |
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case AMD_ID_LV800T: |
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info->flash_id += FLASH_AM800T; |
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info->sector_count = 19; |
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info->size = 0x00100000; |
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break; /* => 1 MB */ |
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case AMD_ID_LV800B: |
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info->flash_id += FLASH_AM800B; |
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info->sector_count = 19; |
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info->size = 0x00100000; |
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break; /* => 1 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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} |
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/* set up sector start address table */ |
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/* set sector offsets for bottom boot block type */ |
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info->start[0] = base + 0x00000000; |
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info->start[1] = base + 0x00004000; |
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info->start[2] = base + 0x00006000; |
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info->start[3] = base + 0x00008000; |
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for (i = 4; i < info->sector_count; i++) { |
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info->start[i] = base + (i * 0x00010000) - 0x00030000; |
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} |
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/* check for protected sectors */ |
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for (i = 0; i < info->sector_count; i++) { |
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
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/* D0 = 1 if protected */ |
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s_addr = (volatile unsigned short *)(info->start[i]); |
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info->protect[i] = s_addr[2] & 1; |
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} |
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/*
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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s_addr = (volatile unsigned short *)info->start[0]; |
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*s_addr = 0x00F0; /* reset bank */ |
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} |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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vu_long *addr = (vu_long*)(info->start[0]); |
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int flag, prot, sect; |
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ulong start, now, last; |
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#ifdef CONFIG_FLASH_16BIT |
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vu_short *s_addr = (vu_short*)addr; |
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#endif |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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/*#ifndef CONFIG_FLASH_16BIT
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ulong type; |
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type = (info->flash_id & FLASH_VENDMASK); |
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if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return; |
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} |
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#endif*/ |
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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start = get_timer (0); |
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last = start; |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect<=s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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#ifdef CONFIG_FLASH_16BIT |
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vu_short *s_sect_addr = (vu_short*)(info->start[sect]); |
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#else |
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vu_long *sect_addr = (vu_long*)(info->start[sect]); |
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#endif |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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#ifdef CONFIG_FLASH_16BIT |
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/*printf("\ns_sect_addr=%x",s_sect_addr);*/ |
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s_addr[0x5555] = 0x00AA; |
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s_addr[0x2AAA] = 0x0055; |
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s_addr[0x5555] = 0x0080; |
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s_addr[0x5555] = 0x00AA; |
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s_addr[0x2AAA] = 0x0055; |
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s_sect_addr[0] = 0x0030; |
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#else |
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addr[0x5555] = 0x00AA00AA; |
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addr[0x2AAA] = 0x00550055; |
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addr[0x5555] = 0x00800080; |
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addr[0x5555] = 0x00AA00AA; |
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addr[0x2AAA] = 0x00550055; |
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sect_addr[0] = 0x00300030; |
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#endif |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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/* wait at least 80us - let's wait 1 ms */ |
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udelay (1000); |
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#ifdef CONFIG_FLASH_16BIT |
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while ((s_sect_addr[0] & 0x0080) != 0x0080) { |
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#else |
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while ((sect_addr[0] & 0x00800080) != 0x00800080) { |
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#endif |
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if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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return 1; |
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} |
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/* show that we're waiting */ |
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if ((now - last) > 1000) { /* every second */ |
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putc ('.'); |
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last = now; |
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} |
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} |
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} |
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} |
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/* reset to read mode */ |
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addr = (volatile unsigned long *)info->start[0]; |
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#ifdef CONFIG_FLASH_16BIT |
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s_addr[0] = 0x00F0; /* reset bank */ |
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#else |
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addr[0] = 0x00F000F0; /* reset bank */ |
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#endif |
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printf (" done\n"); |
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return 0; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp, data; |
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int i, l, rc; |
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wp = (addr & ~3); /* get lower word aligned address */ |
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/*
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i=0, cp=wp; i<l; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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for (; i<4 && cnt>0; ++i) { |
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data = (data << 8) | *src++; |
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--cnt; |
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++cp; |
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} |
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for (; cnt==0 && i<4; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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if ((rc = write_word(info, wp, data)) != 0) { |
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return (rc); |
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} |
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wp += 4; |
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} |
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/*
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* handle word aligned part |
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*/ |
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while (cnt >= 4) { |
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data = 0; |
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for (i=0; i<4; ++i) { |
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data = (data << 8) | *src++; |
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} |
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if ((rc = write_word(info, wp, data)) != 0) { |
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return (rc); |
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} |
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wp += 4; |
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cnt -= 4; |
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} |
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if (cnt == 0) { |
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return (0); |
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} |
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/*
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* handle unaligned tail bytes |
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*/ |
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data = 0; |
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for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
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data = (data << 8) | *src++; |
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--cnt; |
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} |
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for (; i<4; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *)cp); |
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} |
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return (write_word(info, wp, data)); |
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} |
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/*-----------------------------------------------------------------------
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* Write a word to Flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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static int write_word (flash_info_t *info, ulong dest, ulong data) |
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{ |
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vu_long *addr = (vu_long*)(info->start[0]); |
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#ifdef CONFIG_FLASH_16BIT |
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vu_short high_data; |
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vu_short low_data; |
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vu_short *s_addr = (vu_short*)addr; |
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#endif |
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ulong start; |
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int flag; |
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/* Check if Flash is (sufficiently) erased */ |
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if ((*((vu_long *)dest) & data) != data) { |
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return (2); |
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} |
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#ifdef CONFIG_FLASH_16BIT |
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/* Write the 16 higher-bits */ |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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high_data = ((data>>16) & 0x0000ffff); |
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s_addr[0x5555] = 0x00AA; |
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s_addr[0x2AAA] = 0x0055; |
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s_addr[0x5555] = 0x00A0; |
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*((vu_short *)dest) = high_data; |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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/* data polling for D7 */ |
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start = get_timer (0); |
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while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { |
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if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
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return (1); |
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} |
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} |
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/* Write the 16 lower-bits */ |
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#endif |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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#ifdef CONFIG_FLASH_16BIT |
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dest += 0x2; |
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low_data = (data & 0x0000ffff); |
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s_addr[0x5555] = 0x00AA; |
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s_addr[0x2AAA] = 0x0055; |
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s_addr[0x5555] = 0x00A0; |
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*((vu_short *)dest) = low_data; |
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#else |
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addr[0x5555] = 0x00AA00AA; |
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addr[0x2AAA] = 0x00550055; |
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addr[0x5555] = 0x00A000A0; |
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*((vu_long *)dest) = data; |
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#endif |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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/* data polling for D7 */ |
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start = get_timer (0); |
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#ifdef CONFIG_FLASH_16BIT |
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while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { |
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#else |
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while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { |
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#endif |
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if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
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return (1); |
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} |
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} |
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return (0); |
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} |
@ -1,68 +0,0 @@ |
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/*
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* (C) Copyright 2004 |
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* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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#include "kup.h" |
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#include <asm/io.h> |
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int misc_init_f(void) |
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{ |
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
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volatile sysconf8xx_t *siu = &immap->im_siu_conf; |
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while (in_be32(&siu->sc_sipend) & 0x20000000) { |
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debug("waiting for 5V VCC\n"); |
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} |
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/* RS232 / RS485 default is RS232 */ |
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clrbits_be16(&immap->im_ioport.iop_padat, PA_RS485); |
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clrbits_be16(&immap->im_ioport.iop_papar, PA_RS485); |
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clrbits_be16(&immap->im_ioport.iop_paodr, PA_RS485); |
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setbits_be16(&immap->im_ioport.iop_padir, PA_RS485); |
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/* IO Reset min 1 msec */ |
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setbits_be16(&immap->im_ioport.iop_padat, |
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(PA_RESET_IO_01 | PA_RESET_IO_02)); |
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clrbits_be16(&immap->im_ioport.iop_papar, |
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(PA_RESET_IO_01 | PA_RESET_IO_02)); |
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clrbits_be16(&immap->im_ioport.iop_paodr, |
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(PA_RESET_IO_01 | PA_RESET_IO_02)); |
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setbits_be16(&immap->im_ioport.iop_padir, |
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(PA_RESET_IO_01 | PA_RESET_IO_02)); |
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udelay(1000); |
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clrbits_be16(&immap->im_ioport.iop_padat, |
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(PA_RESET_IO_01 | PA_RESET_IO_02)); |
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return (0); |
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} |
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|
||||
#ifdef CONFIG_IDE_LED |
||||
void ide_led(uchar led, uchar status) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
|
||||
/* We have one led for both pcmcia slots */ |
||||
if (status) |
||||
clrbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW); |
||||
else |
||||
setbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW); |
||||
} |
||||
#endif |
||||
|
||||
void poweron_key(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
|
||||
clrbits_be16(&immap->im_ioport.iop_pcpar, PC_SWITCH1); |
||||
clrbits_be16(&immap->im_ioport.iop_pcdir, PC_SWITCH1); |
||||
|
||||
if (in_be16(&immap->im_ioport.iop_pcdat) & (PC_SWITCH1)) |
||||
setenv("key1", "off"); |
||||
else |
||||
setenv("key1", "on"); |
||||
} |
@ -1,40 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __KUP_H |
||||
#define __KUP_H |
||||
|
||||
#define PA_8 0x0080 |
||||
#define PA_9 0x0040 |
||||
#define PA_10 0x0020 |
||||
#define PA_11 0x0010 |
||||
#define PA_12 0x0008 |
||||
|
||||
#define PB_14 0x00020000 |
||||
#define PB_15 0x00010000 |
||||
#define PB_16 0x00008000 |
||||
#define PB_17 0x00004000 |
||||
|
||||
#define PC_4 0x0800 |
||||
#define PC_5 0x0400 |
||||
#define PC_9 0x0040 |
||||
|
||||
#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ |
||||
#define PA_LED_YELLOW PA_8 |
||||
#define PA_RESET_IO_01 PA_9 /* Reset left IO */ |
||||
#define PA_RESET_IO_02 PA_10 /* Reset right IO */ |
||||
#define PB_PROG_IO_01 PB_15 /* Program left IO */ |
||||
#define PB_PROG_IO_02 PB_16 /* Program right IO */ |
||||
#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off */ |
||||
#define PB_LCD_PWM PB_17 /* PB 17 */ |
||||
#define PC_SWITCH1 PC_9 /* Reboot switch */ |
||||
|
||||
|
||||
extern void poweron_key(void); |
||||
extern void load_sernum_ethaddr(void); |
||||
|
||||
#endif /* __KUP_H */ |
@ -1,78 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Process Hardware Information Block: |
||||
* |
||||
* If we boot on a system fresh from factory, check if the Hardware |
||||
* Information Block exists and save the information it contains. |
||||
* |
||||
* The KUP Hardware Information Block is defined as |
||||
* follows: |
||||
* - located in first flash bank |
||||
* - starts at offset CONFIG_SYS_HWINFO_OFFSET |
||||
* - size CONFIG_SYS_HWINFO_SIZE |
||||
* |
||||
* Internal structure: |
||||
* - sequence of ASCII character lines |
||||
* - fields separated by <CR><LF> |
||||
* - last field terminated by NUL character (0x00) |
||||
* |
||||
* Fields in Hardware Information Block: |
||||
* 1) Module Type |
||||
* 2) MAC Address |
||||
* 3) .... |
||||
*/ |
||||
|
||||
|
||||
#define ETHADDR_TOKEN "ethaddr=" |
||||
#define LCD_TOKEN "lcd=" |
||||
|
||||
void load_sernum_ethaddr (void) |
||||
{ |
||||
unsigned char *hwi; |
||||
char *var; |
||||
unsigned char hwi_stack[CONFIG_SYS_HWINFO_SIZE]; |
||||
char *p; |
||||
|
||||
hwi = (unsigned char *) (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET); |
||||
if (*((unsigned long *) hwi) != (unsigned long) CONFIG_SYS_HWINFO_MAGIC) { |
||||
printf ("HardwareInfo not found!\n"); |
||||
return; |
||||
} |
||||
memcpy (hwi_stack, hwi, CONFIG_SYS_HWINFO_SIZE); |
||||
|
||||
/*
|
||||
** ethaddr |
||||
*/ |
||||
var = strstr ((char *)hwi_stack, ETHADDR_TOKEN); |
||||
if (var) { |
||||
var += sizeof (ETHADDR_TOKEN) - 1; |
||||
p = strchr (var, '\r'); |
||||
if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) { |
||||
*p = '\0'; |
||||
setenv ("ethaddr", var); |
||||
*p = '\r'; |
||||
} |
||||
} |
||||
/*
|
||||
** lcd |
||||
*/ |
||||
var = strstr ((char *)hwi_stack, LCD_TOKEN); |
||||
if (var) { |
||||
var += sizeof (LCD_TOKEN) - 1; |
||||
p = strchr (var, '\r'); |
||||
if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) { |
||||
*p = '\0'; |
||||
setenv ("lcd", var); |
||||
*p = '\r'; |
||||
} |
||||
} |
||||
} |
@ -1,221 +0,0 @@ |
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
#include <pcmcia.h> |
||||
|
||||
#undef CONFIG_PCMCIA |
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA) |
||||
#define CONFIG_PCMCIA |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) |
||||
#define CONFIG_PCMCIA |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCMCIA |
||||
|
||||
#define PCMCIA_BOARD_MSG "KUP" |
||||
|
||||
#define KUP4K_PCMCIA_B_3V3 (0x00020000) |
||||
|
||||
int pcmcia_hardware_enable(int slot) |
||||
{ |
||||
volatile cpm8xx_t *cp; |
||||
volatile pcmconf8xx_t *pcmp; |
||||
volatile sysconf8xx_t *sysp; |
||||
uint reg, mask; |
||||
|
||||
debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); |
||||
|
||||
udelay(10000); |
||||
|
||||
sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); |
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); |
||||
cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); |
||||
|
||||
/*
|
||||
* Configure SIUMCR to enable PCMCIA port B |
||||
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead) |
||||
*/ |
||||
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ |
||||
|
||||
/* clear interrupt state, and disable interrupts */ |
||||
pcmp->pcmc_pscr = PCMCIA_MASK(slot); |
||||
pcmp->pcmc_per &= ~PCMCIA_MASK(slot); |
||||
|
||||
/*
|
||||
* Disable interrupts, DMA, and PCMCIA buffers |
||||
* (isolate the interface) and assert RESET signal |
||||
*/ |
||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
||||
reg = 0; |
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(slot) = reg; |
||||
udelay(2500); |
||||
|
||||
/*
|
||||
* Configure Port B pins for |
||||
* 3 Volts enable |
||||
*/ |
||||
if (slot) { /* Slot A is built-in */ |
||||
cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; |
||||
cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; |
||||
/* remove all power */ |
||||
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ |
||||
} |
||||
/*
|
||||
* Make sure there is a card in the slot, then configure the interface. |
||||
*/ |
||||
udelay(10000); |
||||
debug ("[%d] %s: PIPR(%p)=0x%x\n", |
||||
__LINE__,__FUNCTION__, |
||||
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr); |
||||
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { |
||||
printf (" No Card found\n"); |
||||
return (1); |
||||
} |
||||
|
||||
/*
|
||||
* Power On. |
||||
*/ |
||||
printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot); |
||||
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); |
||||
reg = pcmp->pcmc_pipr; |
||||
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", |
||||
reg, |
||||
(reg&PCMCIA_VS1(slot))?"n":"ff", |
||||
(reg&PCMCIA_VS2(slot))?"n":"ff"); |
||||
if ((reg & mask) == mask) { |
||||
puts (" 5.0V card found: NOT SUPPORTED !!!\n"); |
||||
} else { |
||||
if(slot) |
||||
cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; |
||||
puts (" 3.3V card found: "); |
||||
} |
||||
#if 0 |
||||
/* VCC switch error flag, PCMCIA slot INPACK_ pin */ |
||||
cp->cp_pbdir &= ~(0x0020 | 0x0010); |
||||
cp->cp_pbpar &= ~(0x0020 | 0x0010); |
||||
udelay(500000); |
||||
#endif |
||||
debug ("Enable PCMCIA buffers and stop RESET\n"); |
||||
reg = PCMCIA_PGCRX(slot); |
||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(slot) = reg; |
||||
|
||||
udelay(250000); /* some cards need >150 ms to come up :-( */ |
||||
|
||||
debug ("# hardware_enable done\n"); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA) |
||||
int pcmcia_hardware_disable(int slot) |
||||
{ |
||||
volatile immap_t *immap; |
||||
volatile cpm8xx_t *cp; |
||||
volatile pcmconf8xx_t *pcmp; |
||||
u_long reg; |
||||
|
||||
debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); |
||||
|
||||
immap = (immap_t *)CONFIG_SYS_IMMR; |
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); |
||||
cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); |
||||
|
||||
/* remove all power */ |
||||
if (slot) |
||||
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; |
||||
|
||||
/* Configure PCMCIA General Control Register */ |
||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
||||
reg = 0; |
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(slot) = reg; |
||||
|
||||
udelay(10000); |
||||
|
||||
return (0); |
||||
} |
||||
#endif |
||||
|
||||
|
||||
int pcmcia_voltage_set(int slot, int vcc, int vpp) |
||||
{ |
||||
volatile cpm8xx_t *cp; |
||||
volatile pcmconf8xx_t *pcmp; |
||||
u_long reg; |
||||
|
||||
debug ("voltage_set: " \
|
||||
PCMCIA_BOARD_MSG \
|
||||
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", |
||||
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); |
||||
|
||||
if (!slot) /* Slot A is not configurable */ |
||||
return 0; |
||||
|
||||
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); |
||||
cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); |
||||
|
||||
/*
|
||||
* Disable PCMCIA buffers (isolate the interface) |
||||
* and assert RESET signal |
||||
*/ |
||||
debug ("Disable PCMCIA buffers and assert RESET\n"); |
||||
reg = PCMCIA_PGCRX(slot); |
||||
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(slot) = reg; |
||||
udelay(500); |
||||
|
||||
debug ("PCMCIA power OFF\n"); |
||||
/*
|
||||
* Configure Port B pins for |
||||
* 3 Volts enable |
||||
*/ |
||||
cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; |
||||
cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; |
||||
/* remove all power */ |
||||
cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ |
||||
|
||||
switch(vcc) { |
||||
case 0: break; |
||||
case 33: |
||||
cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; |
||||
debug ("PCMCIA powered at 3.3V\n"); |
||||
break; |
||||
case 50: |
||||
debug ("PCMCIA: 5Volt vcc not supported\n"); |
||||
break; |
||||
default: |
||||
puts("PCMCIA: vcc not supported"); |
||||
break; |
||||
} |
||||
udelay(10000); |
||||
/* Checking supported voltages */ |
||||
|
||||
debug ("PIPR: 0x%x --> %s\n", |
||||
pcmp->pcmc_pipr, |
||||
(pcmp->pcmc_pipr & (0x80000000 >> (slot << 4))) |
||||
? "only 5 V --> NOT SUPPORTED" |
||||
: "can do 3.3V"); |
||||
|
||||
|
||||
debug ("Enable PCMCIA buffers and stop RESET\n"); |
||||
reg = PCMCIA_PGCRX(slot); |
||||
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ |
||||
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ |
||||
PCMCIA_PGCRX(slot) = reg; |
||||
udelay(500); |
||||
|
||||
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", |
||||
slot+'A'); |
||||
return (0); |
||||
} |
||||
|
||||
#endif /* CONFIG_PCMCIA */ |
@ -1,12 +0,0 @@ |
||||
if TARGET_KUP4K |
||||
|
||||
config SYS_BOARD |
||||
default "kup4k" |
||||
|
||||
config SYS_VENDOR |
||||
default "kup" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "KUP4K" |
||||
|
||||
endif |
@ -1,6 +0,0 @@ |
||||
KUP4K BOARD |
||||
M: Klaus Heydeck <heydeck@kieback-peter.de> |
||||
S: Maintained |
||||
F: board/kup/kup4k/ |
||||
F: include/configs/KUP4K.h |
||||
F: configs/KUP4K_defconfig |
@ -1,8 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = kup4k.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
|
@ -1,289 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <libfdt.h> |
||||
#include <mpc8xx.h> |
||||
#include <hwconfig.h> |
||||
#include <i2c.h> |
||||
#include "../common/kup.h" |
||||
#include <asm/io.h> |
||||
|
||||
static unsigned char swapbyte(unsigned char c); |
||||
static int read_diag(void); |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* ----------------------------------------------------------------------- */ |
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF |
||||
|
||||
const uint sdram_table[] = { |
||||
/*
|
||||
* Single Read. (Offset 0 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, |
||||
0x1FF77C47, /* last */ |
||||
|
||||
/*
|
||||
* SDRAM Initialization (offset 5 in UPMA RAM) |
||||
* |
||||
* This is no UPM entry point. The following definition uses |
||||
* the remaining space to establish an initialization |
||||
* sequence, which is executed by a RUN command. |
||||
* |
||||
*/ |
||||
0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ |
||||
|
||||
/*
|
||||
* Burst Read. (Offset 8 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM) |
||||
*/ |
||||
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Burst Write. (Offset 20 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Refresh (Offset 30 in UPMA RAM) |
||||
*/ |
||||
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0xFFFFFC84, 0xFFFFFC07, /* last */ |
||||
_NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Exception. (Offset 3c in UPMA RAM) |
||||
*/ |
||||
0x7FFFFC07, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
}; |
||||
|
||||
/* ----------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
*/ |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
uchar rev,mod,tmp,pcf,ak_rev,ak_mod; |
||||
|
||||
/*
|
||||
* Init ChipSelect #4 (CAN + HW-Latch) |
||||
*/ |
||||
out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); |
||||
out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); |
||||
|
||||
/*
|
||||
* Init ChipSelect #5 (S1D13768) |
||||
*/ |
||||
out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5); |
||||
out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5); |
||||
|
||||
tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR)); |
||||
rev = (tmp & 0xF8) >> 3; |
||||
mod = (tmp & 0x07); |
||||
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
||||
|
||||
if (read_diag()) |
||||
gd->flags &= ~GD_FLG_SILENT; |
||||
|
||||
printf("Board: KUP4K Rev %d.%d AK:",rev,mod); |
||||
/*
|
||||
* TI Application report: Before using the IO as an input, |
||||
* a high must be written to the IO first |
||||
*/ |
||||
pcf = 0xFF; |
||||
i2c_write(0x21, 0, 0 , &pcf, 1); |
||||
if (i2c_read(0x21, 0, 0, &pcf, 1)) { |
||||
puts("n/a\n"); |
||||
} else { |
||||
ak_rev = (pcf & 0xF8) >> 3; |
||||
ak_mod = (pcf & 0x07); |
||||
printf("%d.%d\n", ak_rev, ak_mod); |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
/* ----------------------------------------------------------------------- */ |
||||
|
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
long int size = 0; |
||||
uchar *latch, rev, tmp; |
||||
|
||||
/*
|
||||
* Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision |
||||
* Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB |
||||
*/ |
||||
out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); |
||||
out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); |
||||
|
||||
latch = (uchar *)0x90000200; |
||||
tmp = swapbyte(*latch); |
||||
rev = (tmp & 0xF8) >> 3; |
||||
|
||||
upmconfig(UPMA, (uint *) sdram_table, |
||||
sizeof (sdram_table) / sizeof (uint)); |
||||
|
||||
out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); |
||||
|
||||
out_be32(&memctl->memc_mar, 0x00000088); |
||||
/* no refresh yet */ |
||||
if(rev >= 7) { |
||||
out_be32(&memctl->memc_mamr, |
||||
CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE))); |
||||
} else { |
||||
out_be32(&memctl->memc_mamr, |
||||
CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE))); |
||||
} |
||||
|
||||
udelay(200); |
||||
|
||||
/* perform SDRAM initializsation sequence */ |
||||
|
||||
/* SDRAM bank 0 */ |
||||
out_be32(&memctl->memc_mcr, 0x80002105); |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */ |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ |
||||
udelay(1); |
||||
|
||||
/* SDRAM bank 1 */ |
||||
out_be32(&memctl->memc_mcr, 0x80004105); |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */ |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ |
||||
udelay(1); |
||||
|
||||
/* SDRAM bank 2 */ |
||||
out_be32(&memctl->memc_mcr, 0x80006105); |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */ |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ |
||||
udelay(1); |
||||
|
||||
setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ |
||||
udelay(1000); |
||||
|
||||
out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); |
||||
udelay(1000); |
||||
if(rev >= 7) { |
||||
size = 32 * 3 * 1024 * 1024; |
||||
out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL); |
||||
out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL); |
||||
out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL); |
||||
out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL); |
||||
out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL); |
||||
out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL); |
||||
} else { |
||||
size = 16 * 3 * 1024 * 1024; |
||||
out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL); |
||||
out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL); |
||||
out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL); |
||||
out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL); |
||||
out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL); |
||||
out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL); |
||||
} |
||||
return (size); |
||||
} |
||||
|
||||
/* ----------------------------------------------------------------------- */ |
||||
|
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
|
||||
#ifdef CONFIG_IDE_LED |
||||
/* Configure PA8 as output port */ |
||||
setbits_be16(&immap->im_ioport.iop_padir, PA_8); |
||||
setbits_be16(&immap->im_ioport.iop_paodr, PA_8); |
||||
clrbits_be16(&immap->im_ioport.iop_papar, PA_8); |
||||
setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */ |
||||
#endif |
||||
load_sernum_ethaddr(); |
||||
setenv("hw","4k"); |
||||
poweron_key(); |
||||
return (0); |
||||
} |
||||
|
||||
|
||||
static int read_diag(void) |
||||
{ |
||||
int diag; |
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
||||
|
||||
clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */ |
||||
clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ |
||||
setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */ |
||||
clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ |
||||
setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */ |
||||
udelay(500); |
||||
if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) { |
||||
clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */ |
||||
udelay(500); |
||||
if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4) |
||||
diag = 0; |
||||
else |
||||
diag = 1; |
||||
} else { |
||||
diag = 0; |
||||
} |
||||
clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */ |
||||
return (diag); |
||||
} |
||||
|
||||
static unsigned char swapbyte(unsigned char c) |
||||
{ |
||||
unsigned char result = 0; |
||||
int i = 0; |
||||
|
||||
for(i = 0; i < 8; ++i) { |
||||
result = result << 1; |
||||
result |= (c & 1); |
||||
c = c >> 1; |
||||
} |
||||
return result; |
||||
} |
||||
|
||||
/*
|
||||
* Device Tree Support |
||||
*/ |
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) |
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ |
@ -1,121 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib/vsprintf.o (.text) |
||||
lib/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/env_embedded.o(.text) |
||||
|
||||
*(.text) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,12 +0,0 @@ |
||||
if TARGET_KUP4X |
||||
|
||||
config SYS_BOARD |
||||
default "kup4x" |
||||
|
||||
config SYS_VENDOR |
||||
default "kup" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "KUP4X" |
||||
|
||||
endif |
@ -1,6 +0,0 @@ |
||||
KUP4X BOARD |
||||
M: Klaus Heydeck <heydeck@kieback-peter.de> |
||||
S: Maintained |
||||
F: board/kup/kup4x/ |
||||
F: include/configs/KUP4X.h |
||||
F: configs/KUP4X_defconfig |
@ -1,8 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = kup4x.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
|
@ -1,185 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
#include <post.h> |
||||
#include "../common/kup.h" |
||||
#include <asm/io.h> |
||||
|
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF |
||||
|
||||
const uint sdram_table[] = { |
||||
/*
|
||||
* Single Read. (Offset 0 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, |
||||
0x1FF77C47, /* last */ |
||||
|
||||
/*
|
||||
* SDRAM Initialization (offset 5 in UPMA RAM) |
||||
* |
||||
* This is no UPM entry point. The following definition uses |
||||
* the remaining space to establish an initialization |
||||
* sequence, which is executed by a RUN command. |
||||
* |
||||
*/ |
||||
0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ |
||||
|
||||
/*
|
||||
* Burst Read. (Offset 8 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM) |
||||
*/ |
||||
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Burst Write. (Offset 20 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Refresh (Offset 30 in UPMA RAM) |
||||
*/ |
||||
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0xFFFFFC84, 0xFFFFFC07, /* last */ |
||||
_NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Exception. (Offset 3c in UPMA RAM) |
||||
*/ |
||||
0x7FFFFC07, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
}; |
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
*/ |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
uchar latch, rev, mod; |
||||
|
||||
/*
|
||||
* Init ChipSelect #4 (CAN + HW-Latch) |
||||
*/ |
||||
out_be32(&memctl->memc_or4, 0xFFFF8926); |
||||
out_be32(&memctl->memc_br4, 0x90000401); |
||||
|
||||
latch = in_8( (unsigned char *) LATCH_ADDR); |
||||
rev = (latch & 0xF8) >> 3; |
||||
mod = (latch & 0x03); |
||||
|
||||
printf("Board: KUP4X Rev %d.%d\n", rev, mod); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
|
||||
upmconfig(UPMA, (uint *) sdram_table, |
||||
sizeof (sdram_table) / sizeof (uint)); |
||||
|
||||
out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); |
||||
|
||||
out_be32(&memctl->memc_mar, 0x00000088); |
||||
|
||||
out_be32(&memctl->memc_mamr, |
||||
CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */ |
||||
|
||||
udelay(200); |
||||
|
||||
/* perform SDRAM initializsation sequence */ |
||||
|
||||
/* SDRAM bank 0 */ |
||||
out_be32(&memctl->memc_mcr, 0x80002105); |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */ |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ |
||||
udelay(1); |
||||
|
||||
/* SDRAM bank 1 */ |
||||
out_be32(&memctl->memc_mcr, 0x80004105); |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */ |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ |
||||
udelay(1); |
||||
|
||||
/* SDRAM bank 2 */ |
||||
out_be32(&memctl->memc_mcr, 0x80006105); |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */ |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ |
||||
udelay(1); |
||||
|
||||
/* SDRAM bank 3 */ |
||||
out_be32(&memctl->memc_mcr, 0x8000C105); |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x8000C830); /* execute twice */ |
||||
udelay(1); |
||||
out_be32(&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */ |
||||
udelay(1); |
||||
|
||||
setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ |
||||
|
||||
udelay(1000); |
||||
/* 4 x 16 MB */ |
||||
out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); |
||||
udelay(1000); |
||||
out_be32(&memctl->memc_or1, 0xFF000A00); |
||||
out_be32(&memctl->memc_br1, 0x00000081); |
||||
out_be32(&memctl->memc_or2, 0xFE000A00); |
||||
out_be32(&memctl->memc_br2, 0x01000081); |
||||
out_be32(&memctl->memc_or3, 0xFD000A00); |
||||
out_be32(&memctl->memc_br3, 0x02000081); |
||||
out_be32(&memctl->memc_or6, 0xFC000A00); |
||||
out_be32(&memctl->memc_br6, 0x03000081); |
||||
udelay(10000); |
||||
|
||||
return (4 * 16 * 1024 * 1024); |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
|
||||
#ifdef CONFIG_IDE_LED |
||||
/* Configure PA8 as output port */ |
||||
setbits_be16(&immap->im_ioport.iop_padir, PA_8); |
||||
setbits_be16(&immap->im_ioport.iop_paodr, PA_8); |
||||
clrbits_be16(&immap->im_ioport.iop_papar, PA_8); |
||||
setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */ |
||||
#endif |
||||
load_sernum_ethaddr(); |
||||
setenv("hw", "4x"); |
||||
poweron_key(); |
||||
return 0; |
||||
} |
@ -1,82 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.text : |
||||
{ |
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
||||
|
||||
*(.text*) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
_GOT2_TABLE_ = .; |
||||
KEEP(*(.got2)) |
||||
KEEP(*(.got)) |
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
||||
_FIXUP_TABLE_ = .; |
||||
KEEP(*(.fixup)) |
||||
} |
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data*) |
||||
*(.sdata*) |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,121 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib/vsprintf.o (.text) |
||||
lib/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/env_embedded.o(.text) |
||||
|
||||
*(.text) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,3 +0,0 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_8xx=y |
||||
CONFIG_TARGET_KUP4K=y |
@ -1,3 +0,0 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_8xx=y |
||||
CONFIG_TARGET_KUP4X=y |
@ -1,488 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
* Derived from ../tqm8xx/tqm8xx.c |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ |
||||
#define CONFIG_KUP4K 1 /* ...on a KUP4K module */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate */ |
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \
|
||||
"run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \
|
||||
"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \
|
||||
"run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \
|
||||
"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \
|
||||
"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \
|
||||
bootm 400000 \0" \
|
||||
"panic_boot=echo No Bootdevice !!! reset\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \
|
||||
":${netmask}:${hostname}:${netdev}:off\0" \
|
||||
"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \
|
||||
hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \
|
||||
"console=ttyCPM0,115200\0" \
|
||||
"netdev=eth0\0" \
|
||||
"contrast=20\0" \
|
||||
"silent=1\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
|
||||
"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \
|
||||
"cp.b 200000 40050000 14000\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot" |
||||
|
||||
#define CONFIG_PREBOOT "setenv preboot; saveenv" |
||||
|
||||
#define CONFIG_MISC_INIT_R 1 |
||||
#define CONFIG_MISC_INIT_F 1 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#define CONFIG_WATCHDOG 1 /* watchdog enabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/*
|
||||
* enable I2C and select the hardware/software driver |
||||
*/ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE |
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL 0x00000020 /* PB 26 */ |
||||
#define PB_SDA 0x00000010 /* PB 27 */ |
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
||||
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ |
||||
|
||||
/* List of I2C addresses to be verified by POST */ |
||||
|
||||
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \ |
||||
CONFIG_SYS_I2C_RTC_ADDR, \
|
||||
} |
||||
|
||||
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ |
||||
|
||||
#define CONFIG_SYS_DISCOVER_PHY |
||||
#define CONFIG_MII |
||||
|
||||
/* Define to allow the user to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_SNTP |
||||
|
||||
#ifdef CONFIG_POST |
||||
#define CONFIG_CMD_DIAG |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
||||
#endif |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */ |
||||
#define CONFIG_SYS_ALT_MEMTEST 1 |
||||
#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } |
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Dynamic MTD partition support |
||||
*/ |
||||
#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \ |
||||
"64k(env)," \
|
||||
"128k(splash)," \
|
||||
"512k(etc)," \
|
||||
"64k(hw-info)" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
* |
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! |
||||
*/ |
||||
#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF00 |
||||
#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
|
||||
/* KUP4K use both slots, SLOT_A as "primary". */ |
||||
#define CONFIG_PCMCIA_SLOT_A 1 |
||||
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
#define PCMCIA_SOCKETS_NO 2 |
||||
#define PCMCIA_MEM_WIN_NO 8 |
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#define CONFIG_IDE_LED 1 /* LED for ide supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 2 |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 4 |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: |
||||
*/ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \ |
||||
OR_SCY_5_CLK | OR_EHTR | OR_BI) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP \ |
||||
(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM \ |
||||
(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM \ |
||||
((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
* |
||||
* The Divider for PTA (refresh timer) configuration is based on an |
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to |
||||
* the number of chip selects (NCS) and the actually needed refresh |
||||
* rate is done by setting MPTPR. |
||||
* |
||||
* PTA is calculated from |
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
||||
* |
||||
* gclk CPU clock (not bus clock!) |
||||
* Trefresh Refresh cycle * 4 (four word bursts used) |
||||
* |
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
* -------------------------------------------- |
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
||||
* |
||||
* 50 MHz => 50.000.000 / Divider = 98 |
||||
* 66 Mhz => 66.000.000 / Divider = 129 |
||||
* 80 Mhz => 80.000.000 / Divider = 156 |
||||
*/ |
||||
#if defined(CONFIG_80MHz) |
||||
#define CONFIG_SYS_MAMR_PTA 156 |
||||
#elif defined(CONFIG_66MHz) |
||||
#define CONFIG_SYS_MAMR_PTA 129 |
||||
#else /* 50 MHz */ |
||||
#define CONFIG_SYS_MAMR_PTA 98 |
||||
#endif /*CONFIG_??MHz */ |
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us |
||||
* (= 64 ms / 2K = 125 / quad bursts). |
||||
* For a simpler initialization, 15.6 us is used instead. |
||||
* |
||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
||||
*/ |
||||
#define CONFIG_SYS_MPTPR 0x400 |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL 0x68802114 |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL 0x68904114 |
||||
|
||||
/*
|
||||
* Chip Selects |
||||
*/ |
||||
#define CONFIG_SYS_OR0 |
||||
#define CONFIG_SYS_BR0 |
||||
|
||||
#define CONFIG_SYS_OR1_8COL 0xFF000A00 |
||||
#define CONFIG_SYS_BR1_8COL 0x00000081 |
||||
#define CONFIG_SYS_OR2_8COL 0xFE000A00 |
||||
#define CONFIG_SYS_BR2_8COL 0x01000081 |
||||
#define CONFIG_SYS_OR3_8COL 0xFC000A00 |
||||
#define CONFIG_SYS_BR3_8COL 0x02000081 |
||||
|
||||
#define CONFIG_SYS_OR1_9COL 0xFE000A00 |
||||
#define CONFIG_SYS_BR1_9COL 0x00000081 |
||||
#define CONFIG_SYS_OR2_9COL 0xFE000A00 |
||||
#define CONFIG_SYS_BR2_9COL 0x02000081 |
||||
#define CONFIG_SYS_OR3_9COL 0xFE000A00 |
||||
#define CONFIG_SYS_BR3_9COL 0x04000081 |
||||
|
||||
#define CONFIG_SYS_OR4 0xFFFF8926 |
||||
#define CONFIG_SYS_BR4 0x90000401 |
||||
|
||||
#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */ |
||||
#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */ |
||||
|
||||
#define LATCH_ADDR 0x90000200 |
||||
|
||||
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
||||
#define CONFIG_AUTOBOOT_STOP_STR "." |
||||
#define CONFIG_SILENT_CONSOLE 1 |
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ |
||||
#define CONFIG_VERSION_VARIABLE 1 |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -1,440 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2005 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
* Derived from ../tqm8xx/tqm8xx.c |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ |
||||
#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate */ |
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */ |
||||
#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */ |
||||
|
||||
|
||||
#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT)) |
||||
|
||||
/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ |
||||
/* in general, we always know this for FADS+new ADS anyway */ |
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ |
||||
|
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
|
||||
"run addhw;diskboot 200000 0:1;bootm 200000\0" \
|
||||
"usb_boot=setenv bootargs root=/dev/sda2 ip=off; \
|
||||
run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1; \
|
||||
usb stop; bootm 200000\0" \
|
||||
"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
|
||||
"panic_boot=echo No Bootdevice !!! reset\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
|
||||
":${netmask}:${hostname}:${netdev}:off\0" \
|
||||
"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
|
||||
"netdev=eth0\0" \
|
||||
"silent=1\0" \
|
||||
"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
|
||||
"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \
|
||||
"cp.b 200000 40040000 14000\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot" |
||||
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1 |
||||
#define CONFIG_MISC_INIT_F 1 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#define CONFIG_WATCHDOG 1 /* watchdog enabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/*
|
||||
* enable I2C and select the hardware/software driver |
||||
*/ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
||||
|
||||
#ifdef CONFIG_SYS_I2C_SOFT |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE |
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL 0x00000020 /* PB 26 */ |
||||
#define PB_SDA 0x00000010 /* PB 27 */ |
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
||||
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
||||
#endif /* CONFIG_SYS_I2C_SOFT */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ |
||||
|
||||
|
||||
/* List of I2C addresses to be verified by POST */ |
||||
|
||||
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \ |
||||
CONFIG_SYS_I2C_RTC_ADDR, \
|
||||
} |
||||
|
||||
|
||||
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ |
||||
|
||||
#define CONFIG_SYS_DISCOVER_PHY |
||||
#define CONFIG_MII |
||||
|
||||
#undef CONFIG_KUP4K_LOGO |
||||
|
||||
/* Define to allow the user to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
|
||||
/* POST support */ |
||||
#define CONFIG_POST (CONFIG_SYS_POST_CPU | \ |
||||
CONFIG_SYS_POST_RTC | \
|
||||
CONFIG_SYS_POST_I2C) |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_SNTP |
||||
#define CONFIG_CMD_USB |
||||
|
||||
#ifdef CONFIG_POST |
||||
#define CONFIG_CMD_DIAG |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } |
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#if 0 |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#if 1 |
||||
#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */ |
||||
#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */ |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* set the PLL, the low-power modes and the reset control (15-29) |
||||
*/ |
||||
#define CONFIG_SYS_PLPRCR ((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) | \ |
||||
PLPRCR_SPLSS | PLPRCR_TEXPS) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF00 |
||||
#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
|
||||
/* KUP4K use both slots, SLOT_A as "primary". */ |
||||
#define CONFIG_PCMCIA_SLOT_A 1 |
||||
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
#define PCMCIA_SOCKETS_NO 1 |
||||
#define PCMCIA_MEM_WIN_NO 8 |
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#define CONFIG_IDE_LED 1 /* LED for ide supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 2 |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: |
||||
*/ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP \ |
||||
(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM \ |
||||
(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM \ |
||||
((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x400 |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
#define CONFIG_SYS_MAMR 0x80802114 |
||||
|
||||
|
||||
/*
|
||||
* Chip Selects |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_OR4 0xFFFF8926 |
||||
#define CONFIG_SYS_BR4 0x90000401 |
||||
|
||||
#define LATCH_ADDR 0x90000200 |
||||
|
||||
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
||||
|
||||
#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ |
||||
#define CONFIG_SILENT_CONSOLE 1 |
||||
|
||||
#define CONFIG_USB_STORAGE 1 |
||||
#define CONFIG_USB_SL811HS 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue