@ -118,165 +118,187 @@ struct socfpga_clock_manager {
u32 _pad_0xe8_0x200 [ 70 ] ;
} ;
# define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
# define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
# define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
# define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
# define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
# define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
# define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
# define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
# define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
# define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
# define CLKMGR_CTRL_SAFEMODE (1 << 0)
# define CLKMGR_CTRL_SAFEMODE_OFFSET 0
# define CLKMGR_BYPASS_PERPLLSRC (1 << 4)
# define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
# define CLKMGR_BYPASS_PERPLL (1 << 3)
# define CLKMGR_BYPASS_PERPLL_OFFSET 3
# define CLKMGR_BYPASS_SDRPLLSRC (1 << 2)
# define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
# define CLKMGR_BYPASS_SDRPLL (1 << 1)
# define CLKMGR_BYPASS_SDRPLL_OFFSET 1
# define CLKMGR_BYPASS_MAINPLL (1 << 0)
# define CLKMGR_BYPASS_MAINPLL_OFFSET 0
# define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
# define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
# define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
# define CLKMGR_STAT_BUSY (1 << 0)
/* Main PLL */
# define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
# define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
# define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
# define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
# define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
# define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
# define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
# define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
# define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
# define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
# define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
# define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
# define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
# define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
# define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
# define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
# define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
# define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
# define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
# define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7)
# define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
# define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
# define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
# define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
# define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
# define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1)
# define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
# define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
# define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
# define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
# define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0)
# define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
# define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
# define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
# define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1)
# define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
# define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
# define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
# define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
# define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2)
# define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
# define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
# define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
# define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
# define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
# define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
# define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
# define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
# define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
# define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
# define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
# define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
# define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
# define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
# define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
# define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
# define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
# define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
# define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
# define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
# define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
# define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
# define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
# define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
# define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
# define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
# define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
# define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
# define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
# define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
# define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
# define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
# define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
# define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
# define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
# define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0)
# define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
# define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1)
# define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
# define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
# define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
# define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
/* Per PLL */
# define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
# define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
# define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
# define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
# define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
# define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
# define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
# define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
# define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
# define CLKMGR_VCO_SSRC_EOSC1 0x0
# define CLKMGR_VCO_SSRC_EOSC2 0x1
# define CLKMGR_VCO_SSRC_F2S 0x2
# define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
# define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
# define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
# define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
# define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
# define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
# define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
# define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
# define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
# define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4)
# define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
# define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
# define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0)
# define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
# define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
# define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
# define CLKMGR_SDMMC_CLK_SRC_PER 0x2
# define CLKMGR_QSPI_CLK_SRC_F2S 0x0
# define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
# define CLKMGR_QSPI_CLK_SRC_PER 0x2
# define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
# define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
# define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
# define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
# define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
# define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
# define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
# define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
# define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
# define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
# define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
# define CLKMGR_VCO_SSRC_EOSC1 0x0
# define CLKMGR_VCO_SSRC_EOSC2 0x1
# define CLKMGR_VCO_SSRC_F2S 0x2
# define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
# define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
# define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
# define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
# define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
# define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
# define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
# define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
# define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
# define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
# define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
# define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
# define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
# define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
# define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
# define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
# define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
# define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
# define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
# define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
# define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
# define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
# define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
# define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
# define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
# define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
# define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
# define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
# define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
# define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
# define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
# define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
# define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
# define CLKMGR_SDMMC_CLK_SRC_PER 0x2
# define CLKMGR_QSPI_CLK_SRC_F2S 0x0
# define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
# define CLKMGR_QSPI_CLK_SRC_PER 0x2
/* SDR PLL */
# define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
# define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
# define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
# define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
# define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
# define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
# define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
# define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
# define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
# define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
# define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
# define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
# define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0)
# define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
# define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
# define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
# define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
# define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
# define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
# define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
# define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
# define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
# define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
# define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
# define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
# define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
# define MAIN_VCO_BASE \
( CLKMGR_MAINPLLGRP_VCO_DENOM_SET ( CONFIG_HPS_MAINPLLGRP_VCO_DENOM ) | \
CLKMGR_MAINPLLGRP_VCO_NUMER_SET ( CONFIG_HPS_MAINPLLGRP_VCO_NUMER ) )
# define PERI_VCO_BASE \
( CLKMGR_PERPLLGRP_VCO_PSRC_SET ( CONFIG_HPS_PERPLLGRP_VCO_PSRC ) | \
CLKMGR_PERPLLGRP_VCO_DENOM_SET ( CONFIG_HPS_PERPLLGRP_VCO_DENOM ) | \
CLKMGR_PERPLLGRP_VCO_NUMER_SET ( CONFIG_HPS_PERPLLGRP_VCO_NUMER ) )
# define SDR_VCO_BASE \
( CLKMGR_SDRPLLGRP_VCO_SSRC_SET ( CONFIG_HPS_SDRPLLGRP_VCO_SSRC ) | \
CLKMGR_SDRPLLGRP_VCO_DENOM_SET ( CONFIG_HPS_SDRPLLGRP_VCO_DENOM ) | \
CLKMGR_SDRPLLGRP_VCO_NUMER_SET ( CONFIG_HPS_SDRPLLGRP_VCO_NUMER ) )
# define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
# define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
# define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
# define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
# define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24)
# define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
# define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
# define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
# define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
# define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
# define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
# define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
# define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
# define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
# define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
# define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
# define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
# define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
# define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
# define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
# define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
# define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
# define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
# define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
# define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
# define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
# define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
# define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
# endif /* _CLOCK_MANAGER_H_ */
Marek Vasut
10 years ago