This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini <trini@konsulko.com>lime2-spi
Tom Rini
6 years ago
committed by
Stefano Babic
parent
bcca8aa9ee
commit
448fc44fb8
@ -1,15 +0,0 @@ |
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if TARGET_MX31ADS |
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config SYS_BOARD |
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default "mx31ads" |
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config SYS_VENDOR |
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default "freescale" |
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config SYS_SOC |
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default "mx31" |
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config SYS_CONFIG_NAME |
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default "mx31ads" |
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endif |
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@ -1,6 +0,0 @@ |
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MX31ADS BOARD |
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#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
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S: Orphan (since 2013-09) |
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F: board/freescale/mx31ads/ |
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F: include/configs/mx31ads.h |
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F: configs/mx31ads_defconfig |
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@ -1,8 +0,0 @@ |
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#
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# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx31ads.o
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obj-y += lowlevel_init.o
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@ -1,268 +0,0 @@ |
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/* |
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* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/imx-regs.h> |
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|
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.macro REG reg, val |
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ldr r2, =\reg |
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ldr r3, =\val |
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str r3, [r2] |
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.endm |
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|
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.macro REG8 reg, val |
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ldr r2, =\reg |
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ldr r3, =\val |
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strb r3, [r2] |
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.endm |
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|
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.macro DELAY loops |
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ldr r2, =\loops |
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1: |
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subs r2, r2, #1 |
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nop |
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bcs 1b |
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.endm |
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|
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/* RedBoot: AIPS setup - Only setup MPROTx registers. |
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* The PACR default values are good.*/ |
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.macro init_aips
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/* |
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* Set all MPROTx to be non-bufferable, trusted for R/W, |
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* not forced to user-mode. |
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*/ |
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ldr r0, =0x43F00000 |
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ldr r1, =0x77777777 |
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str r1, [r0, #0x00] |
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str r1, [r0, #0x04] |
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ldr r0, =0x53F00000 |
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str r1, [r0, #0x00] |
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str r1, [r0, #0x04] |
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|
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/* |
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* Clear the on and off peripheral modules Supervisor Protect bit |
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* for SDMA to access them. Did not change the AIPS control registers |
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* (offset 0x20) access type |
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*/ |
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ldr r0, =0x43F00000 |
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ldr r1, =0x0 |
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str r1, [r0, #0x40] |
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str r1, [r0, #0x44] |
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str r1, [r0, #0x48] |
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str r1, [r0, #0x4C] |
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ldr r1, [r0, #0x50] |
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and r1, r1, #0x00FFFFFF |
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str r1, [r0, #0x50] |
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ldr r0, =0x53F00000 |
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ldr r1, =0x0 |
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str r1, [r0, #0x40] |
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str r1, [r0, #0x44] |
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str r1, [r0, #0x48] |
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str r1, [r0, #0x4C] |
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ldr r1, [r0, #0x50] |
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and r1, r1, #0x00FFFFFF |
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str r1, [r0, #0x50] |
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.endm /* init_aips */ |
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|
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/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ |
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.macro init_max
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ldr r0, =0x43F04000 |
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ |
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ldr r1, =0x00302154 |
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str r1, [r0, #0x000] /* for S0 */ |
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str r1, [r0, #0x100] /* for S1 */ |
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str r1, [r0, #0x200] /* for S2 */ |
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str r1, [r0, #0x300] /* for S3 */ |
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str r1, [r0, #0x400] /* for S4 */ |
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/* SGPCR - always park on last master */ |
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ldr r1, =0x10 |
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str r1, [r0, #0x010] /* for S0 */ |
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str r1, [r0, #0x110] /* for S1 */ |
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str r1, [r0, #0x210] /* for S2 */ |
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str r1, [r0, #0x310] /* for S3 */ |
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str r1, [r0, #0x410] /* for S4 */ |
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/* MGPCR - restore default values */ |
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ldr r1, =0x0 |
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str r1, [r0, #0x800] /* for M0 */ |
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str r1, [r0, #0x900] /* for M1 */ |
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str r1, [r0, #0xA00] /* for M2 */ |
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str r1, [r0, #0xB00] /* for M3 */ |
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str r1, [r0, #0xC00] /* for M4 */ |
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str r1, [r0, #0xD00] /* for M5 */ |
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.endm /* init_max */ |
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|
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/* RedBoot: M3IF setup */ |
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.macro init_m3if
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/* Configure M3IF registers */ |
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ldr r1, =0xB8003000 |
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/* |
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* M3IF Control Register (M3IFCTL) |
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 |
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 |
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 |
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 |
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 |
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 |
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 |
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 |
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* ------------ |
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* 0x00000040 |
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*/ |
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ldr r0, =0x00000040 |
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str r0, [r1] /* M3IF control reg */ |
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.endm /* init_m3if */ |
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/* RedBoot: To support 133MHz DDR */ |
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.macro init_drive_strength
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/* |
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* Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits |
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* in SW_PAD_CTL registers |
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*/ |
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/* SDCLK */ |
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ldr r1, =0x43FAC200 |
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ldr r0, [r1, #0x6C] |
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bic r0, r0, #(1 << 12) |
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str r0, [r1, #0x6C] |
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/* CAS */ |
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ldr r0, [r1, #0x70] |
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bic r0, r0, #(1 << 22) |
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str r0, [r1, #0x70] |
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/* RAS */ |
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ldr r0, [r1, #0x74] |
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bic r0, r0, #(1 << 2) |
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str r0, [r1, #0x74] |
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/* CS2 (CSD0) */ |
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ldr r0, [r1, #0x7C] |
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bic r0, r0, #(1 << 22) |
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str r0, [r1, #0x7C] |
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/* DQM3 */ |
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ldr r0, [r1, #0x84] |
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bic r0, r0, #(1 << 22) |
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str r0, [r1, #0x84] |
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/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ |
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ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ |
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pad_loop: |
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ldr r0, [r1, #0x88] |
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bic r0, r0, #(1 << 22) |
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bic r0, r0, #(1 << 12) |
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bic r0, r0, #(1 << 2) |
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str r0, [r1, #0x88] |
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add r1, r1, #4 |
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subs r2, r2, #0x1 |
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bne pad_loop |
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.endm /* init_drive_strength */ |
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/* CPLD on CS4 setup */ |
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.macro init_cs4
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ldr r0, =WEIM_BASE |
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ldr r1, =0x0000D843 |
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str r1, [r0, #0x40] |
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ldr r1, =0x22252521 |
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str r1, [r0, #0x44] |
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ldr r1, =0x22220A00 |
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str r1, [r0, #0x48] |
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.endm /* init_cs4 */ |
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.globl lowlevel_init
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lowlevel_init: |
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/* Redboot initializes very early AIPS, what for? |
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* Then it also initializes Multi-Layer AHB Crossbar Switch, |
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* M3IF */ |
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/* Also setup the Peripheral Port Remap register inside the core */ |
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ldr r0, =0x40000015 /* start from AIPS 2GB region */ |
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mcr p15, 0, r0, c15, c2, 4 |
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init_aips |
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init_max |
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init_m3if |
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init_drive_strength |
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init_cs4 |
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/* Image Processing Unit: */ |
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/* Too early to switch display on? */ |
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REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ |
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/* Clock Control Module: */ |
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REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ |
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DELAY 0x40000 |
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ |
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ |
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/* PBC CPLD on CS4 */ |
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mov r1, #CS4_BASE |
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ldrh r1, [r1, #0x2] |
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/* Is 27MHz switch set? */ |
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ands r1, r1, #0x10 |
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/* 532-133-66.5 */ |
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ldr r0, =CCM_BASE |
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ldr r1, =0xFF871D58 |
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/* PDR0 */ |
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str r1, [r0, #0x4] |
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ldreq r1, MPCTL_PARAM_532 |
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ldrne r1, MPCTL_PARAM_532_27 |
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/* MPCTL */ |
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str r1, [r0, #0x10] |
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/* Set UPLL=240MHz, USB=60MHz */ |
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ldr r1, =0x49FCFE7F |
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/* PDR1 */ |
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str r1, [r0, #0x8] |
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ldreq r1, UPCTL_PARAM_240 |
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ldrne r1, UPCTL_PARAM_240_27 |
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/* UPCTL */ |
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str r1, [r0, #0x14] |
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/* default CLKO to 1/8 of the ARM core */ |
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mov r1, #0x000002C0 |
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add r1, r1, #0x00000006 |
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/* COSR */ |
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str r1, [r0, #0x1c] |
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/* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */ |
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/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ |
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/* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ |
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/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ |
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/* Default: 1, 4, 12, 1 */ |
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REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) |
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/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ |
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REG 0xB8001010, 0x00000004 |
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REG 0xB8001004, 0x006ac73a |
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REG 0xB8001000, 0x92100000 |
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REG 0x80000f00, 0x12344321 |
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REG 0xB8001000, 0xa2100000 |
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REG 0x80000000, 0x12344321 |
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REG 0x80000000, 0x12344321 |
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REG 0xB8001000, 0xb2100000 |
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REG8 0x80000033, 0xda |
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REG8 0x81000000, 0xff |
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REG 0xB8001000, 0x82226080 |
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REG 0x80000000, 0xDEADBEEF |
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REG 0xB8001010, 0x0000000c |
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mov pc, lr |
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MPCTL_PARAM_532: |
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.word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) |
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MPCTL_PARAM_532_27: |
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.word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) |
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UPCTL_PARAM_240: |
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.word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) |
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UPCTL_PARAM_240_27: |
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.word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0)) |
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@ -1,114 +0,0 @@ |
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/*
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* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/sys_proto.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int dram_init(void) |
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{ |
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/* dram_init must store complete ramsize in gd->ram_size */ |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, |
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PHYS_SDRAM_1_SIZE); |
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return 0; |
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} |
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int board_early_init_f(void) |
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{ |
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int i; |
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/* CS0: Nor Flash */ |
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/*
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* CS0L and CS0A values are from the RedBoot sources by Freescale |
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* and are also equal to those used by Sascha Hauer for the Phytec |
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* i.MX31 board. CS0U is just a slightly optimized hardware default: |
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* the only non-zero field "Wait State Control" is set to half the |
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* default value. |
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*/ |
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static const struct mxc_weimcs cs0 = { |
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ |
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), |
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ |
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CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), |
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ |
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CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) |
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}; |
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mxc_setup_weimcs(0, &cs0); |
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/* setup pins for UART1 */ |
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); |
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); |
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); |
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mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); |
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|
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/* SPI2 */ |
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mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); |
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mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); |
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mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); |
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mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); |
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mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); |
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mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); |
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mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); |
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/* start SPI2 clock */ |
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__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); |
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/* PBC setup */ |
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/* Enable UART transceivers also reset the Ethernet/external UART */ |
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readw(CS4_BASE + 4); |
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writew(0x8023, CS4_BASE + 4); |
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/* RedBoot also has an empty loop with 100000 iterations here -
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* clock doesn't run yet */ |
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for (i = 0; i < 100000; i++) |
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; |
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/* Clear the reset, toggle the LEDs */ |
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writew(0xDF, CS4_BASE + 6); |
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/* clock still doesn't run */ |
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for (i = 0; i < 100000; i++) |
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; |
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/* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ |
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readb(CS4_BASE + 8); |
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readb(CS4_BASE + 7); |
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readb(CS4_BASE + 8); |
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readb(CS4_BASE + 7); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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printf("Board: MX31ADS\n"); |
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return 0; |
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} |
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|
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#ifdef CONFIG_CMD_NET |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_CS8900 |
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rc = cs8900_initialize(0, CONFIG_CS8900_BASE); |
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#endif |
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return rc; |
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} |
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#endif |
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@ -1,110 +0,0 @@ |
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/* |
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* January 2004 - Changed to support H4 device |
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* Copyright (c) 2004 Texas Instruments |
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* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = 0x00000000; |
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|
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. = ALIGN(4); |
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.text : |
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{ |
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*(.__image_copy_start) |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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|
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* (.vectors) |
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arch/arm/cpu/arm1136/start.o (.text*) |
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board/freescale/mx31ads/built-in.o (.text*) |
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arch/arm/lib/built-in.o (.text*) |
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net/built-in.o (.text*) |
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drivers/mtd/built-in.o (.text*) |
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|
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. = DEFINED(env_offset) ? env_offset : .; |
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env/embedded.o(.text*) |
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|
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*(.text*) |
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} |
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. = ALIGN(4); |
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.rodata : { *(.rodata*) } |
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|
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. = ALIGN(4); |
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.data : { |
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*(.data*) |
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} |
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|
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. = ALIGN(4); |
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|
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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|
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. = ALIGN(4); |
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|
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.image_copy_end : |
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{ |
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*(.__image_copy_end) |
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} |
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|
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.rel_dyn_start : |
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{ |
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*(.__rel_dyn_start) |
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} |
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|
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.rel.dyn : { |
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*(.rel*) |
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} |
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.rel_dyn_end : |
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{ |
||||
*(.__rel_dyn_end) |
||||
} |
||||
|
||||
.hash : { *(.hash*) } |
||||
|
||||
.end : |
||||
{ |
||||
*(.__end) |
||||
} |
||||
|
||||
_image_binary_end = .; |
||||
|
||||
/* |
||||
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c |
||||
* __bss_base and __bss_limit are for linker only (overlay ordering) |
||||
*/ |
||||
|
||||
.bss_start __rel_dyn_start (OVERLAY) : { |
||||
KEEP(*(.__bss_start)); |
||||
__bss_base = .; |
||||
} |
||||
|
||||
.bss __bss_base (OVERLAY) : { |
||||
*(.bss*) |
||||
. = ALIGN(4); |
||||
__bss_limit = .; |
||||
} |
||||
.bss_end __bss_limit (OVERLAY) : { |
||||
KEEP(*(.__bss_end)); |
||||
} |
||||
|
||||
.dynsym _image_binary_end : { *(.dynsym) } |
||||
.dynbss : { *(.dynbss) } |
||||
.dynstr : { *(.dynstr*) } |
||||
.dynamic : { *(.dynamic*) } |
||||
.gnu.hash : { *(.gnu.hash) } |
||||
.plt : { *(.plt*) } |
||||
.interp : { *(.interp*) } |
||||
.gnu : { *(.gnu*) } |
||||
.ARM.exidx : { *(.ARM.exidx*) } |
||||
} |
||||
@ -1,15 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_MX31ADS=y |
||||
CONFIG_SYS_TEXT_BASE=0xA0000000 |
||||
# CONFIG_AUTO_COMPLETE is not set |
||||
CONFIG_CMD_IMLS=y |
||||
CONFIG_CMD_SPI=y |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_DATE=y |
||||
CONFIG_ENV_IS_IN_FLASH=y |
||||
CONFIG_MXC_GPIO=y |
||||
# CONFIG_MMC is not set |
||||
CONFIG_MTD_NOR_FLASH=y |
||||
CONFIG_MXC_SPI=y |
||||
@ -1,145 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> |
||||
* |
||||
* Configuration settings for the MX31ADS Freescale board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_MX31 1 /* This is a mx31 */ |
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART1_BASE |
||||
|
||||
#define CONFIG_HARD_SPI 1 |
||||
#define CONFIG_DEFAULT_SPI_BUS 1 |
||||
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
||||
|
||||
/* PMIC Controller */ |
||||
#define CONFIG_POWER |
||||
#define CONFIG_POWER_SPI |
||||
#define CONFIG_POWER_FSL |
||||
#define CONFIG_FSL_PMIC_BUS 1 |
||||
#define CONFIG_FSL_PMIC_CS 0 |
||||
#define CONFIG_FSL_PMIC_CLK 1000000 |
||||
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
||||
#define CONFIG_FSL_PMIC_BITLEN 32 |
||||
#define CONFIG_RTC_MC13XXX |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
|
||||
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"uboot_addr=0xa0000000\0" \
|
||||
"uboot=mx31ads/u-boot.bin\0" \
|
||||
"kernel=mx31ads/uImage\0" \
|
||||
"nfsroot=/opt/eldk/arm\0" \
|
||||
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
|
||||
"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"bootcmd=run bootcmd_net\0" \
|
||||
"bootcmd_net=run bootargs_base bootargs_nfs; " \
|
||||
"tftpboot ${loadaddr} ${kernel}; bootm\0" \
|
||||
"prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
|
||||
"protect off ${uboot_addr} 0xa003ffff; " \
|
||||
"erase ${uboot_addr} 0xa003ffff; " \
|
||||
"cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
|
||||
"setenv filesize; saveenv\0" |
||||
|
||||
#define CONFIG_CS8900 |
||||
#define CONFIG_CS8900_BASE 0xb4020300 |
||||
#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ |
||||
|
||||
/*
|
||||
* The MX31ADS board seems to have a hardware "peculiarity" confirmed under |
||||
* U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A |
||||
* controller inverted. The controller is capable of detecting and correcting |
||||
* this, but it needs 4 network packets for that. Which means, at startup, you |
||||
* will not receive answers to the first 4 packest, unless there have been some |
||||
* broadcasts on the network, or your board is on a hub. Reducing the ARP |
||||
* timeout from default 5 seconds to 200ms we speed up the initial TFTP |
||||
* transfer, should the user wish one, significantly. |
||||
*/ |
||||
#define CONFIG_ARP_TIMEOUT 200UL |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x10000 |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM_1 CSD0_BASE |
||||
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_GBL_DATA_OFFSET) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_BASE CS0_BASE |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ |
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ |
||||
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024) |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CFI FLASH driver setup |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ |
||||
#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ |
||||
|
||||
/*
|
||||
* JFFS2 partitions |
||||
*/ |
||||
#define CONFIG_JFFS2_DEV "nor0" |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue