This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
9 years ago
committed by
Tom Rini
parent
6e830dfc1a
commit
452ef83046
@ -1,9 +0,0 @@ |
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if TARGET_VPAC270 |
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config SYS_BOARD |
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default "vpac270" |
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config SYS_CONFIG_NAME |
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default "vpac270" |
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endif |
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@ -1,8 +0,0 @@ |
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VPAC270 BOARD |
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M: Marek Vasut <marek.vasut@gmail.com> |
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S: Maintained |
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F: board/vpac270/ |
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F: include/configs/vpac270.h |
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F: configs/vpac270_nor_128_defconfig |
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F: configs/vpac270_nor_256_defconfig |
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F: configs/vpac270_ond_256_defconfig |
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@ -1,13 +0,0 @@ |
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#
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# Voipac PXA270 Support
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#
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# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifndef CONFIG_SPL_BUILD |
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obj-y := vpac270.o
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else |
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obj-y := onenand.o
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endif |
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@ -1,46 +0,0 @@ |
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/*
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* Voipac PXA270 OneNAND SPL |
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* |
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <config.h> |
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#include <asm/io.h> |
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#include <onenand_uboot.h> |
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#include <asm/arch/pxa.h> |
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void board_init_f(unsigned long unused) |
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{ |
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extern uint32_t _end; |
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uint32_t tmp; |
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asm volatile("mov %0, pc" : "=r"(tmp)); |
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tmp >>= 24; |
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/* The code runs from OneNAND RAM, copy SPL to SRAM and execute it. */ |
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if (tmp == 0) { |
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tmp = (uint32_t)&_end - CONFIG_SPL_TEXT_BASE; |
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onenand_spl_load_image(0, tmp, (void *)CONFIG_SPL_TEXT_BASE); |
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asm volatile("mov pc, %0" : : "r"(CONFIG_SPL_TEXT_BASE)); |
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} |
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/* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */ |
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arch_cpu_init(); |
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pxa2xx_dram_init(); |
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onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR, |
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CONFIG_SPL_ONENAND_LOAD_SIZE, |
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(void *)CONFIG_SYS_TEXT_BASE); |
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asm volatile("mov pc, %0" : : "r"(CONFIG_SYS_TEXT_BASE)); |
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for (;;) |
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; |
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} |
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void __attribute__((noreturn)) hang(void) |
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{ |
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for (;;) |
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; |
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} |
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@ -1,81 +0,0 @@ |
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/* |
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
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* on behalf of DENX Software Engineering GmbH |
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* |
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* January 2004 - Changed to support H4 device |
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* Copyright (c) 2004-2008 Texas Instruments |
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* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = CONFIG_SPL_TEXT_BASE; |
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.text.0 : |
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{ |
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*(.vectors) |
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arch/arm/cpu/pxa/start.o (.text*) |
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arch/arm/lib/built-in.o (.text*) |
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board/vpac270/built-in.o (.text*) |
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drivers/built-in.o (.text*) |
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} |
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/* Start of the rest of the SPL */ |
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. = CONFIG_SPL_TEXT_BASE + 0x800; |
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.text.1 : |
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{ |
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*(.text*) |
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} |
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. = ALIGN(4); |
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.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
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. = ALIGN(4); |
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.data : { |
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*(.data*) |
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} |
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. = ALIGN(4); |
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__image_copy_end = .; |
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.rel.dyn : { |
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__rel_dyn_start = .; |
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*(.rel*) |
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__rel_dyn_end = .; |
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} |
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. = ALIGN(0x800); |
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.end : |
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{ |
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*(.__end) |
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} |
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_image_binary_end = .; |
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.bss __rel_dyn_start (OVERLAY) : { |
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__bss_start = .; |
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*(.bss*) |
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. = ALIGN(4); |
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__bss_end = .; |
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} |
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.dynsym _image_binary_end : { *(.dynsym) } |
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.dynbss : { *(.dynbss) } |
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.dynstr : { *(.dynstr*) } |
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.dynamic : { *(.dynamic*) } |
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.hash : { *(.hash*) } |
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.plt : { *(.plt*) } |
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.interp : { *(.interp*) } |
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.gnu : { *(.gnu*) } |
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.ARM.exidx : { *(.ARM.exidx*) } |
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} |
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@ -1,126 +0,0 @@ |
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/*
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* Voipac PXA270 Support |
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* |
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/regs-mmc.h> |
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#include <asm/arch/pxa.h> |
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#include <netdev.h> |
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#include <serial.h> |
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#include <asm/io.h> |
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#include <usb.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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int board_init(void) |
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{ |
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/* We have RAM, disable cache */ |
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dcache_disable(); |
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icache_disable(); |
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/* memory and cpu-speed are setup before relocation */ |
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/* so we do _nothing_ here */ |
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/* Arch number of vpac270 */ |
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gd->bd->bi_arch_number = MACH_TYPE_VPAC270; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = 0xa0000100; |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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#ifndef CONFIG_ONENAND |
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pxa2xx_dram_init(); |
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#endif |
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gd->ram_size = PHYS_SDRAM_1_SIZE; |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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#ifdef CONFIG_RAM_256M |
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
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#endif |
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} |
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#ifdef CONFIG_CMD_MMC |
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int board_mmc_init(bd_t *bis) |
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{ |
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pxa_mmc_register(0); |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_CMD_USB |
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int board_usb_init(int index, enum usb_init_type init) |
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{ |
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writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & |
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), |
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UHCHR); |
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writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); |
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while (readl(UHCHR) & UHCHR_FSBIR) |
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; |
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writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); |
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writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); |
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/* Clear any OTG Pin Hold */ |
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if (readl(PSSR) & PSSR_OTGPH) |
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writel(readl(PSSR) | PSSR_OTGPH, PSSR); |
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writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); |
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writel(readl(UHCRHDA) | 0x100, UHCRHDA); |
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/* Set port power control mask bits, only 3 ports. */ |
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writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); |
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/* enable port 2 */ |
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writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | |
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UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); |
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return 0; |
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} |
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int board_usb_cleanup(int index, enum usb_init_type init) |
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{ |
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return 0; |
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} |
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void usb_board_stop(void) |
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{ |
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR); |
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udelay(11); |
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); |
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writel(readl(UHCCOMS) | 1, UHCCOMS); |
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udelay(10); |
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writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); |
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return; |
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} |
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#endif |
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#ifdef CONFIG_DRIVER_DM9000 |
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int board_eth_init(bd_t *bis) |
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{ |
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return dm9000_initialize(bis); |
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} |
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#endif |
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@ -1,6 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_VPAC270=y |
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CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_128M" |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_SYS_PROMPT="$ " |
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@ -1,6 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_VPAC270=y |
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CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_256M" |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_SYS_PROMPT="$ " |
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@ -1,8 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_VPAC270=y |
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CONFIG_SPL=y |
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CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M" |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_SYS_PROMPT="$ " |
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@ -1,325 +0,0 @@ |
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/*
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* Voipac PXA270 configuration file |
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* |
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Board Configuration Options |
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*/ |
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#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ |
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#define CONFIG_VPAC270 1 /* Voipac PXA270 board */ |
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#define CONFIG_SYS_TEXT_BASE 0xa0000000 |
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#ifdef CONFIG_ONENAND |
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#define CONFIG_SPL_ONENAND_SUPPORT |
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#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000 |
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#define CONFIG_SPL_ONENAND_LOAD_SIZE \ |
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(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) |
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#define CONFIG_SPL_TEXT_BASE 0x5c000000 |
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#define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds" |
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#endif |
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/*
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* Environment settings |
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*/ |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_SYS_MALLOC_LEN (128*1024) |
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#define CONFIG_ARCH_CPU_INIT |
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#define CONFIG_BOOTCOMMAND \ |
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"if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
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"bootm 0xa4000000; " \
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"fi; " \
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"if usb reset && fatload usb 0 0xa4000000 uImage; then " \
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"bootm 0xa4000000; " \
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"fi; " \
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"if ide reset && fatload ide 0 0xa4000000 uImage; then " \
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"bootm 0xa4000000; " \
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"fi; " \
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"bootm 0x60000;" |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"update_onenand=" \
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"onenand erase 0x0 0x80000 ; " \
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"onenand write 0xa0000000 0x0 0x80000" |
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#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" |
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#define CONFIG_TIMESTAMP |
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#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ |
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#define CONFIG_CMDLINE_TAG |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_LZMA /* LZMA compression support */ |
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#define CONFIG_OF_LIBFDT |
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/*
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* Serial Console Configuration |
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*/ |
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#define CONFIG_PXA_SERIAL |
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#define CONFIG_FFUART 1 |
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#define CONFIG_CONS_INDEX 3 |
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#define CONFIG_BAUDRATE 115200 |
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/*
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* Bootloader Components Configuration |
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*/ |
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#define CONFIG_CMD_ENV |
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#define CONFIG_CMD_MMC |
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#define CONFIG_CMD_USB |
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#undef CONFIG_LCD |
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#define CONFIG_CMD_IDE |
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#ifdef CONFIG_ONENAND |
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#define CONFIG_CMD_ONENAND |
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#else |
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#undef CONFIG_CMD_ONENAND |
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#endif |
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/*
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* Networking Configuration |
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* chip on the Voipac PXA270 board |
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*/ |
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#ifdef CONFIG_CMD_NET |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_DRIVER_DM9000 1 |
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#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ |
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#define DM9000_IO (CONFIG_DM9000_BASE) |
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#define DM9000_DATA (CONFIG_DM9000_BASE + 4) |
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#define CONFIG_NET_RETRY_COUNT 10 |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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#endif |
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/*
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* MMC Card Configuration |
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*/ |
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#ifdef CONFIG_CMD_MMC |
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#define CONFIG_MMC |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_PXA_MMC_GENERIC |
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#define CONFIG_SYS_MMC_BASE 0xF0000000 |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_DOS_PARTITION |
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#endif |
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/*
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* KGDB |
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*/ |
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#ifdef CONFIG_CMD_KGDB |
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#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ |
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#endif |
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/*
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* HUSH Shell Configuration |
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*/ |
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#define CONFIG_SYS_HUSH_PARSER 1 |
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|
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#define CONFIG_SYS_LONGHELP |
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#ifdef CONFIG_SYS_HUSH_PARSER |
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#else |
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#endif |
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#define CONFIG_SYS_CBSIZE 256 |
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#define CONFIG_SYS_PBSIZE \ |
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(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
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#define CONFIG_SYS_MAXARGS 16 |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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#define CONFIG_SYS_DEVICE_NULLDEV 1 |
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#define CONFIG_CMDLINE_EDITING 1 |
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#define CONFIG_AUTO_COMPLETE 1 |
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/*
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* Clock Configuration |
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*/ |
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#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ |
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/*
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* DRAM Map |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */ |
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ |
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#ifdef CONFIG_RAM_256M |
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#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ |
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#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ |
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#endif |
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|
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#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ |
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#ifdef CONFIG_RAM_256M |
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#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ |
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#else |
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#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ |
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#endif |
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|
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
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|
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#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 |
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
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#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 |
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|
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/*
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* NOR FLASH |
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*/ |
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#define CONFIG_SYS_MONITOR_BASE 0x0 |
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#define CONFIG_SYS_MONITOR_LEN 0x80000 |
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#define CONFIG_ENV_ADDR \ |
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
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#define CONFIG_ENV_SIZE 0x20000 |
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#define CONFIG_ENV_SECT_SIZE 0x20000 |
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|
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#if defined(CONFIG_CMD_FLASH) /* NOR */ |
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
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|
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#ifdef CONFIG_RAM_256M |
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#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ |
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#endif |
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|
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_FLASH_CFI_DRIVER 1 |
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|
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#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) |
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#ifdef CONFIG_RAM_256M |
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 |
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } |
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#else |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
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#endif |
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|
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#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) |
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#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) |
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|
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
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#define CONFIG_SYS_FLASH_PROTECTION 1 |
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|
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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|
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#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_SYS_ONENAND_BASE 0x00000000 |
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|
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#define CONFIG_ENV_IS_IN_ONENAND 1 |
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|
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#else /* No flash */ |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_ENV_IS_NOWHERE |
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#endif |
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|
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/*
|
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* IDE |
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*/ |
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#ifdef CONFIG_CMD_IDE |
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#define CONFIG_LBA48 |
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#undef CONFIG_IDE_LED |
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#undef CONFIG_IDE_RESET |
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|
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#define __io |
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|
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#define CONFIG_SYS_IDE_MAXBUS 1 |
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#define CONFIG_SYS_IDE_MAXDEVICE 1 |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 |
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 |
||||
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 |
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0x120 |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 |
||||
|
||||
#define CONFIG_SYS_ATA_STRIDE 2 |
||||
#endif |
||||
|
||||
/*
|
||||
* GPIO settings |
||||
*/ |
||||
#define CONFIG_SYS_GPSR0_VAL 0x01308800 |
||||
#define CONFIG_SYS_GPSR1_VAL 0x00cf0000 |
||||
#define CONFIG_SYS_GPSR2_VAL 0x922ac000 |
||||
#define CONFIG_SYS_GPSR3_VAL 0x0161e800 |
||||
|
||||
#define CONFIG_SYS_GPCR0_VAL 0x00010000 |
||||
#define CONFIG_SYS_GPCR1_VAL 0x0 |
||||
#define CONFIG_SYS_GPCR2_VAL 0x0 |
||||
#define CONFIG_SYS_GPCR3_VAL 0x0 |
||||
|
||||
#define CONFIG_SYS_GPDR0_VAL 0xcbb18800 |
||||
#define CONFIG_SYS_GPDR1_VAL 0xfccfa981 |
||||
#define CONFIG_SYS_GPDR2_VAL 0x922affff |
||||
#define CONFIG_SYS_GPDR3_VAL 0x0161e904 |
||||
|
||||
#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 |
||||
#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510 |
||||
#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a |
||||
#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa |
||||
#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa |
||||
#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401 |
||||
#define CONFIG_SYS_GAFR3_L_VAL 0x54010310 |
||||
#define CONFIG_SYS_GAFR3_U_VAL 0x00025401 |
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x30 |
||||
|
||||
/*
|
||||
* Clock settings |
||||
*/ |
||||
#define CONFIG_SYS_CKEN 0x00500240 |
||||
#define CONFIG_SYS_CCCR 0x02000290 |
||||
|
||||
/*
|
||||
* Memory settings |
||||
*/ |
||||
#define CONFIG_SYS_MSC0_VAL 0x3ffc95f9 |
||||
#define CONFIG_SYS_MSC1_VAL 0x02ccf974 |
||||
#define CONFIG_SYS_MSC2_VAL 0x00000000 |
||||
#ifdef CONFIG_RAM_256M |
||||
#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 |
||||
#else |
||||
#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 |
||||
#endif |
||||
#define CONFIG_SYS_MDREFR_VAL 0x201fe01e |
||||
#define CONFIG_SYS_MDMRS_VAL 0x00000000 |
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
||||
#define CONFIG_SYS_SXCNFG_VAL 0x40044004 |
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces |
||||
*/ |
||||
#define CONFIG_SYS_MECR_VAL 0x00000001 |
||||
#define CONFIG_SYS_MCMEM0_VAL 0x00014307 |
||||
#define CONFIG_SYS_MCMEM1_VAL 0x00014307 |
||||
#define CONFIG_SYS_MCATT0_VAL 0x0001c787 |
||||
#define CONFIG_SYS_MCATT1_VAL 0x0001c787 |
||||
#define CONFIG_SYS_MCIO0_VAL 0x0001430f |
||||
#define CONFIG_SYS_MCIO1_VAL 0x0001430f |
||||
|
||||
/*
|
||||
* LCD |
||||
*/ |
||||
#ifdef CONFIG_LCD |
||||
#define CONFIG_VOIPAC_LCD |
||||
#endif |
||||
|
||||
/*
|
||||
* USB |
||||
*/ |
||||
#ifdef CONFIG_CMD_USB |
||||
#define CONFIG_USB_OHCI_NEW |
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT |
||||
#define CONFIG_SYS_USB_OHCI_BOARD_INIT |
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 |
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270" |
||||
#define CONFIG_USB_STORAGE |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue