The device interface is 16 bits wide. All the available packets are read from the incoming fifo. Signed-off-by: Roberto Cerati <roberto.cerati@bticino.it> Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> [voice.shen@atmel.com: address comments from review results] [voice.shen@atmel.com: clean up for submit] Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>master
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/*
|
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* Micrel KS8851_MLL 16bit Network driver |
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* Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <asm/io.h> |
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#include <common.h> |
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#include <command.h> |
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#include <malloc.h> |
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#include <net.h> |
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#include <miiphy.h> |
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#include "ks8851_mll.h" |
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#define DRIVERNAME "ks8851_mll" |
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#define MAX_RECV_FRAMES 32 |
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#define MAX_BUF_SIZE 2048 |
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#define TX_BUF_SIZE 2000 |
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#define RX_BUF_SIZE 2000 |
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static const struct chip_id chip_ids[] = { |
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{CIDER_ID, "KSZ8851"}, |
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{0, NULL}, |
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}; |
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/*
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* union ks_tx_hdr - tx header data |
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* @txb: The header as bytes |
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* @txw: The header as 16bit, little-endian words |
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* |
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* A dual representation of the tx header data to allow |
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* access to individual bytes, and to allow 16bit accesses |
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* with 16bit alignment. |
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*/ |
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union ks_tx_hdr { |
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u8 txb[4]; |
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__le16 txw[2]; |
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}; |
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|
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/*
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* struct ks_net - KS8851 driver private data |
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* @net_device : The network device we're bound to |
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* @txh : temporaly buffer to save status/length. |
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* @frame_head_info : frame header information for multi-pkt rx. |
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* @statelock : Lock on this structure for tx list. |
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* @msg_enable : The message flags controlling driver output (see ethtool). |
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* @frame_cnt : number of frames received. |
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* @bus_width : i/o bus width. |
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* @irq : irq number assigned to this device. |
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* @rc_rxqcr : Cached copy of KS_RXQCR. |
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* @rc_txcr : Cached copy of KS_TXCR. |
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* @rc_ier : Cached copy of KS_IER. |
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* @sharedbus : Multipex(addr and data bus) mode indicator. |
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* @cmd_reg_cache : command register cached. |
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* @cmd_reg_cache_int : command register cached. Used in the irq handler. |
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* @promiscuous : promiscuous mode indicator. |
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* @all_mcast : mutlicast indicator. |
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* @mcast_lst_size : size of multicast list. |
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* @mcast_lst : multicast list. |
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* @mcast_bits : multicast enabed. |
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* @mac_addr : MAC address assigned to this device. |
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* @fid : frame id. |
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* @extra_byte : number of extra byte prepended rx pkt. |
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* @enabled : indicator this device works. |
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*/ |
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/* Receive multiplex framer header info */ |
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struct type_frame_head { |
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u16 sts; /* Frame status */ |
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u16 len; /* Byte count */ |
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} fr_h_i[MAX_RECV_FRAMES]; |
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struct ks_net { |
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struct net_device *netdev; |
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union ks_tx_hdr txh; |
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struct type_frame_head *frame_head_info; |
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u32 msg_enable; |
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u32 frame_cnt; |
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int bus_width; |
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int irq; |
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u16 rc_rxqcr; |
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u16 rc_txcr; |
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u16 rc_ier; |
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u16 sharedbus; |
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u16 cmd_reg_cache; |
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u16 cmd_reg_cache_int; |
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u16 promiscuous; |
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u16 all_mcast; |
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u16 mcast_lst_size; |
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u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN]; |
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u8 mcast_bits[HW_MCAST_SIZE]; |
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u8 mac_addr[6]; |
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u8 fid; |
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u8 extra_byte; |
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u8 enabled; |
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} ks_str, *ks; |
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#define BE3 0x8000 /* Byte Enable 3 */ |
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#define BE2 0x4000 /* Byte Enable 2 */ |
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#define BE1 0x2000 /* Byte Enable 1 */ |
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#define BE0 0x1000 /* Byte Enable 0 */ |
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static u8 ks_rdreg8(struct eth_device *dev, u16 offset) |
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{ |
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u8 shift_bit = offset & 0x03; |
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u8 shift_data = (offset & 1) << 3; |
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writew(offset | (BE0 << shift_bit), dev->iobase + 2); |
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return (u8)(readw(dev->iobase) >> shift_data); |
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} |
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static u16 ks_rdreg16(struct eth_device *dev, u16 offset) |
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{ |
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); |
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return readw(dev->iobase); |
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} |
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static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val) |
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{ |
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u8 shift_bit = (offset & 0x03); |
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u16 value_write = (u16)(val << ((offset & 1) << 3)); |
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writew(offset | (BE0 << shift_bit), dev->iobase + 2); |
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writew(value_write, dev->iobase); |
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} |
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static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val) |
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{ |
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); |
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writew(val, dev->iobase); |
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} |
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/*
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* ks_inblk - read a block of data from QMU. This is called after sudo DMA mode |
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* enabled. |
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* @ks: The chip state |
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* @wptr: buffer address to save data |
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* @len: length in byte to read |
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*/ |
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static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len) |
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{ |
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len >>= 1; |
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while (len--) |
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*wptr++ = readw(dev->iobase); |
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} |
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/*
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* ks_outblk - write data to QMU. This is called after sudo DMA mode enabled. |
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* @ks: The chip information |
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* @wptr: buffer address |
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* @len: length in byte to write |
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*/ |
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static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len) |
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{ |
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len >>= 1; |
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while (len--) |
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writew(*wptr++, dev->iobase); |
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} |
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static void ks_enable_int(struct eth_device *dev) |
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{ |
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ks_wrreg16(dev, KS_IER, ks->rc_ier); |
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} |
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static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode) |
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{ |
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unsigned pmecr; |
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ks_rdreg16(dev, KS_GRR); |
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pmecr = ks_rdreg16(dev, KS_PMECR); |
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pmecr &= ~PMECR_PM_MASK; |
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pmecr |= pwrmode; |
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ks_wrreg16(dev, KS_PMECR, pmecr); |
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} |
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/*
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* ks_read_config - read chip configuration of bus width. |
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* @ks: The chip information |
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*/ |
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static void ks_read_config(struct eth_device *dev) |
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{ |
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u16 reg_data = 0; |
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/* Regardless of bus width, 8 bit read should always work. */ |
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reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF; |
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reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8; |
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/* addr/data bus are multiplexed */ |
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ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; |
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/*
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* There are garbage data when reading data from QMU, |
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* depending on bus-width. |
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*/ |
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if (reg_data & CCR_8BIT) { |
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ks->bus_width = ENUM_BUS_8BIT; |
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ks->extra_byte = 1; |
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} else if (reg_data & CCR_16BIT) { |
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ks->bus_width = ENUM_BUS_16BIT; |
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ks->extra_byte = 2; |
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} else { |
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ks->bus_width = ENUM_BUS_32BIT; |
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ks->extra_byte = 4; |
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} |
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} |
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/*
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* ks_soft_reset - issue one of the soft reset to the device |
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* @ks: The device state. |
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* @op: The bit(s) to set in the GRR |
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* |
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* Issue the relevant soft-reset command to the device's GRR register |
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* specified by @op. |
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* |
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* Note, the delays are in there as a caution to ensure that the reset |
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* has time to take effect and then complete. Since the datasheet does |
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* not currently specify the exact sequence, we have chosen something |
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* that seems to work with our device. |
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*/ |
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static void ks_soft_reset(struct eth_device *dev, unsigned op) |
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{ |
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/* Disable interrupt first */ |
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ks_wrreg16(dev, KS_IER, 0x0000); |
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ks_wrreg16(dev, KS_GRR, op); |
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mdelay(10); /* wait a short time to effect reset */ |
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ks_wrreg16(dev, KS_GRR, 0); |
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mdelay(1); /* wait for condition to clear */ |
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} |
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void ks_enable_qmu(struct eth_device *dev) |
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{ |
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u16 w; |
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w = ks_rdreg16(dev, KS_TXCR); |
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/* Enables QMU Transmit (TXCR). */ |
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ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE); |
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/* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */ |
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w = ks_rdreg16(dev, KS_RXQCR); |
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ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE); |
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/* Enables QMU Receive (RXCR1). */ |
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w = ks_rdreg16(dev, KS_RXCR1); |
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ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE); |
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} |
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static void ks_disable_qmu(struct eth_device *dev) |
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{ |
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u16 w; |
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w = ks_rdreg16(dev, KS_TXCR); |
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/* Disables QMU Transmit (TXCR). */ |
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w &= ~TXCR_TXE; |
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ks_wrreg16(dev, KS_TXCR, w); |
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/* Disables QMU Receive (RXCR1). */ |
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w = ks_rdreg16(dev, KS_RXCR1); |
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w &= ~RXCR1_RXE; |
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ks_wrreg16(dev, KS_RXCR1, w); |
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} |
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static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len) |
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{ |
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u32 r = ks->extra_byte & 0x1; |
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u32 w = ks->extra_byte - r; |
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/* 1. set sudo DMA mode */ |
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ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI); |
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ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); |
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/*
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* 2. read prepend data |
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* |
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* read 4 + extra bytes and discard them. |
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* extra bytes for dummy, 2 for status, 2 for len |
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*/ |
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if (r) |
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ks_rdreg8(dev, 0); |
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ks_inblk(dev, buf, w + 2 + 2); |
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/* 3. read pkt data */ |
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ks_inblk(dev, buf, ALIGN(len, 4)); |
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/* 4. reset sudo DMA Mode */ |
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ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff); |
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} |
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static void ks_rcv(struct eth_device *dev, uchar **pv_data) |
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{ |
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struct type_frame_head *frame_hdr = ks->frame_head_info; |
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int i; |
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ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8; |
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/* read all header information */ |
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for (i = 0; i < ks->frame_cnt; i++) { |
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/* Checking Received packet status */ |
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frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR); |
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/* Get packet len from hardware */ |
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frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR); |
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frame_hdr++; |
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} |
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frame_hdr = ks->frame_head_info; |
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while (ks->frame_cnt--) { |
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if ((frame_hdr->sts & RXFSHR_RXFV) && |
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(frame_hdr->len < RX_BUF_SIZE) && |
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frame_hdr->len) { |
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/* read data block including CRC 4 bytes */ |
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ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len); |
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/* NetRxPackets buffer size is ok (*pv_data pointer) */ |
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NetReceive(*pv_data, frame_hdr->len); |
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pv_data++; |
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} else { |
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ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF)); |
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printf(DRIVERNAME ": bad packet\n"); |
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} |
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frame_hdr++; |
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} |
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} |
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/*
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* ks_read_selftest - read the selftest memory info. |
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* @ks: The device state |
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* |
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* Read and check the TX/RX memory selftest information. |
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*/ |
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static int ks_read_selftest(struct eth_device *dev) |
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{ |
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u16 both_done = MBIR_TXMBF | MBIR_RXMBF; |
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u16 mbir; |
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int ret = 0; |
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mbir = ks_rdreg16(dev, KS_MBIR); |
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if ((mbir & both_done) != both_done) { |
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printf(DRIVERNAME ": Memory selftest not finished\n"); |
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return 0; |
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} |
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if (mbir & MBIR_TXMBFA) { |
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printf(DRIVERNAME ": TX memory selftest fails\n"); |
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ret |= 1; |
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} |
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if (mbir & MBIR_RXMBFA) { |
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printf(DRIVERNAME ": RX memory selftest fails\n"); |
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ret |= 2; |
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} |
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debug(DRIVERNAME ": the selftest passes\n"); |
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return ret; |
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} |
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static void ks_setup(struct eth_device *dev) |
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{ |
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u16 w; |
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/* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */ |
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ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI); |
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/* Setup Receive Frame Data Pointer Auto-Increment */ |
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ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI); |
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/* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */ |
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ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK); |
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/* Setup RxQ Command Control (RXQCR) */ |
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ks->rc_rxqcr = RXQCR_CMD_CNTL; |
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ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr); |
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/*
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* set the force mode to half duplex, default is full duplex |
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* because if the auto-negotiation fails, most switch uses |
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* half-duplex. |
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*/ |
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w = ks_rdreg16(dev, KS_P1MBCR); |
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w &= ~P1MBCR_FORCE_FDX; |
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ks_wrreg16(dev, KS_P1MBCR, w); |
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w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP; |
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ks_wrreg16(dev, KS_TXCR, w); |
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w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC; |
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/* Normal mode */ |
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w |= RXCR1_RXPAFMA; |
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ks_wrreg16(dev, KS_RXCR1, w); |
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} |
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static void ks_setup_int(struct eth_device *dev) |
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{ |
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ks->rc_ier = 0x00; |
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/* Clear the interrupts status of the hardware. */ |
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ks_wrreg16(dev, KS_ISR, 0xffff); |
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/* Enables the interrupts of the hardware. */ |
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ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI); |
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} |
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static int ks8851_mll_detect_chip(struct eth_device *dev) |
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{ |
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unsigned short val, i; |
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ks_read_config(dev); |
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val = ks_rdreg16(dev, KS_CIDER); |
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if (val == 0xffff) { |
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/* Special case -- no chip present */ |
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printf(DRIVERNAME ": is chip mounted ?\n"); |
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return -1; |
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} else if ((val & 0xfff0) != CIDER_ID) { |
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printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val); |
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return -1; |
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} |
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debug("Read back KS8851 id 0x%x\n", val); |
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/* only one entry in the table */ |
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val &= 0xfff0; |
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for (i = 0; chip_ids[i].id != 0; i++) { |
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if (chip_ids[i].id == val) |
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break; |
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} |
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if (!chip_ids[i].id) { |
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printf(DRIVERNAME ": Unknown chip ID %04x\n", val); |
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return -1; |
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} |
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dev->priv = (void *)&chip_ids[i]; |
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return 0; |
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} |
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static void ks8851_mll_reset(struct eth_device *dev) |
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{ |
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/* wake up powermode to normal mode */ |
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ks_set_powermode(dev, PMECR_PM_NORMAL); |
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mdelay(1); /* wait for normal mode to take effect */ |
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/* Disable interrupt and reset */ |
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ks_soft_reset(dev, GRR_GSR); |
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/* turn off the IRQs and ack any outstanding */ |
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ks_wrreg16(dev, KS_IER, 0x0000); |
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ks_wrreg16(dev, KS_ISR, 0xffff); |
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/* shutdown RX/TX QMU */ |
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ks_disable_qmu(dev); |
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} |
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static void ks8851_mll_phy_configure(struct eth_device *dev) |
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{ |
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u16 data; |
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ks_setup(dev); |
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ks_setup_int(dev); |
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/* Probing the phy */ |
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data = ks_rdreg16(dev, KS_OBCR); |
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ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA); |
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debug(DRIVERNAME ": phy initialized\n"); |
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} |
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static void ks8851_mll_enable(struct eth_device *dev) |
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{ |
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ks_wrreg16(dev, KS_ISR, 0xffff); |
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ks_enable_int(dev); |
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ks_enable_qmu(dev); |
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} |
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static int ks8851_mll_init(struct eth_device *dev, bd_t *bd) |
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{ |
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struct chip_id *id = dev->priv; |
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debug(DRIVERNAME ": detected %s controller\n", id->name); |
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if (ks_read_selftest(dev)) { |
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printf(DRIVERNAME ": Selftest failed\n"); |
||||
return -1; |
||||
} |
||||
|
||||
ks8851_mll_reset(dev); |
||||
|
||||
/* Configure the PHY, initialize the link state */ |
||||
ks8851_mll_phy_configure(dev); |
||||
|
||||
/* static allocation of private informations */ |
||||
ks->frame_head_info = fr_h_i; |
||||
|
||||
/* Turn on Tx + Rx */ |
||||
ks8851_mll_enable(dev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len) |
||||
{ |
||||
/* start header at txb[0] to align txw entries */ |
||||
ks->txh.txw[0] = 0; |
||||
ks->txh.txw[1] = cpu_to_le16(len); |
||||
|
||||
/* 1. set sudo-DMA mode */ |
||||
ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI); |
||||
ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); |
||||
/* 2. write status/lenth info */ |
||||
ks_outblk(dev, ks->txh.txw, 4); |
||||
/* 3. write pkt data */ |
||||
ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4)); |
||||
/* 4. reset sudo-DMA mode */ |
||||
ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff); |
||||
/* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */ |
||||
ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE); |
||||
/* 6. wait until TXQCR_METFE is auto-cleared */ |
||||
do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE); |
||||
} |
||||
|
||||
static int ks8851_mll_send(struct eth_device *dev, void *packet, int length) |
||||
{ |
||||
u8 *data = (u8 *)packet; |
||||
u16 tmplen = (u16)length; |
||||
u16 retv; |
||||
|
||||
/*
|
||||
* Extra space are required: |
||||
* 4 byte for alignment, 4 for status/length, 4 for CRC |
||||
*/ |
||||
retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff; |
||||
if (retv >= tmplen + 12) { |
||||
ks_write_qmu(dev, data, tmplen); |
||||
return 0; |
||||
} else { |
||||
printf(DRIVERNAME ": failed to send packet: No buffer\n"); |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
static void ks8851_mll_halt(struct eth_device *dev) |
||||
{ |
||||
ks8851_mll_reset(dev); |
||||
} |
||||
|
||||
/*
|
||||
* Maximum receive ring size; that is, the number of packets |
||||
* we can buffer before overflow happens. Basically, this just |
||||
* needs to be enough to prevent a packet being discarded while |
||||
* we are processing the previous one. |
||||
*/ |
||||
static int ks8851_mll_recv(struct eth_device *dev) |
||||
{ |
||||
u16 status; |
||||
|
||||
status = ks_rdreg16(dev, KS_ISR); |
||||
|
||||
ks_wrreg16(dev, KS_ISR, status); |
||||
|
||||
if ((status & IRQ_RXI)) |
||||
ks_rcv(dev, (uchar **)NetRxPackets); |
||||
|
||||
if ((status & IRQ_LDI)) { |
||||
u16 pmecr = ks_rdreg16(dev, KS_PMECR); |
||||
pmecr &= ~PMECR_WKEVT_MASK; |
||||
ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ks8851_mll_write_hwaddr(struct eth_device *dev) |
||||
{ |
||||
u16 addrl, addrm, addrh; |
||||
|
||||
addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1]; |
||||
addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3]; |
||||
addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5]; |
||||
|
||||
ks_wrreg16(dev, KS_MARH, addrh); |
||||
ks_wrreg16(dev, KS_MARM, addrm); |
||||
ks_wrreg16(dev, KS_MARL, addrl); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int ks8851_mll_initialize(u8 dev_num, int base_addr) |
||||
{ |
||||
struct eth_device *dev; |
||||
|
||||
dev = malloc(sizeof(*dev)); |
||||
if (!dev) { |
||||
printf("Error: Failed to allocate memory\n"); |
||||
return -1; |
||||
} |
||||
memset(dev, 0, sizeof(*dev)); |
||||
|
||||
dev->iobase = base_addr; |
||||
|
||||
ks = &ks_str; |
||||
|
||||
/* Try to detect chip. Will fail if not present. */ |
||||
if (ks8851_mll_detect_chip(dev)) { |
||||
free(dev); |
||||
return -1; |
||||
} |
||||
|
||||
dev->init = ks8851_mll_init; |
||||
dev->halt = ks8851_mll_halt; |
||||
dev->send = ks8851_mll_send; |
||||
dev->recv = ks8851_mll_recv; |
||||
dev->write_hwaddr = ks8851_mll_write_hwaddr; |
||||
sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num); |
||||
|
||||
eth_register(dev); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,357 @@ |
||||
/*
|
||||
* drivers/net/ks8851_mll.c |
||||
* |
||||
* Supports: |
||||
* KS8851 16bit MLL chip from Micrel Inc. |
||||
* |
||||
* Copyright (c) 2009 Micrel Inc. |
||||
* |
||||
* modified by |
||||
* (c) 2011 Bticino s.p.a, Roberto Cerati <roberto.cerati@bticino.it> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
#ifndef _KS8851_MLL_H_ |
||||
#define _KS8851_MLL_H_ |
||||
|
||||
#include <linux/types.h> |
||||
|
||||
#define KS_CCR 0x08 |
||||
#define CCR_EEPROM (1 << 9) |
||||
#define CCR_SPI (1 << 8) |
||||
#define CCR_8BIT (1 << 7) |
||||
#define CCR_16BIT (1 << 6) |
||||
#define CCR_32BIT (1 << 5) |
||||
#define CCR_SHARED (1 << 4) |
||||
#define CCR_32PIN (1 << 0) |
||||
|
||||
/* MAC address registers */ |
||||
#define KS_MARL 0x10 |
||||
#define KS_MARM 0x12 |
||||
#define KS_MARH 0x14 |
||||
|
||||
#define KS_OBCR 0x20 |
||||
#define OBCR_ODS_16MA (1 << 6) |
||||
|
||||
#define KS_EEPCR 0x22 |
||||
#define EEPCR_EESA (1 << 4) |
||||
#define EEPCR_EESB (1 << 3) |
||||
#define EEPCR_EEDO (1 << 2) |
||||
#define EEPCR_EESCK (1 << 1) |
||||
#define EEPCR_EECS (1 << 0) |
||||
|
||||
#define KS_MBIR 0x24 |
||||
#define MBIR_TXMBF (1 << 12) |
||||
#define MBIR_TXMBFA (1 << 11) |
||||
#define MBIR_RXMBF (1 << 4) |
||||
#define MBIR_RXMBFA (1 << 3) |
||||
|
||||
#define KS_GRR 0x26 |
||||
#define GRR_QMU (1 << 1) |
||||
#define GRR_GSR (1 << 0) |
||||
|
||||
#define KS_WFCR 0x2A |
||||
#define WFCR_MPRXE (1 << 7) |
||||
#define WFCR_WF3E (1 << 3) |
||||
#define WFCR_WF2E (1 << 2) |
||||
#define WFCR_WF1E (1 << 1) |
||||
#define WFCR_WF0E (1 << 0) |
||||
|
||||
#define KS_WF0CRC0 0x30 |
||||
#define KS_WF0CRC1 0x32 |
||||
#define KS_WF0BM0 0x34 |
||||
#define KS_WF0BM1 0x36 |
||||
#define KS_WF0BM2 0x38 |
||||
#define KS_WF0BM3 0x3A |
||||
|
||||
#define KS_WF1CRC0 0x40 |
||||
#define KS_WF1CRC1 0x42 |
||||
#define KS_WF1BM0 0x44 |
||||
#define KS_WF1BM1 0x46 |
||||
#define KS_WF1BM2 0x48 |
||||
#define KS_WF1BM3 0x4A |
||||
|
||||
#define KS_WF2CRC0 0x50 |
||||
#define KS_WF2CRC1 0x52 |
||||
#define KS_WF2BM0 0x54 |
||||
#define KS_WF2BM1 0x56 |
||||
#define KS_WF2BM2 0x58 |
||||
#define KS_WF2BM3 0x5A |
||||
|
||||
#define KS_WF3CRC0 0x60 |
||||
#define KS_WF3CRC1 0x62 |
||||
#define KS_WF3BM0 0x64 |
||||
#define KS_WF3BM1 0x66 |
||||
#define KS_WF3BM2 0x68 |
||||
#define KS_WF3BM3 0x6A |
||||
|
||||
#define KS_TXCR 0x70 |
||||
#define TXCR_TCGICMP (1 << 8) |
||||
#define TXCR_TCGUDP (1 << 7) |
||||
#define TXCR_TCGTCP (1 << 6) |
||||
#define TXCR_TCGIP (1 << 5) |
||||
#define TXCR_FTXQ (1 << 4) |
||||
#define TXCR_TXFCE (1 << 3) |
||||
#define TXCR_TXPE (1 << 2) |
||||
#define TXCR_TXCRC (1 << 1) |
||||
#define TXCR_TXE (1 << 0) |
||||
|
||||
#define KS_TXSR 0x72 |
||||
#define TXSR_TXLC (1 << 13) |
||||
#define TXSR_TXMC (1 << 12) |
||||
#define TXSR_TXFID_MASK (0x3f << 0) |
||||
#define TXSR_TXFID_SHIFT (0) |
||||
#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f) |
||||
|
||||
|
||||
#define KS_RXCR1 0x74 |
||||
#define RXCR1_FRXQ (1 << 15) |
||||
#define RXCR1_RXUDPFCC (1 << 14) |
||||
#define RXCR1_RXTCPFCC (1 << 13) |
||||
#define RXCR1_RXIPFCC (1 << 12) |
||||
#define RXCR1_RXPAFMA (1 << 11) |
||||
#define RXCR1_RXFCE (1 << 10) |
||||
#define RXCR1_RXEFE (1 << 9) |
||||
#define RXCR1_RXMAFMA (1 << 8) |
||||
#define RXCR1_RXBE (1 << 7) |
||||
#define RXCR1_RXME (1 << 6) |
||||
#define RXCR1_RXUE (1 << 5) |
||||
#define RXCR1_RXAE (1 << 4) |
||||
#define RXCR1_RXINVF (1 << 1) |
||||
#define RXCR1_RXE (1 << 0) |
||||
#define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \ |
||||
RXCR1_RXMAFMA | RXCR1_RXPAFMA) |
||||
|
||||
#define KS_RXCR2 0x76 |
||||
#define RXCR2_SRDBL_MASK (0x7 << 5) |
||||
#define RXCR2_SRDBL_SHIFT (5) |
||||
#define RXCR2_SRDBL_4B (0x0 << 5) |
||||
#define RXCR2_SRDBL_8B (0x1 << 5) |
||||
#define RXCR2_SRDBL_16B (0x2 << 5) |
||||
#define RXCR2_SRDBL_32B (0x3 << 5) |
||||
/* #define RXCR2_SRDBL_FRAME (0x4 << 5) */ |
||||
#define RXCR2_IUFFP (1 << 4) |
||||
#define RXCR2_RXIUFCEZ (1 << 3) |
||||
#define RXCR2_UDPLFE (1 << 2) |
||||
#define RXCR2_RXICMPFCC (1 << 1) |
||||
#define RXCR2_RXSAF (1 << 0) |
||||
|
||||
#define KS_TXMIR 0x78 |
||||
|
||||
#define KS_RXFHSR 0x7C |
||||
#define RXFSHR_RXFV (1 << 15) |
||||
#define RXFSHR_RXICMPFCS (1 << 13) |
||||
#define RXFSHR_RXIPFCS (1 << 12) |
||||
#define RXFSHR_RXTCPFCS (1 << 11) |
||||
#define RXFSHR_RXUDPFCS (1 << 10) |
||||
#define RXFSHR_RXBF (1 << 7) |
||||
#define RXFSHR_RXMF (1 << 6) |
||||
#define RXFSHR_RXUF (1 << 5) |
||||
#define RXFSHR_RXMR (1 << 4) |
||||
#define RXFSHR_RXFT (1 << 3) |
||||
#define RXFSHR_RXFTL (1 << 2) |
||||
#define RXFSHR_RXRF (1 << 1) |
||||
#define RXFSHR_RXCE (1 << 0) |
||||
#define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\ |
||||
RXFSHR_RXFTL | RXFSHR_RXMR |\
|
||||
RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
|
||||
RXFSHR_RXTCPFCS) |
||||
#define KS_RXFHBCR 0x7E |
||||
#define RXFHBCR_CNT_MASK 0x0FFF |
||||
|
||||
#define KS_TXQCR 0x80 |
||||
#define TXQCR_AETFE (1 << 2) |
||||
#define TXQCR_TXQMAM (1 << 1) |
||||
#define TXQCR_METFE (1 << 0) |
||||
|
||||
#define KS_RXQCR 0x82 |
||||
#define RXQCR_RXDTTS (1 << 12) |
||||
#define RXQCR_RXDBCTS (1 << 11) |
||||
#define RXQCR_RXFCTS (1 << 10) |
||||
#define RXQCR_RXIPHTOE (1 << 9) |
||||
#define RXQCR_RXDTTE (1 << 7) |
||||
#define RXQCR_RXDBCTE (1 << 6) |
||||
#define RXQCR_RXFCTE (1 << 5) |
||||
#define RXQCR_ADRFE (1 << 4) |
||||
#define RXQCR_SDA (1 << 3) |
||||
#define RXQCR_RRXEF (1 << 0) |
||||
#define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE) |
||||
|
||||
#define KS_TXFDPR 0x84 |
||||
#define TXFDPR_TXFPAI (1 << 14) |
||||
#define TXFDPR_TXFP_MASK (0x7ff << 0) |
||||
#define TXFDPR_TXFP_SHIFT (0) |
||||
|
||||
#define KS_RXFDPR 0x86 |
||||
#define RXFDPR_RXFPAI (1 << 14) |
||||
|
||||
#define KS_RXDTTR 0x8C |
||||
#define KS_RXDBCTR 0x8E |
||||
|
||||
#define KS_IER 0x90 |
||||
#define KS_ISR 0x92 |
||||
#define IRQ_LCI (1 << 15) |
||||
#define IRQ_TXI (1 << 14) |
||||
#define IRQ_RXI (1 << 13) |
||||
#define IRQ_RXOI (1 << 11) |
||||
#define IRQ_TXPSI (1 << 9) |
||||
#define IRQ_RXPSI (1 << 8) |
||||
#define IRQ_TXSAI (1 << 6) |
||||
#define IRQ_RXWFDI (1 << 5) |
||||
#define IRQ_RXMPDI (1 << 4) |
||||
#define IRQ_LDI (1 << 3) |
||||
#define IRQ_EDI (1 << 2) |
||||
#define IRQ_SPIBEI (1 << 1) |
||||
#define IRQ_DEDI (1 << 0) |
||||
|
||||
#define KS_RXFCTR 0x9C |
||||
#define RXFCTR_THRESHOLD_MASK 0x00FF |
||||
|
||||
#define KS_RXFC 0x9D |
||||
#define RXFCTR_RXFC_MASK (0xff << 8) |
||||
#define RXFCTR_RXFC_SHIFT (8) |
||||
#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff) |
||||
#define RXFCTR_RXFCT_MASK (0xff << 0) |
||||
#define RXFCTR_RXFCT_SHIFT (0) |
||||
|
||||
#define KS_TXNTFSR 0x9E |
||||
|
||||
#define KS_MAHTR0 0xA0 |
||||
#define KS_MAHTR1 0xA2 |
||||
#define KS_MAHTR2 0xA4 |
||||
#define KS_MAHTR3 0xA6 |
||||
|
||||
#define KS_FCLWR 0xB0 |
||||
#define KS_FCHWR 0xB2 |
||||
#define KS_FCOWR 0xB4 |
||||
|
||||
#define KS_CIDER 0xC0 |
||||
#define CIDER_ID 0x8870 |
||||
#define CIDER_REV_MASK (0x7 << 1) |
||||
#define CIDER_REV_SHIFT (1) |
||||
#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7) |
||||
|
||||
#define KS_CGCR 0xC6 |
||||
#define KS_IACR 0xC8 |
||||
#define IACR_RDEN (1 << 12) |
||||
#define IACR_TSEL_MASK (0x3 << 10) |
||||
#define IACR_TSEL_SHIFT (10) |
||||
#define IACR_TSEL_MIB (0x3 << 10) |
||||
#define IACR_ADDR_MASK (0x1f << 0) |
||||
#define IACR_ADDR_SHIFT (0) |
||||
|
||||
#define KS_IADLR 0xD0 |
||||
#define KS_IAHDR 0xD2 |
||||
|
||||
#define KS_PMECR 0xD4 |
||||
#define PMECR_PME_DELAY (1 << 14) |
||||
#define PMECR_PME_POL (1 << 12) |
||||
#define PMECR_WOL_WAKEUP (1 << 11) |
||||
#define PMECR_WOL_MAGICPKT (1 << 10) |
||||
#define PMECR_WOL_LINKUP (1 << 9) |
||||
#define PMECR_WOL_ENERGY (1 << 8) |
||||
#define PMECR_AUTO_WAKE_EN (1 << 7) |
||||
#define PMECR_WAKEUP_NORMAL (1 << 6) |
||||
#define PMECR_WKEVT_MASK (0xf << 2) |
||||
#define PMECR_WKEVT_SHIFT (2) |
||||
#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf) |
||||
#define PMECR_WKEVT_ENERGY (0x1 << 2) |
||||
#define PMECR_WKEVT_LINK (0x2 << 2) |
||||
#define PMECR_WKEVT_MAGICPKT (0x4 << 2) |
||||
#define PMECR_WKEVT_FRAME (0x8 << 2) |
||||
#define PMECR_PM_MASK (0x3 << 0) |
||||
#define PMECR_PM_SHIFT (0) |
||||
#define PMECR_PM_NORMAL (0x0 << 0) |
||||
#define PMECR_PM_ENERGY (0x1 << 0) |
||||
#define PMECR_PM_SOFTDOWN (0x2 << 0) |
||||
#define PMECR_PM_POWERSAVE (0x3 << 0) |
||||
|
||||
/* Standard MII PHY data */ |
||||
#define KS_P1MBCR 0xE4 |
||||
#define P1MBCR_FORCE_FDX (1 << 8) |
||||
|
||||
#define KS_P1MBSR 0xE6 |
||||
#define P1MBSR_AN_COMPLETE (1 << 5) |
||||
#define P1MBSR_AN_CAPABLE (1 << 3) |
||||
#define P1MBSR_LINK_UP (1 << 2) |
||||
|
||||
#define KS_PHY1ILR 0xE8 |
||||
#define KS_PHY1IHR 0xEA |
||||
#define KS_P1ANAR 0xEC |
||||
#define KS_P1ANLPR 0xEE |
||||
|
||||
#define KS_P1SCLMD 0xF4 |
||||
#define P1SCLMD_LEDOFF (1 << 15) |
||||
#define P1SCLMD_TXIDS (1 << 14) |
||||
#define P1SCLMD_RESTARTAN (1 << 13) |
||||
#define P1SCLMD_DISAUTOMDIX (1 << 10) |
||||
#define P1SCLMD_FORCEMDIX (1 << 9) |
||||
#define P1SCLMD_AUTONEGEN (1 << 7) |
||||
#define P1SCLMD_FORCE100 (1 << 6) |
||||
#define P1SCLMD_FORCEFDX (1 << 5) |
||||
#define P1SCLMD_ADV_FLOW (1 << 4) |
||||
#define P1SCLMD_ADV_100BT_FDX (1 << 3) |
||||
#define P1SCLMD_ADV_100BT_HDX (1 << 2) |
||||
#define P1SCLMD_ADV_10BT_FDX (1 << 1) |
||||
#define P1SCLMD_ADV_10BT_HDX (1 << 0) |
||||
|
||||
#define KS_P1CR 0xF6 |
||||
#define P1CR_HP_MDIX (1 << 15) |
||||
#define P1CR_REV_POL (1 << 13) |
||||
#define P1CR_OP_100M (1 << 10) |
||||
#define P1CR_OP_FDX (1 << 9) |
||||
#define P1CR_OP_MDI (1 << 7) |
||||
#define P1CR_AN_DONE (1 << 6) |
||||
#define P1CR_LINK_GOOD (1 << 5) |
||||
#define P1CR_PNTR_FLOW (1 << 4) |
||||
#define P1CR_PNTR_100BT_FDX (1 << 3) |
||||
#define P1CR_PNTR_100BT_HDX (1 << 2) |
||||
#define P1CR_PNTR_10BT_FDX (1 << 1) |
||||
#define P1CR_PNTR_10BT_HDX (1 << 0) |
||||
|
||||
/* TX Frame control */ |
||||
#define TXFR_TXIC (1 << 15) |
||||
#define TXFR_TXFID_MASK (0x3f << 0) |
||||
#define TXFR_TXFID_SHIFT (0) |
||||
|
||||
#define KS_P1SR 0xF8 |
||||
#define P1SR_HP_MDIX (1 << 15) |
||||
#define P1SR_REV_POL (1 << 13) |
||||
#define P1SR_OP_100M (1 << 10) |
||||
#define P1SR_OP_FDX (1 << 9) |
||||
#define P1SR_OP_MDI (1 << 7) |
||||
#define P1SR_AN_DONE (1 << 6) |
||||
#define P1SR_LINK_GOOD (1 << 5) |
||||
#define P1SR_PNTR_FLOW (1 << 4) |
||||
#define P1SR_PNTR_100BT_FDX (1 << 3) |
||||
#define P1SR_PNTR_100BT_HDX (1 << 2) |
||||
#define P1SR_PNTR_10BT_FDX (1 << 1) |
||||
#define P1SR_PNTR_10BT_HDX (1 << 0) |
||||
|
||||
#define ENUM_BUS_NONE 0 |
||||
#define ENUM_BUS_8BIT 1 |
||||
#define ENUM_BUS_16BIT 2 |
||||
#define ENUM_BUS_32BIT 3 |
||||
|
||||
#define MAX_MCAST_LST 32 |
||||
#define HW_MCAST_SIZE 8 |
||||
#define MAC_ADDR_LEN 6 |
||||
|
||||
/* Chip ID values */ |
||||
struct chip_id { |
||||
u16 id; |
||||
char *name; |
||||
}; |
||||
|
||||
#endif |
Loading…
Reference in new issue