adapt omap3 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>master
Aneesh V
13 years ago
committed by
Albert ARIBAUD
parent
8b457fa828
commit
45bf05854b
@ -1,263 +0,0 @@ |
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/* |
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* Copyright (c) 2009 Wind River Systems, Inc. |
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* Tom Rix <Tom.Rix@windriver.com>
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* |
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* This file is based on and replaces the existing cache.c file |
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* The copyrights for the cache.c file are: |
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* |
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* (C) Copyright 2008 Texas Insturments |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de>
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* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <asm/arch/omap3.h> |
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/* |
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* omap3 cache code |
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*/ |
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.align 5
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.global invalidate_dcache
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.global l2_cache_enable
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.global l2_cache_disable
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.global setup_auxcr
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/* |
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* invalidate_dcache() |
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* |
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* Invalidate the whole D-cache. |
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* |
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* Corrupted registers: r0-r5, r7, r9-r11 |
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* |
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* - mm - mm_struct describing address space |
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*/ |
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invalidate_dcache: |
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stmfd r13!, {r0 - r5, r7, r9 - r12, r14} |
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mov r7, r0 @ take a backup of device type
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cmp r0, #0x3 @ check if the device type is
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@ GP
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moveq r12, #0x1 @ set up to invalide L2
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smi: .word 0x01600070 @ Call SMI monitor (smieq)
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cmp r7, #0x3 @ compare again in case its
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@ lost
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beq finished_inval @ if GP device, inval done
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@ above
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished_inval @ if loc is 0, then no need to
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@ clean
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mov r10, #0 @ start clean at cache level 0
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inval_loop1: |
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add r2, r10, r10, lsr #1 @ work out 3x current cache
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@ level
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mov r1, r0, lsr r2 @ extract cache type bits from
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@ clidr
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and r1, r1, #7 @ mask of the bits for current
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@ cache only
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cmp r1, #2 @ see what cache we have at
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@ this level
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blt skip_inval @ skip if no cache, or just
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@ i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level
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@ in cssr
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mov r2, #0 @ operand for mcr SBZ
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mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
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@ sych the new cssr&csidr,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the
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@ cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff |
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ands r4, r4, r1, lsr #3 @ find maximum number on the
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@ way size
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clz r5, r4 @ find bit position of way
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@ size increment
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ldr r7, =0x7fff |
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ands r7, r7, r1, lsr #13 @ extract max number of the
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@ index size
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inval_loop2: |
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mov r9, r4 @ create working copy of max
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@ way size
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inval_loop3: |
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orr r11, r10, r9, lsl r5 @ factor way and cache number
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@ into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge inval_loop3 |
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subs r7, r7, #1 @ decrement the index
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bge inval_loop2 |
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skip_inval: |
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add r10, r10, #2 @ increment cache number
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cmp r3, r10 |
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bgt inval_loop1 |
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finished_inval: |
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level
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@ in cssr
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mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} |
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l2_cache_set: |
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stmfd r13!, {r4 - r6, lr} |
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mov r5, r0 |
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bl get_cpu_rev |
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mov r4, r0 |
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bl get_cpu_family |
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@ ES2 onwards we can disable/enable L2 ourselves
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cmp r0, #CPU_OMAP34XX |
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cmpeq r4, #CPU_3XX_ES10 |
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mrc 15, 0, r0, cr1, cr0, 1 |
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bic r0, r0, #2 |
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orr r0, r0, r5, lsl #1 |
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mcreq 15, 0, r0, cr1, cr0, 1 |
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@ GP Device ROM code API usage here
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@ r12 = AUXCR Write function and r0 value
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mov ip, #3 |
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@ SMCNE instruction to call ROM Code API
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.word 0x11600070
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ldmfd r13!, {r4 - r6, pc} |
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l2_cache_enable: |
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mov r0, #1 |
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b l2_cache_set |
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l2_cache_disable: |
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mov r0, #0 |
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b l2_cache_set |
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/****************************************************************************** |
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* Routine: setup_auxcr() |
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* Description: Write to AuxCR desired value using SMI. |
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* general use. |
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*****************************************************************************/ |
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setup_auxcr: |
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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and r2, r0, #0x00f00000 @ variant
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and r3, r0, #0x0000000f @ revision
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orr r1, r3, r2, lsr #20-4 @ combine variant and revision
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mov r12, #0x3 |
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mrc p15, 0, r0, c1, c0, 1 |
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orr r0, r0, #0x10 @ Enable ASA
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@ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
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cmp r1, #0x21 |
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orrlt r0, r0, #1 << 5 |
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.word 0xE1600070 @ SMC
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mov r12, #0x2 |
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mrc p15, 1, r0, c9, c0, 2 |
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@ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
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cmp r1, #0x21 |
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orrlt r0, r0, #1 << 27 |
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.word 0xE1600070 @ SMC
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bx lr |
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.align 5
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.global v7_flush_dcache_all
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.global v7_flush_cache_all
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/* |
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* v7_flush_dcache_all() |
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* |
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* Flush the whole D-cache. |
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* |
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* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) |
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* |
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* - mm - mm_struct describing address space |
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*/ |
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v7_flush_dcache_all: |
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# dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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loop1: |
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff |
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff |
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop2: |
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mov r9, r4 @ create working copy of max way size
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loop3: |
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orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge loop3 |
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subs r7, r7, #1 @ decrement the index
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bge loop2 |
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skip: |
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add r10, r10, #2 @ increment cache number
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cmp r3, r10 |
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bgt loop1 |
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finished: |
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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# dsb |
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mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
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@ with armv7 this is 'isb',
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@ but we compile with armv5
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mov pc, lr |
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/* |
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* v7_flush_cache_all() |
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* |
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* Flush the entire cache system. |
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* The data cache flush is now achieved using atomic clean / invalidates |
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* working outwards from L1 cache. This is done using Set/Way based cache |
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* maintainance instructions. |
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* The instruction cache can still be invalidated back to the point of |
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* unification in a single instruction. |
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* |
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*/ |
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v7_flush_cache_all: |
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stmfd sp!, {r0-r7, r9-r11, lr} |
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bl v7_flush_dcache_all |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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ldmfd sp!, {r0-r7, r9-r11, lr} |
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mov pc, lr |
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