Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>master
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/immap_ls102xa.h> |
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#include <ahci.h> |
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#include <scsi.h> |
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/* port register default value */ |
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#define AHCI_PORT_PHY_1_CFG 0xa003fffe |
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#define AHCI_PORT_PHY_2_CFG 0x28183411 |
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#define AHCI_PORT_PHY_3_CFG 0x0e081004 |
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#define AHCI_PORT_PHY_4_CFG 0x00480811 |
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#define AHCI_PORT_PHY_5_CFG 0x192c96a4 |
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#define AHCI_PORT_TRANS_CFG 0x08000025 |
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#define SATA_ECC_REG_ADDR 0x20220520 |
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#define SATA_ECC_DISABLE 0x00020000 |
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int ls1021a_sata_init(void) |
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{ |
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struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; |
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 |
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out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); |
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#endif |
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); |
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out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); |
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out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); |
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out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG); |
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out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG); |
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); |
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ahci_init((void __iomem *)AHCI_BASE_ADDR); |
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scsi_scan(0); |
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return 0; |
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} |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __FSL_SATA_H_ |
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#define __FSL_SATA_H_ |
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int ls1021a_sata_init(void); |
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#endif |
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