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@ -32,6 +32,10 @@ DECLARE_GLOBAL_DATA_PTR; |
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#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ |
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#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ |
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#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ |
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#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */ |
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#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */ |
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#define ZYNQ_SPI_FIFO_DEPTH 128 |
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#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT |
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#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ |
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@ -143,7 +147,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs) |
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* xx01 - cs1 |
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* x011 - cs2 |
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*/ |
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cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK; |
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cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; |
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writel(cr, ®s->cr); |
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} |
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@ -260,14 +264,14 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed) |
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/* Set baudrate x8, if the freq is 0 */ |
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baud_rate_val = 0x2; |
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} else if (plat->speed_hz != speed) { |
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while ((baud_rate_val < 8) && |
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while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) && |
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((plat->frequency / |
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(2 << baud_rate_val)) > speed)) |
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baud_rate_val++; |
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plat->speed_hz = speed / (2 << baud_rate_val); |
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} |
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confr &= ~ZYNQ_SPI_CR_BRD_MASK; |
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confr |= (baud_rate_val << 3); |
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confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT); |
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writel(confr, ®s->cr); |
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priv->freq = speed; |
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