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ARM: uniphier: rework struct uniphier_board_data

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This commit reworks "struct uniphier_board_data" with an array of
DRAM channel data in it.  It will allow further cleanups by means of
"for" statements that iterate over the DDR channels.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
master
Masahiro Yamada 9 years ago
parent 8353266825
commit 46abfcc99e
11 changed files with 161 additions and 114 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
  2. 2
      arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
  3. 176
      arch/arm/mach-uniphier/boards.c
  4. 10
      arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
  5. 16
      arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
  6. 10
      arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
  7. 12
      arch/arm/mach-uniphier/dram/umc-proxstream2.c
  8. 21
      arch/arm/mach-uniphier/init.h
  9. 6
      arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
  10. 6
      arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
  11. 14
      arch/arm/mach-uniphier/memconf/memconf.c

2
arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
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@ -22,7 +22,7 @@ int ph1_ld4_bcu_init(const struct uniphier_board_data *bd)
writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
/* Specify DDR channel */
shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;

2
arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
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@ -26,7 +26,7 @@ int ph1_sld3_bcu_init(const struct uniphier_board_data *bd)
writel(0x24440000, BCSCR5);
/* Specify DDR channel */
shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;

176
arch/arm/mach-uniphier/boards.c
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@ -14,106 +14,152 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
static const struct uniphier_board_data ph1_sld3_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x20000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xc0000000,
.dram_ch1_size = 0x20000000,
.dram_ch1_width = 16,
.dram_ch2_base = 0xc0000000,
.dram_ch2_size = 0x10000000,
.dram_ch2_width = 16,
.dram_freq = 1600,
.dram_freq = 1600,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x20000000,
.width = 16,
},
.dram_ch[2] = {
.base = 0xc0000000,
.size = 0x10000000,
.width = 16,
},
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
static const struct uniphier_board_data ph1_ld4_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x10000000,
.dram_ch0_width = 16,
.dram_ch1_base = 0x90000000,
.dram_ch1_size = 0x10000000,
.dram_ch1_width = 16,
.dram_freq = 1600,
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x10000000,
.width = 16,
},
.dram_ch[1] = {
.base = 0x90000000,
.size = 0x10000000,
.width = 16,
},
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
/* 1GB RAM board */
static const struct uniphier_board_data ph1_pro4_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x20000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xa0000000,
.dram_ch1_size = 0x20000000,
.dram_ch1_width = 32,
.dram_freq = 1600,
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xa0000000,
.size = 0x20000000,
.width = 32,
},
};
/* 2GB RAM board */
static const struct uniphier_board_data ph1_pro4_2g_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x40000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xc0000000,
.dram_ch1_size = 0x40000000,
.dram_ch1_width = 32,
.dram_freq = 1600,
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
static const struct uniphier_board_data ph1_sld8_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x10000000,
.dram_ch0_width = 16,
.dram_ch1_base = 0x90000000,
.dram_ch1_size = 0x10000000,
.dram_ch1_width = 16,
.dram_freq = 1333,
.dram_freq = 1333,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x10000000,
.width = 16,
},
.dram_ch[1] = {
.base = 0x90000000,
.size = 0x10000000,
.width = 16,
},
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
static const struct uniphier_board_data ph1_pro5_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x20000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xa0000000,
.dram_ch1_size = 0x20000000,
.dram_ch1_width = 32,
.dram_freq = 1866,
.dram_freq = 1866,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xa0000000,
.size = 0x20000000,
.width = 32,
},
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
static const struct uniphier_board_data proxstream2_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x40000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xc0000000,
.dram_ch1_size = 0x20000000,
.dram_ch1_width = 32,
.dram_ch2_base = 0xe0000000,
.dram_ch2_size = 0x20000000,
.dram_ch2_width = 16,
.dram_freq = 2133,
.dram_freq = 2133,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[2] = {
.base = 0xe0000000,
.size = 0x20000000,
.width = 16,
},
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
static const struct uniphier_board_data ph1_ld6b_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x40000000,
.dram_ch0_width = 32,
.dram_ch1_base = 0xc0000000,
.dram_ch1_size = 0x20000000,
.dram_ch1_width = 32,
.dram_ch2_base = 0xe0000000,
.dram_ch2_size = 0x20000000,
.dram_ch2_width = 16,
.dram_freq = 1866,
.dram_freq = 1866,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[2] = {
.base = 0xe0000000,
.size = 0x20000000,
.width = 16,
},
};
#endif

10
arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
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@ -162,13 +162,13 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
{
if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
(bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) &&
(bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) &&
(bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
return umc_init_sub(bd->dram_freq,
bd->dram_ch0_size / SZ_128M,
bd->dram_ch1_size / SZ_128M);
bd->dram_ch[0].size / SZ_128M,
bd->dram_ch[1].size / SZ_128M);
} else {
pr_err("Unsupported DDR configuration\n");
return -EINVAL;

16
arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
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@ -146,39 +146,39 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size);
ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size);
ddrphy_prepare_training(phy0_0, 0);
ddrphy_training(phy0_0);
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size);
ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size);
ddrphy_prepare_training(phy0_1, 1);
ddrphy_training(phy0_1);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size);
ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size);
ddrphy_prepare_training(phy1_0, 0);
ddrphy_training(phy1_0);
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size);
ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size);
ddrphy_prepare_training(phy1_1, 1);
ddrphy_training(phy1_1);
ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size,
bd->dram_ch0_width);
ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch[0].size,
bd->dram_ch[0].width);
if (ret)
return ret;
ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size,
bd->dram_ch1_width);
ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch[1].size,
bd->dram_ch[1].width);
if (ret)
return ret;

10
arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
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@ -142,13 +142,13 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
{
if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
(bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) &&
(bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) &&
bd->dram_freq == 1333 &&
bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
return umc_init_sub(bd->dram_freq,
bd->dram_ch0_size / SZ_128M,
bd->dram_ch1_size / SZ_128M);
bd->dram_ch[0].size / SZ_128M,
bd->dram_ch[1].size / SZ_128M);
} else {
pr_err("Unsupported DDR configuration\n");
return -EINVAL;

12
arch/arm/mach-uniphier/dram/umc-proxstream2.c
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@ -603,22 +603,22 @@ int proxstream2_umc_init(const struct uniphier_board_data *bd)
return -EINVAL;
}
ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M,
bd->dram_ch0_width);
ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch[0].size / SZ_256M,
bd->dram_ch[0].width);
if (ret) {
printf("failed to initialize UMC ch0\n");
return ret;
}
ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M,
bd->dram_ch1_width);
ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch[1].size / SZ_256M,
bd->dram_ch[1].width);
if (ret) {
printf("failed to initialize UMC ch1\n");
return ret;
}
ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M,
bd->dram_ch2_width);
ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch[2].size / SZ_256M,
bd->dram_ch[2].width);
if (ret) {
printf("failed to initialize UMC ch2\n");
return ret;

21
arch/arm/mach-uniphier/init.h
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@ -7,17 +7,18 @@
#ifndef __MACH_INIT_H
#define __MACH_INIT_H
#define UNIPHIER_MAX_NR_DRAM_CH 3
struct uniphier_dram_ch {
unsigned long base;
unsigned long size;
unsigned int width;
};
struct uniphier_board_data {
unsigned long dram_ch0_base;
unsigned long dram_ch0_size;
unsigned long dram_ch0_width;
unsigned long dram_ch1_base;
unsigned long dram_ch1_size;
unsigned long dram_ch1_width;
unsigned long dram_ch2_base;
unsigned long dram_ch2_size;
unsigned long dram_ch2_width;
unsigned int dram_freq;
unsigned int dram_freq;
unsigned int dram_nr_ch;
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
};
const struct uniphier_board_data *uniphier_get_board_param(void);

6
arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
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@ -21,14 +21,14 @@ int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
switch (bd->dram_ch2_width) {
switch (bd->dram_ch[2].width) {
case 16:
tmp |= SG_MEMCONF_CH2_NUM_1;
size_per_word = bd->dram_ch2_size;
size_per_word = bd->dram_ch[2].size;
break;
case 32:
tmp |= SG_MEMCONF_CH2_NUM_2;
size_per_word = bd->dram_ch2_size >> 1;
size_per_word = bd->dram_ch[2].size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch2 width\n");

6
arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
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@ -21,14 +21,14 @@ int proxstream2_memconf_init(const struct uniphier_board_data *bd)
tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
switch (bd->dram_ch2_width) {
switch (bd->dram_ch[2].width) {
case 16:
tmp |= SG_MEMCONF_CH2_NUM_1;
size_per_word = bd->dram_ch2_size;
size_per_word = bd->dram_ch[2].size;
break;
case 32:
tmp |= SG_MEMCONF_CH2_NUM_2;
size_per_word = bd->dram_ch2_size >> 1;
size_per_word = bd->dram_ch[2].size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch2 width\n");

14
arch/arm/mach-uniphier/memconf/memconf.c
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@ -21,14 +21,14 @@ int memconf_init(const struct uniphier_board_data *bd)
tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
switch (bd->dram_ch0_width) {
switch (bd->dram_ch[0].width) {
case 16:
tmp |= SG_MEMCONF_CH0_NUM_1;
size_per_word = bd->dram_ch0_size;
size_per_word = bd->dram_ch[0].size;
break;
case 32:
tmp |= SG_MEMCONF_CH0_NUM_2;
size_per_word = bd->dram_ch0_size >> 1;
size_per_word = bd->dram_ch[0].size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch0 width\n");
@ -59,14 +59,14 @@ int memconf_init(const struct uniphier_board_data *bd)
tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
switch (bd->dram_ch1_width) {
switch (bd->dram_ch[1].width) {
case 16:
tmp |= SG_MEMCONF_CH1_NUM_1;
size_per_word = bd->dram_ch1_size;
size_per_word = bd->dram_ch[1].size;
break;
case 32:
tmp |= SG_MEMCONF_CH1_NUM_2;
size_per_word = bd->dram_ch1_size >> 1;
size_per_word = bd->dram_ch[1].size >> 1;
break;
default:
pr_err("error: unsupported DRAM Ch1 width\n");
@ -94,7 +94,7 @@ int memconf_init(const struct uniphier_board_data *bd)
return -EINVAL;
}
if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base)
if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
tmp |= SG_MEMCONF_SPARSEMEM;
else
tmp &= ~SG_MEMCONF_SPARSEMEM;

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