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powerpc: mpc8xx: remove SXNI855T board support

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This board has been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
master
Masahiro Yamada 10 years ago committed by Tom Rini
parent d1a4aafd71
commit 4723ce49e5
14 changed files with 2 additions and 3594 deletions
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  1. 2
      CREDITS
  2. 4
      arch/powerpc/cpu/mpc8xx/Kconfig
  3. 11
      board/sixnet/Kconfig
  4. 6
      board/sixnet/MAINTAINERS
  5. 8
      board/sixnet/Makefile
  6. 774
      board/sixnet/flash.c
  7. 1719
      board/sixnet/fpgadata.c
  8. 578
      board/sixnet/sixnet.c
  9. 20
      board/sixnet/sixnet.h
  10. 82
      board/sixnet/u-boot.lds
  11. 3
      configs/SXNI855T_defconfig
  12. 1
      doc/README.scrapyard
  13. 10
      include/commproc.h
  14. 378
      include/configs/SXNI855T.h

2
CREDITS
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@ -126,7 +126,7 @@ D: Palmtreo680 board, docg4 nand flash driver
N: Dave Ellis
E: DGE@sixnetio.com
D: EEPROM Speedup, SXNI855T port
D: EEPROM Speedup
N: Daniel Engstr?m
E: daniel@omicron.se

4
arch/powerpc/cpu/mpc8xx/Kconfig
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@ -47,9 +47,6 @@ config TARGET_R360MPI
config TARGET_RRVISION
bool "Support RRvision"
config TARGET_SXNI855T
bool "Support SXNI855T"
config TARGET_SPD823TS
bool "Support SPD823TS"
@ -145,7 +142,6 @@ source "board/lwmon/Kconfig"
source "board/manroland/uc100/Kconfig"
source "board/netvia/Kconfig"
source "board/r360mpi/Kconfig"
source "board/sixnet/Kconfig"
source "board/spd8xx/Kconfig"
source "board/tqc/tqm8xx/Kconfig"

11
board/sixnet/Kconfig
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@ -1,11 +0,0 @@
if TARGET_SXNI855T
config SYS_BOARD
string
default "sixnet"
config SYS_CONFIG_NAME
string
default "SXNI855T"
endif

6
board/sixnet/MAINTAINERS
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@ -1,6 +0,0 @@
SIXNET BOARD
M: Dave Ellis <DGE@sixnetio.com>
S: Orphan (since 2014-06)
F: board/sixnet/
F: include/configs/SXNI855T.h
F: configs/SXNI855T_defconfig

8
board/sixnet/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = sixnet.o flash.o

774
board/sixnet/flash.c
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@ -1,774 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc8xx.h>
/* environment.h defines the various CONFIG_ENV_... values in terms
* of whichever ones are given in the configuration file.
*/
#include <environment.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
* has nothing to do with the flash chip being 8-bit or 16-bit.
*/
#ifdef CONFIG_FLASH_16BIT
typedef unsigned short FLASH_PORT_WIDTH;
typedef volatile unsigned short FLASH_PORT_WIDTHV;
#define FLASH_ID_MASK 0xFFFF
#else
typedef unsigned long FLASH_PORT_WIDTH;
typedef volatile unsigned long FLASH_PORT_WIDTHV;
#define FLASH_ID_MASK 0xFFFFFFFF
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define ORMASK(size) ((-size) & OR_AM_MSK)
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
static void flash_reset(flash_info_t *info);
static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
static void flash_get_offsets(ulong base, flash_info_t *info);
#ifdef CONFIG_SYS_FLASH_PROTECTION
static void flash_sync_real_protect(flash_info_t *info);
#endif
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b;
int i;
/* Init: no FLASHes known */
for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_info[0].size = size_b;
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b);
}
/* Remap FLASH according to real size, so only at proper address */
memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b);
/* Do this again (was done already in flast_get_size), just
* in case we move it when remap the FLASH.
*/
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#ifdef CONFIG_SYS_FLASH_PROTECTION
/* read the hardware protection status (if any) into the
* protection array in flash_info.
*/
flash_sync_real_protect(&flash_info[0]);
#endif
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#ifdef CONFIG_ENV_ADDR
flash_protect ( FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]);
#endif
#ifdef CONFIG_ENV_ADDR_REDUND
flash_protect ( FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
return (size_b);
}
/*-----------------------------------------------------------------------
*/
static void flash_reset(flash_info_t *info)
{
FPWV *base = (FPWV *)(info->start[0]);
/* Put FLASH back in read mode */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
*base = (FPW)0x00FF00FF; /* Intel Read Mode */
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
*base = (FPW)0x00F000F0; /* AMD Read Mode */
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
/* set up sector start address table */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
&& (info->flash_id & FLASH_BTYPE)) {
int bootsect_size; /* number of bytes/boot sector */
int sect_size; /* number of bytes/regular sector */
bootsect_size = 0x00002000 * (sizeof(FPW)/2);
sect_size = 0x00010000 * (sizeof(FPW)/2);
/* set sector offsets for bottom boot block type */
for (i = 0; i < 8; ++i) {
info->start[i] = base + (i * bootsect_size);
}
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + ((i - 7) * sect_size);
}
}
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
int sect_size; /* number of bytes/sector */
sect_size = 0x00010000 * (sizeof(FPW)/2);
/* set up sector start address table (uniform sector type) */
for( i = 0; i < info->sector_count; i++ )
info->start[i] = base + (i * sect_size);
}
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
int sect_size; /* number of bytes/sector */
sect_size = 0x00010000 * (sizeof(FPW)/2);
/* set up sector start address table (top boot sector type) */
for (i = 0; i < info->sector_count - 3; i++)
info->start[i] = base + (i * sect_size);
i = info->sector_count - 1;
info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2);
info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2);
info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2);
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
uchar *boottype;
uchar *bootletter;
char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
uchar topboottype[] = "top boot sector";
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_STM: printf ("STM "); break;
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
}
/* check for top or bottom boot, if it applies */
if (info->flash_id & FLASH_BTYPE) {
boottype = botboottype;
bootletter = botbootletter;
}
else {
boottype = topboottype;
bootletter = topbootletter;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM800T:
fmt = "29LV800B%s (8 Mbit, %s)\n";
break;
case FLASH_AM640U:
fmt = "29LV641D (64 Mbit, uniform sectors)\n";
break;
case FLASH_28F800C3B:
case FLASH_28F800C3T:
fmt = "28F800C3%s (8 Mbit, %s)\n";
break;
case FLASH_INTEL800B:
case FLASH_INTEL800T:
fmt = "28F800B3%s (8 Mbit, %s)\n";
break;
case FLASH_28F160C3B:
case FLASH_28F160C3T:
fmt = "28F160C3%s (16 Mbit, %s)\n";
break;
case FLASH_INTEL160B:
case FLASH_INTEL160T:
fmt = "28F160B3%s (16 Mbit, %s)\n";
break;
case FLASH_28F320C3B:
case FLASH_28F320C3T:
fmt = "28F320C3%s (32 Mbit, %s)\n";
break;
case FLASH_INTEL320B:
case FLASH_INTEL320T:
fmt = "28F320B3%s (32 Mbit, %s)\n";
break;
case FLASH_28F640C3B:
case FLASH_28F640C3T:
fmt = "28F640C3%s (64 Mbit, %s)\n";
break;
case FLASH_INTEL640B:
case FLASH_INTEL640T:
fmt = "28F640B3%s (64 Mbit, %s)\n";
break;
default:
fmt = "Unknown Chip Type\n";
break;
}
printf (fmt, bootletter, boottype);
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20,
info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size (FPWV *addr, flash_info_t *info)
{
/* Write auto select command: read Manufacturer ID */
/* Write auto select command sequence and test FLASH answer */
addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */
addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */
/* The manufacturer codes are only 1 byte, so just use 1 byte.
* This works for any bus width and any FLASH device width.
*/
switch (addr[0] & 0xff) {
case (uchar)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (uchar)INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
case (FPW)AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000 * (sizeof(FPW)/2);
break; /* => 1 or 2 MiB */
case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x00800000 * (sizeof(FPW)/2);
break; /* => 8 or 16 MB */
case (FPW)INTEL_ID_28F800C3B:
info->flash_id += FLASH_28F800C3B;
info->sector_count = 23;
info->size = 0x00100000 * (sizeof(FPW)/2);
break; /* => 1 or 2 MB */
case (FPW)INTEL_ID_28F800B3B:
info->flash_id += FLASH_INTEL800B;
info->sector_count = 23;
info->size = 0x00100000 * (sizeof(FPW)/2);
break; /* => 1 or 2 MB */
case (FPW)INTEL_ID_28F160C3B:
info->flash_id += FLASH_28F160C3B;
info->sector_count = 39;
info->size = 0x00200000 * (sizeof(FPW)/2);
break; /* => 2 or 4 MB */
case (FPW)INTEL_ID_28F160B3B:
info->flash_id += FLASH_INTEL160B;
info->sector_count = 39;
info->size = 0x00200000 * (sizeof(FPW)/2);
break; /* => 2 or 4 MB */
case (FPW)INTEL_ID_28F320C3B:
info->flash_id += FLASH_28F320C3B;
info->sector_count = 71;
info->size = 0x00400000 * (sizeof(FPW)/2);
break; /* => 4 or 8 MB */
case (FPW)INTEL_ID_28F320B3B:
info->flash_id += FLASH_INTEL320B;
info->sector_count = 71;
info->size = 0x00400000 * (sizeof(FPW)/2);
break; /* => 4 or 8 MB */
case (FPW)INTEL_ID_28F640C3B:
info->flash_id += FLASH_28F640C3B;
info->sector_count = 135;
info->size = 0x00800000 * (sizeof(FPW)/2);
break; /* => 8 or 16 MB */
case (FPW)INTEL_ID_28F640B3B:
info->flash_id += FLASH_INTEL640B;
info->sector_count = 135;
info->size = 0x00800000 * (sizeof(FPW)/2);
break; /* => 8 or 16 MB */
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* => no or unknown flash */
}
flash_get_offsets((ulong)addr, info);
/* Put FLASH back in read mode */
flash_reset(info);
return (info->size);
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
/*-----------------------------------------------------------------------
*/
static void flash_sync_real_protect(flash_info_t *info)
{
FPWV *addr = (FPWV *)(info->start[0]);
FPWV *sect;
int i;
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F800C3B:
case FLASH_28F800C3T:
case FLASH_28F160C3B:
case FLASH_28F160C3T:
case FLASH_28F320C3B:
case FLASH_28F320C3T:
case FLASH_28F640C3B:
case FLASH_28F640C3T:
/* check for protected sectors */
*addr = (FPW)0x00900090;
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02.
* D0 = 1 for each device if protected.
* If at least one device is protected the sector is marked
* protected, but mixed protected and unprotected devices
* within a sector should never happen.
*/
sect = (FPWV *)(info->start[i]);
info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
}
/* Put FLASH back in read mode */
flash_reset(info);
break;
case FLASH_AM640U:
case FLASH_AM800T:
default:
/* no hardware protect that we support */
break;
}
}
#endif
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
FPWV *addr;
int flag, prot, sect;
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
ulong start, now, last;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_INTEL800B:
case FLASH_INTEL160B:
case FLASH_INTEL320B:
case FLASH_INTEL640B:
case FLASH_28F800C3B:
case FLASH_28F160C3B:
case FLASH_28F320C3B:
case FLASH_28F640C3B:
case FLASH_AM640U:
case FLASH_AM800T:
break;
case FLASH_UNKNOWN:
default:
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
start = get_timer(0);
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
if (info->protect[sect] != 0) /* protected, skip it */
continue;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr = (FPWV *)(info->start[sect]);
if (intel) {
*addr = (FPW)0x00500050; /* clear status register */
*addr = (FPW)0x00200020; /* erase setup */
*addr = (FPW)0x00D000D0; /* erase confirm */
}
else {
/* must be AMD style if not Intel */
FPWV *base; /* first address in bank */
base = (FPWV *)(info->start[0]);
base[0x0555] = (FPW)0x00AA00AA; /* unlock */
base[0x02AA] = (FPW)0x00550055; /* unlock */
base[0x0555] = (FPW)0x00800080; /* erase mode */
base[0x0555] = (FPW)0x00AA00AA; /* unlock */
base[0x02AA] = (FPW)0x00550055; /* unlock */
*addr = (FPW)0x00300030; /* erase sector */
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 50us for AMD, 80us for Intel.
* Let's wait 1 ms.
*/
udelay (1000);
while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
if (intel) {
/* suspend erase */
*addr = (FPW)0x00B000B0;
}
flash_reset(info); /* reset to read mode */
rcode = 1; /* failed */
break;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
flash_reset(info); /* reset to read mode */
}
printf (" done\n");
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
int bytes; /* number of bytes to program in current word */
int left; /* number of bytes left to program */
int i, res;
for (left = cnt, res = 0;
left > 0 && res == 0;
addr += sizeof(data), left -= sizeof(data) - bytes) {
bytes = addr & (sizeof(data) - 1);
addr &= ~(sizeof(data) - 1);
/* combine source and destination data so can program
* an entire word of 16 or 32 bits
*/
for (i = 0; i < sizeof(data); i++) {
data <<= 8;
if (i < bytes || i - bytes >= left )
data += *((uchar *)addr + i);
else
data += *src++;
}
/* write one word to the flash */
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
res = write_word_amd(info, (FPWV *)addr, data);
break;
case FLASH_MAN_INTEL:
res = write_word_intel(info, (FPWV *)addr, data);
break;
default:
/* unknown flash type, error! */
printf ("missing or unknown FLASH type\n");
res = 1; /* not really a timeout, but gives error */
break;
}
}
return (res);
}
/*-----------------------------------------------------------------------
* Write a word to Flash for AMD FLASH
* A word is 16 or 32 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
{
ulong start;
int flag;
int res = 0; /* result, assume success */
FPWV *base; /* first address in flash bank */
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
return (2);
}
base = (FPWV *)(info->start[0]);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
base[0x0555] = (FPW)0x00AA00AA; /* unlock */
base[0x02AA] = (FPW)0x00550055; /* unlock */
base[0x0555] = (FPW)0x00A000A0; /* selects program mode */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer (0);
/* data polling for D7 */
while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW)0x00F000F0; /* reset bank */
res = 1;
}
}
return (res);
}
/*-----------------------------------------------------------------------
* Write a word to Flash for Intel FLASH
* A word is 16 or 32 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
{
ulong start;
int flag;
int res = 0; /* result, assume success */
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*dest = (FPW)0x00500050; /* clear status register */
*dest = (FPW)0x00FF00FF; /* make sure in read mode */
*dest = (FPW)0x00400040; /* program setup */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer (0);
while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW)0x00B000B0; /* Suspend program */
res = 1;
}
}
if (res == 0 && (*dest & (FPW)0x00100010))
res = 1; /* write failed, time out error is close enough */
*dest = (FPW)0x00500050; /* clear status register */
*dest = (FPW)0x00FF00FF; /* make sure in read mode */
return (res);
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
/*-----------------------------------------------------------------------
*/
int flash_real_protect (flash_info_t * info, long sector, int prot)
{
int rcode = 0; /* assume success */
FPWV *addr; /* address of sector */
FPW value;
addr = (FPWV *) (info->start[sector]);
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F800C3B:
case FLASH_28F800C3T:
case FLASH_28F160C3B:
case FLASH_28F160C3T:
case FLASH_28F320C3B:
case FLASH_28F320C3T:
case FLASH_28F640C3B:
case FLASH_28F640C3T:
flash_reset (info); /* make sure in read mode */
*addr = (FPW) 0x00600060L; /* lock command setup */
if (prot)
*addr = (FPW) 0x00010001L; /* lock sector */
else
*addr = (FPW) 0x00D000D0L; /* unlock sector */
flash_reset (info); /* reset to read mode */
/* now see if it really is locked/unlocked as requested */
*addr = (FPW) 0x00900090;
/* read sector protection at sector address, (A7 .. A0) = 0x02.
* D0 = 1 for each device if protected.
* If at least one device is protected the sector is marked
* protected, but return failure. Mixed protected and
* unprotected devices within a sector should never happen.
*/
value = addr[2] & (FPW) 0x00010001;
if (value == 0)
info->protect[sector] = 0;
else if (value == (FPW) 0x00010001)
info->protect[sector] = 1;
else {
/* error, mixed protected and unprotected */
rcode = 1;
info->protect[sector] = 1;
}
if (info->protect[sector] != prot)
rcode = 1; /* failed to protect/unprotect as requested */
/* reload all protection bits from hardware for now */
flash_sync_real_protect (info);
break;
case FLASH_AM640U:
case FLASH_AM800T:
default:
/* no hardware protect that we support */
info->protect[sector] = prot;
break;
}
return rcode;
}
#endif

1719
board/sixnet/fpgadata.c
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board/sixnet/sixnet.c
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/*
* (C) Copyright 2001, 2002
* Dave Ellis, SIXNET, dge@sixnetio.com.
* Based on code by:
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* and other contributors to U-Boot.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <config.h>
#include <jffs2/jffs2.h>
#include <mpc8xx.h>
#include <net.h> /* for eth_init() */
#include <rtc.h>
#include "sixnet.h"
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define ORMASK(size) ((-size) & OR_AM_MSK)
static long ram_size(ulong *, long);
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_SHOW_BOOT_PROGRESS
void show_boot_progress (int status)
{
#if defined(CONFIG_STATUS_LED)
# if defined(STATUS_LED_BOOT)
if (status == BOOTSTAGE_ID_RUN_OS) {
/* ready to transfer to kernel, make sure LED is proper state */
status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
}
# endif /* STATUS_LED_BOOT */
#endif /* CONFIG_STATUS_LED */
}
#endif
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
* returns 0 if recognized, -1 if unknown
*/
int checkboard (void)
{
puts ("Board: SIXNET SXNI855T\n");
return 0;
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_CMD_PCMCIA)
#error "SXNI855T has no PCMCIA port"
#endif
/* ------------------------------------------------------------------------- */
#define _not_used_ 0xffffffff
/* UPMB table for dual UART. */
/* this table is for 50MHz operation, it should work at all lower speeds */
const uint duart_table[] =
{
/* single read. (offset 0 in upm RAM) */
0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
/* burst read. (offset 8 in upm RAM) */
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* single write. (offset 18 in upm RAM) */
0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
/* burst write. (offset 20 in upm RAM) */
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* refresh. (offset 30 in upm RAM) */
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* exception. (offset 3c in upm RAM) */
_not_used_, _not_used_, _not_used_, _not_used_,
};
/* Load FPGA very early in boot sequence, since it must be
* loaded before the 16C2550 serial channels can be used as
* console channels.
*
* Note: Much of the configuration is not complete. The
* stack is in DPRAM since SDRAM has not been initialized,
* so the stack must be kept small. Global variables
* are still in FLASH, so they cannot be written.
* Only the FLASH, DPRAM, immap and FPGA can be addressed,
* the other chip selects may not have been initialized.
* The clocks have been initialized, so udelay() can be
* used.
*/
#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */
int board_postclk_init (void)
{
/* the data to load to the XCSxxXL FPGA */
static const unsigned char fpgadata[] = {
# include "fpgadata.c"
};
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#define porta (immap->im_ioport.iop_padat)
const unsigned char* pdata;
/* /INITFPGA and DONEFPGA signals are inputs */
immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
/* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
porta &= ~FPGA_PROGRAM_L;
/* Set FPGA as an output */
immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
/* delay a little to make sure FPGA sees it, really
* only need less than a microsecond.
*/
udelay(10);
/* unassert /PROGRAM */
porta |= FPGA_PROGRAM_L;
/* delay while FPGA does last erase, indicated by
* /INITFPGA going high. This should happen within a
* few milliseconds.
*/
/* ### FIXME - a timeout check would be good, maybe flash
* the status LED to indicate the error?
*/
while ((porta & FPGA_INIT_L) == 0)
; /* waiting */
/* write program data to FPGA at the programming address
* so extra /CS1 strobes at end of configuration don't actually
* write to any registers.
*/
fpga = 0xff; /* first write is ignored */
fpga = 0xff; /* fill byte */
fpga = 0xff; /* fill byte */
fpga = 0x4f; /* preamble code */
fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
fpga = 0x4b; /* field check code */
pdata = fpgadata;
/* while no error write out each of the 28 byte frames */
while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
&& pdata < fpgadata + sizeof(fpgadata)) {
fpga = 0x4f; /* preamble code */
/* 21 bytes of data in a frame */
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++); fpga = *(pdata++);
fpga = *(pdata++);
fpga = 0x4b; /* field check code */
fpga = 0xff; /* extended write cycle */
fpga = 0x4b; /* extended write cycle
* (actually 0x4b from bitgen.exe)
*/
fpga = 0xff; /* extended write cycle */
fpga = 0xff; /* extended write cycle */
fpga = 0xff; /* extended write cycle */
}
fpga = 0xff; /* startup byte */
fpga = 0xff; /* startup byte */
fpga = 0xff; /* startup byte */
fpga = 0xff; /* startup byte */
#if 0 /* ### FIXME */
/* If didn't load all the data or FPGA_DONE is low the load failed.
* Maybe someday stop here and flash the status LED? The console
* is not configured, so can't print an error message. Can't write
* global variables to set a flag (except gd?).
* For now it must work.
*/
#endif
/* Now that the FPGA is loaded, set up the Dual UART chip
* selects. Must be done here since it may be used as the console.
*/
upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
memctl->memc_mbmr = DUART_MBMR;
memctl->memc_or5 = DUART_OR_VALUE;
memctl->memc_br5 = DUART_BR5_VALUE;
memctl->memc_or6 = DUART_OR_VALUE;
memctl->memc_br6 = DUART_BR6_VALUE;
return (0);
}
/* ------------------------------------------------------------------------- */
/* base address for SRAM, assume 32-bit port, valid */
#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
/* up to 64MB - will be adjusted for actual size */
#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \
| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
/*
* Miscellaneous platform dependent initializations after running in RAM.
*/
int misc_init_r (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
bd_t *bd = gd->bd;
uchar enetaddr[6];
memctl->memc_or2 = NVRAM_OR_PRELIM;
memctl->memc_br2 = NVRAM_BR_VALUE;
/* Is there any SRAM? Is it 16 or 32 bits wide? */
/* First look for 32-bit SRAM */
bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
if (bd->bi_sramsize == 0) {
/* no 32-bit SRAM, but there could be 16-bit SRAM since
* it would report size 0 when configured for 32-bit bus.
* Try again with a 16-bit bus.
*/
memctl->memc_br2 |= BR_PS_16;
bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
}
if (bd->bi_sramsize == 0) {
memctl->memc_br2 = 0; /* disable select since nothing there */
}
else {
/* adjust or2 for actual size of SRAM */
memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
}
/* set standard MPC8xx clock so kernel will see the time
* even if it doesn't have a DS1306 clock driver.
* This helps with experimenting with standard kernels.
*/
{
ulong tim;
struct rtc_time tmp;
rtc_get(&tmp); /* get time from DS1306 RTC */
/* convert to seconds since 1970 */
tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
immap->im_sitk.sitk_rtck = KAPWR_KEY;
immap->im_sit.sit_rtc = tim;
}
/* set up ethernet address for SCC ethernet. If eth1addr
* is present it gets a unique address, otherwise it
* shares the FEC address.
*/
if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
eth_getenv_enetaddr("ethaddr", enetaddr);
eth_setenv_enetaddr("eth1addr", enetaddr);
}
return (0);
}
#if defined(CONFIG_CMD_NAND)
void nand_init(void)
{
unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'.
*
* The memory size MUST be a power of 2 for this to work.
*
* The only memory modified is 8 bytes at offset 0. This is important
* since for the SRAM this location is reserved for autosizing, so if
* it is modified and the board is reset before ram_size() completes
* no damage is done. Normally even the memory at 0 is preserved. The
* higher SRAM addresses may contain battery backed RAM disk data which
* must never be corrupted.
*/
static long ram_size(ulong *base, long maxsize)
{
volatile long *test_addr;
volatile ulong *base_addr = base;
ulong ofs; /* byte offset from base_addr */
ulong save; /* to make test non-destructive */
ulong save2; /* to make test non-destructive */
long ramsize = -1; /* size not determined yet */
save = *base_addr; /* save value at 0 so can restore */
save2 = *(base_addr+1); /* save value at 4 so can restore */
/* is any SRAM present? */
*base_addr = 0x5555aaaa;
/* It is important to drive the data bus with different data so
* it doesn't remember the value and look like RAM that isn't there.
*/
*(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */
if (*base_addr != 0x5555aaaa)
ramsize = 0; /* no RAM present, or defective */
else {
*base_addr = 0xaaaa5555;
*(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
if (*base_addr != 0xaaaa5555)
ramsize = 0; /* no RAM present, or defective */
}
/* now size it if any is present */
for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
test_addr = (long*)((long)base_addr + ofs); /* location to test */
*base_addr = ~*test_addr;
if (*base_addr == *test_addr)
ramsize = ofs; /* wrapped back to 0, so this is the size */
}
*base_addr = save; /* restore value at 0 */
*(base_addr+1) = save2; /* restore value at 4 */
return (ramsize);
}
/* ------------------------------------------------------------------------- */
/* sdram table based on the FADS manual */
/* for chip MB811171622A-100 */
/* this table is for 50MHz operation, it should work at all lower speeds */
const uint sdram_table[] =
{
/* single read. (offset 0 in upm RAM) */
0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
0x1ff77c47,
/* precharge and Mode Register Set initialization (offset 5).
* This is also entered at offset 6 to do Mode Register Set
* without the precharge.
*/
0x1ff77c34, 0xefeabc34, 0x1fb57c35,
/* burst read. (offset 8 in upm RAM) */
0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* single write. (offset 18 in upm RAM) */
/* FADS had 0x1f27fc04, ...
* but most other boards have 0x1f07fc04, which
* sets GPL0 from A11MPC to 0 1/4 clock earlier,
* like the single read.
* This seems better so I am going with the change.
*/
0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
_not_used_, _not_used_, _not_used_, _not_used_,
/* burst write. (offset 20 in upm RAM) */
0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* refresh. (offset 30 in upm RAM) */
0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
_not_used_, _not_used_, _not_used_, _not_used_,
/* exception. (offset 3c in upm RAM) */
0x7ffffc07, _not_used_, _not_used_, _not_used_ };
/* ------------------------------------------------------------------------- */
#define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */
/* precharge and set Mode Register */
#define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
MCR_MB_CS3 | /* chip select */ \
MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */
/* set Mode Register, no precharge */
#define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
MCR_MB_CS3 | /* chip select */ \
MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */
/* runs refresh loop twice so get 8 refresh cycles */
#define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
MCR_MB_CS3 | /* chip select */ \
MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
/* MAMR values work in either mamr or mbmr */
#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \
((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
| MAMR_DSA_1_CYCL /* 1 cycle disable */ \
| MAMR_RLFA_1X /* Read loop 1 time */ \
| MAMR_WLFA_1X /* Write loop 1 time */ \
| MAMR_TLFA_4X) /* Timer loop 4 times */
/* 8 column SDRAM */
#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \
| MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
| MAMR_G0CLA_A11) /* GPL0 A11[MPC] */
/* 9 column SDRAM */
#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \
| MAMR_AMA_TYPE_1 /* Address MUX 1 */ \
| MAMR_G0CLA_A10) /* GPL0 A10[MPC] */
/* base address 0, 32-bit port, SDRAM UPM, valid */
#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
/* up to 256MB, SAM, G5LS - will be adjusted for actual size */
#define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
/* This is the Mode Select Register value for the SDRAM.
* Burst length: 4
* Burst Type: sequential
* CAS Latency: 2
* Write Burst Length: burst
*/
#define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */
/* ------------------------------------------------------------------------- */
phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
uint size_sdram = 0;
uint size_sdram9 = 0;
uint base = 0; /* SDRAM must start at 0 */
int i;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/* Configure the refresh (mostly). This needs to be
* based upon processor clock speed and optimized to provide
* the highest level of performance.
*
* Preliminary prescaler for refresh.
* This value is selected for four cycles in 31.2 us,
* which gives 8192 cycles in 64 milliseconds.
* This may be too fast, but works for any memory.
* It is adjusted to 4096 cycles in 64 milliseconds if
* possible once we know what memory we have.
*
* We have to be careful changing UPM registers after we
* ask it to run these commands.
*
* PTA - periodic timer period for our design is
* 50 MHz x 31.2us
* --------------- = 195
* 1 x 8 x 1
*
* 50MHz clock
* 31.2us refresh interval
* SCCR[DFBRG] 0
* PTP divide by 8
* 1 chip select
*/
memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
/* The SDRAM Mode Register value is shifted left 2 bits since
* A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
*/
memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */
udelay(200); /* SDRAM needs 200uS before set it up */
/* Now run the precharge/nop/mrs commands. */
memctl->memc_mcr = SDRAM_MCR_PRE;
udelay(2);
/* Run 8 refresh cycles (2 sets of 4) */
memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */
udelay(2);
/* some brands want Mode Register set after the refresh
* cycles. This shouldn't hurt anything for the brands
* that were happy with the first time we set it.
*/
memctl->memc_mcr = SDRAM_MCR_MRS;
udelay(2);
memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */
memctl->memc_or3 = SDRAM_OR_PRELIM;
memctl->memc_br3 = SDRAM_BR_VALUE + base;
/* Some brands need at least 10 DRAM accesses to stabilize.
* It wont hurt the brands that don't.
*/
for (i=0; i<10; ++i) {
volatile ulong *addr = (volatile ulong *)base;
ulong val;
val = *(addr + i);
*(addr + i) = val;
}
/* Check SDRAM memory Size in 8 column mode.
* For a 9 column memory we will get half the actual size.
*/
size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
/* Check SDRAM memory Size in 9 column mode.
* For an 8 column memory we will see at most 4 megabytes.
*/
memctl->memc_mamr = SDRAM_MAMR_9COL;
size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
if (size_sdram < size_sdram9) /* leave configuration at 9 columns */
size_sdram = size_sdram9;
else /* go back to 8 columns */
memctl->memc_mamr = SDRAM_MAMR_8COL;
/* adjust or3 for actual size of SDRAM
*/
memctl->memc_or3 |= ORMASK(size_sdram);
/* Adjust refresh rate depending on SDRAM type.
* For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
* it at the current (fast) rate.
* For 16, 64 and 128 MBit half the rate will do.
*/
if (size_sdram <= 32 * 1024 * 1024)
memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */
return (size_sdram);
}

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board/sixnet/sixnet.h
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Memory map:
*
* ff100000 -> ff13ffff : FPGA CS1
* ff030000 -> ff03ffff : EXPANSION CS7
* ff020000 -> ff02ffff : DATA FLASH CS4
* ff018000 -> ff01ffff : UART B CS6/UPMB
* ff010000 -> ff017fff : UART A CS5/UPMB
* ff000000 -> ff00ffff : IMAP internal to the MPC855T
* f8000000 -> fbffffff : FLASH CS0 up to 64MB
* f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB
* 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB
*/

82
board/sixnet/u-boot.lds
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/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

3
configs/SXNI855T_defconfig
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@ -1,3 +0,0 @@
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_SXNI855T=y

1
doc/README.scrapyard
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
sixnet powerpc mpc8xx - - Dave Ellis <DGE@sixnetio.com>
svm_sc8xx powerpc mpc8xx - - John Zhan <zhanz@sinovee.com>
stxxtc powerpc mpc8xx - - Dan Malek <dan@embeddedalley.com>
omap5912osk arm arm926ejs - - Rishi Bhattacharya <rishi@ti.com>

10
include/commproc.h
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@ -865,16 +865,6 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x00002E00)
#endif /* CONFIG_SPD823TS */
/*** SXNI855T ******************************************************/
#if defined(CONFIG_SXNI855T)
#ifdef CONFIG_FEC_ENET
#define FEC_ENET /* use FEC for Ethernet */
#endif /* CONFIG_FEC_ETHERNET */
#endif /* CONFIG_SXNI855T */
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \

378
include/configs/SXNI855T.h
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@ -1,378 +0,0 @@
/*
* U-Boot configuration for SIXNET SXNI855T CPU board.
* This board is based (loosely) on the Motorola FADS board, so this
* file is based (loosely) on config_FADS860T.h, see it for additional
* credits.
*
* Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Memory map:
*
* ff100000 -> ff13ffff : FPGA CS1
* ff030000 -> ff03ffff : EXPANSION CS7
* ff020000 -> ff02ffff : DATA FLASH CS4
* ff018000 -> ff01ffff : UART B CS6/UPMB
* ff010000 -> ff017fff : UART A CS5/UPMB
* ff000000 -> ff00ffff : IMAP internal to the MPC855T
* f8000000 -> fbffffff : FLASH CS0 up to 64MB
* f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB
* 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB
*/
/* ------------------------------------------------------------------------- */
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#include <mpc8xx_irq.h>
#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */
/* The 855T is just a stripped 860T and needs code for 860, so for now
* at least define 860, 860T and 855T
*/
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC855T 1
#define CONFIG_SYS_TEXT_BASE 0xF8000000
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_SCC1
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 9600
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_HAS_ETH1
/*-----------------------------------------------------------------------
* Definitions for status LED
*/
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */
# define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#ifdef DEV /* development (debug) settings */
#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF
#else /* production settings */
#define CONFIG_BOOT_LED_STATE STATUS_LED_ON
#endif
#define CONFIG_SHOW_BOOT_PROGRESS 1
#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram ip=off"
#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define PB_SCL 0x00000020 /* PB 26 */
#define PB_SDA 0x00000010 /* PB 27 */
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
#define CONFIG_MII 1
#define CONFIG_SYS_DISCOVER_PHY
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_DATE
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save a little memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00100000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CONFIG_SYS_IMMR 0xFF000000
#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SRAM_BASE 0xF4000000
#define CONFIG_SYS_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */
#define CONFIG_SYS_FLASH_BASE 0xF8000000
#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
#define CONFIG_SYS_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */
#define CONFIG_SYS_DFLASH_SIZE 0x00010000
#define CONFIG_SYS_FPGA_BASE 0xFF100000 /* Xilinx FPGA */
#define CONFIG_SYS_FPGA_PROG 0xFF130000 /* Programming address */
#define CONFIG_SYS_FPGA_SIZE 0x00040000 /* 256KiB usable */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
* AMD 29LV641 has 128 64K sectors in 8MB
*/
#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* set the PLL, the low-power modes and the reset control (15-29)
*/
#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
#define CONFIG_SYS_DER 0
/* Because of the way the 860 starts up and assigns CS0 the
* entire address space, we have to set the memory controller
* differently. Normally, you write the option register
* first, and then enable the chip select by writing the
* base register. For CS0, you must write the base register
* first, followed by the option register.
*/
/*
* Init Memory Controller:
*
**********************************************************
* BR0 and OR0 (FLASH)
*/
#define CONFIG_SYS_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_FLASH_16BIT
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
#define CONFIG_SYS_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */
/**********************************************************
* BR1 and OR1 (FPGA)
* These preliminary values are also the final values.
*/
#define CONFIG_SYS_OR_TIMING_FPGA \
(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
#define CONFIG_SYS_OR1_PRELIM (((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA)
/**********************************************************
* BR4 and OR4 (data flash)
* These preliminary values are also the final values.
*/
#define CONFIG_SYS_OR_TIMING_DFLASH \
(OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH)
/**********************************************************
* BR5/6 and OR5/6 (Dual UART)
*/
#define CONFIG_SYS_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */
#define CONFIG_SYS_DUARTA_BASE 0xff010000
#define CONFIG_SYS_DUARTB_BASE 0xff018000
#define DUART_MBMR 0
#define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI)
#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
#define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
#define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
#define CONFIG_RESET_ON_PANIC /* reset if system panic() */
#define CONFIG_ENV_IS_IN_FLASH
#ifdef CONFIG_ENV_IS_IN_FLASH
/* environment is in FLASH */
#define CONFIG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */
#define CONFIG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */
#define CONFIG_ENV_SECT_SIZE 0x00010000
#define CONFIG_ENV_SIZE 0x00002000
#else
/* environment is in EEPROM */
#define CONFIG_ENV_IS_IN_EEPROM 1
#define CONFIG_ENV_OFFSET 0 /* at beginning of EEPROM */
#define CONFIG_ENV_SIZE 1024 /* Use only a part of it*/
#endif
#if 1
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR "delayabit"
#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */
#endif
#endif /* __CONFIG_H */
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