This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
10 years ago
committed by
Tom Rini
parent
daf770864d
commit
47b87d2eed
@ -1,12 +0,0 @@ |
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if TARGET_RD6281A |
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|
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config SYS_BOARD |
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default "rd6281a" |
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config SYS_VENDOR |
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default "Marvell" |
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config SYS_CONFIG_NAME |
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default "rd6281a" |
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endif |
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@ -1,6 +0,0 @@ |
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RD6281A BOARD |
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M: Prafulla Wadaskar <prafulla@marvell.com> |
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S: Maintained |
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F: board/Marvell/rd6281a/ |
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F: include/configs/rd6281a.h |
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F: configs/rd6281a_defconfig |
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@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2009
|
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := rd6281a.o
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@ -1,151 +0,0 @@ |
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# |
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# (C) Copyright 2009 |
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# Marvell Semiconductor <www.marvell.com> |
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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# Refer doc/README.kwbimage for more details about how-to configure |
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# and create kirkwood boot image |
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# |
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|
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# Boot Media configurations |
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BOOT_FROM nand |
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NAND_ECC_MODE default |
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NAND_PAGE_SIZE 0x0800 |
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|
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# SOC registers configuration using bootrom header extension |
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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|
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# Configure RGMII-0 interface pad voltage to 1.8V |
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DATA 0xFFD100e0 0x1b1b1b9b |
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz |
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DATA 0xFFD01400 0x43000c30 # DDR Configuration register |
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# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) |
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# bit23-14: zero |
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# bit24: 1= enable exit self refresh mode on DDR access |
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# bit25: 1 required |
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# bit29-26: zero |
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# bit31-30: 01 |
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DATA 0xFFD01404 0x37543000 # DDR Controller Control Low |
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# bit 4: 0=addr/cmd in smame cycle |
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# bit 5: 0=clk is driven during self refresh, we don't care for APX |
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# bit 6: 0=use recommended falling edge of clk for addr/cmd |
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# bit14: 0=input buffer always powered up |
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# bit18: 1=cpu lock transaction enabled |
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# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 |
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# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM |
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# bit30-28: 3 required |
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# bit31: 0=no additional STARTBURST delay |
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DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) |
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# bit3-0: TRAS lsbs |
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# bit7-4: TRCD |
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# bit11- 8: TRP |
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# bit15-12: TWR |
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# bit19-16: TWTR |
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# bit20: TRAS msb |
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# bit23-21: 0x0 |
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# bit27-24: TRRD |
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# bit31-28: TRTP |
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DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) |
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# bit6-0: TRFC |
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# bit8-7: TR2R |
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# bit10-9: TR2W |
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# bit12-11: TW2W |
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# bit31-13: zero required |
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DATA 0xFFD01410 0x00000099 # DDR Address Control |
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# bit1-0: 00, Cs0width=x8 |
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# bit3-2: 11, Cs0size=1Gb |
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# bit5-4: 00, Cs1width=x8 |
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# bit7-6: 11, Cs1size=1Gb |
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# bit9-8: 00, Cs2width=nonexistent |
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# bit11-10: 00, Cs2size =nonexistent |
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# bit13-12: 00, Cs3width=nonexistent |
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# bit15-14: 00, Cs3size =nonexistent |
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# bit16: 0, Cs0AddrSel |
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# bit17: 0, Cs1AddrSel |
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# bit18: 0, Cs2AddrSel |
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# bit19: 0, Cs3AddrSel |
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# bit31-20: 0 required |
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
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# bit0: 0, OpenPage enabled |
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# bit31-1: 0 required |
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DATA 0xFFD01418 0x00000000 # DDR Operation |
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# bit3-0: 0x0, DDR cmd |
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# bit31-4: 0 required |
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DATA 0xFFD0141C 0x00000C52 # DDR Mode |
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# bit2-0: 2, BurstLen=2 required |
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# bit3: 0, BurstType=0 required |
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# bit6-4: 4, CL=5 |
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# bit7: 0, TestMode=0 normal |
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# bit8: 0, DLL reset=0 normal |
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# bit11-9: 6, auto-precharge write recovery ???????????? |
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# bit12: 0, PD must be zero |
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# bit31-13: 0 required |
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DATA 0xFFD01420 0x00000004 # DDR Extended Mode |
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# bit0: 0, DDR DLL enabled |
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# bit1: 0, DDR drive strenght normal |
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# bit2: 1, DDR ODT control lsd (disabled) |
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# bit5-3: 000, required |
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# bit6: 0, DDR ODT control msb, (disabled) |
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# bit9-7: 000, required |
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# bit10: 0, differential DQS enabled |
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# bit11: 0, required |
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# bit12: 0, DDR output buffer enabled |
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# bit31-13: 0 required |
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DATA 0xFFD01424 0x0000F17F # DDR Controller Control High |
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# bit2-0: 111, required |
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# bit3 : 1 , MBUS Burst Chop disabled |
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# bit6-4: 111, required |
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# bit7 : 0 |
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# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz |
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# bit9 : 0 , no half clock cycle addition to dataout |
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# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals |
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# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh |
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# bit15-12: 1111 required |
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# bit31-16: 0 required |
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DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) |
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DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) |
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 |
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DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size |
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# bit0: 1, Window enabled |
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# bit1: 0, Write Protect disabled |
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# bit3-2: 00, CS0 hit selected |
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# bit23-4: ones, required |
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# bit31-24: 0x0F, Size (i.e. 256MB) |
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DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb |
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DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 |
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
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DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) |
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# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 |
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# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 |
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# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 |
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# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 |
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) |
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# bit1-0: 00, ODT0 controlled by ODT Control (low) register above |
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# bit3-2: 01, ODT1 active NEVER! |
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# bit31-4: zero, required |
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DATA 0xFFD0149C 0x0000E40F # CPU ODT Control |
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
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#bit0=1, enable DDR init upon this register write |
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# End of Header extension |
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DATA 0x0 0x0 |
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@ -1,157 +0,0 @@ |
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/*
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/soc.h> |
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#include <asm/arch/mpp.h> |
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#include "rd6281a.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_early_init_f(void) |
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{ |
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/*
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* default gpio configuration |
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* There are maximum 64 gpios controlled through 2 sets of registers |
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* the below configuration configures mainly initial LED status |
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*/ |
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mvebu_config_gpio(RD6281A_OE_VAL_LOW, |
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RD6281A_OE_VAL_HIGH, |
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RD6281A_OE_LOW, RD6281A_OE_HIGH); |
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/* Multi-Purpose Pins Functionality configuration */ |
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static const u32 kwmpp_config[] = { |
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MPP0_NF_IO2, |
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MPP1_NF_IO3, |
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MPP2_NF_IO4, |
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MPP3_NF_IO5, |
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MPP4_NF_IO6, |
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MPP5_NF_IO7, |
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MPP6_SYSRST_OUTn, |
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MPP7_GPO, |
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MPP8_TW_SDA, |
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MPP9_TW_SCK, |
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MPP10_UART0_TXD, |
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MPP11_UART0_RXD, |
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MPP12_SD_CLK, |
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MPP13_SD_CMD, |
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MPP14_SD_D0, |
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MPP15_SD_D1, |
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MPP16_SD_D2, |
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MPP17_SD_D3, |
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MPP18_NF_IO0, |
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MPP19_NF_IO1, |
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MPP20_GE1_0, |
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MPP21_GE1_1, |
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MPP22_GE1_2, |
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MPP23_GE1_3, |
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MPP24_GE1_4, |
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MPP25_GE1_5, |
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MPP26_GE1_6, |
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MPP27_GE1_7, |
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MPP28_GPIO, |
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MPP29_GPIO, |
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MPP30_GE1_10, |
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MPP31_GE1_11, |
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MPP32_GE1_12, |
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MPP33_GE1_13, |
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MPP34_GE1_14, |
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MPP35_GPIO, |
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MPP36_AUDIO_SPDIFI, |
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MPP37_AUDIO_SPDIFO, |
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MPP38_GPIO, |
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MPP39_TDM_SPI_CS0, |
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MPP40_TDM_SPI_SCK, |
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MPP41_TDM_SPI_MISO, |
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MPP42_TDM_SPI_MOSI, |
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MPP43_TDM_CODEC_INTn, |
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MPP44_GPIO, |
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MPP45_TDM_PCLK, |
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MPP46_TDM_FS, |
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MPP47_TDM_DRX, |
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MPP48_TDM_DTX, |
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MPP49_GPIO, |
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0 |
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}; |
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kirkwood_mpp_conf(kwmpp_config, NULL); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/*
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* arch number of board |
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*/ |
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gd->bd->bi_arch_number = MACH_TYPE_RD88F6281; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
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return 0; |
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} |
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void mv_phy_88e1116_init(char *name) |
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{ |
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u16 reg; |
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u16 devadr; |
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if (miiphy_set_current_dev(name)) |
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return; |
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/* command to read PHY dev address */ |
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { |
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printf("Err..%s could not read PHY dev address\n", |
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__FUNCTION__); |
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return; |
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} |
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/*
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* Enable RGMII delay on Tx and Rx for CPU port |
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* Ref: sec 4.7.2 of chip datasheet |
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*/ |
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); |
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); |
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); |
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); |
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); |
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/* reset the phy */ |
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if (miiphy_read (name, devadr, MII_BMCR, ®) != 0) { |
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printf("Err..(%s) PHY status read failed\n", __FUNCTION__); |
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return; |
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} |
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if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) { |
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printf("Err..(%s) PHY reset failed\n", __FUNCTION__); |
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return; |
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} |
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printf("88E1116 Initialized on %s\n", name); |
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} |
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/* Configure and enable Switch and PHY */ |
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void reset_phy(void) |
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{ |
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/* configure and initialize switch */ |
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struct mv88e61xx_config swcfg = { |
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.name = "egiga0", |
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.vlancfg = MV88E61XX_VLANCFG_ROUTER, |
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.rgmii_delay = MV88E61XX_RGMII_DELAY_EN, |
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.led_init = MV88E61XX_LED_INIT_EN, |
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.portstate = MV88E61XX_PORTSTT_FORWARDING, |
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.cpuport = (1 << 5), |
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.ports_enabled = 0x3f, |
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}; |
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mv88e61xx_switch_initialize(&swcfg); |
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/* configure and initialize PHY */ |
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mv_phy_88e1116_init("egiga1"); |
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} |
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@ -1,25 +0,0 @@ |
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/*
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __RD6281A_H |
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#define __RD6281A_H |
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#define RD6281A_OE_LOW (~(1 << 7)) |
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#define RD6281A_OE_HIGH (~(1 << 2 | 1 << 12)) |
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#define RD6281A_OE_VAL_LOW (0) |
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#define RD6281A_OE_VAL_HIGH (1 << 12) |
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/* PHY related */ |
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#define MV88E1116_LED_FCTRL_REG 10 |
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#define MV88E1116_CPRSP_CR3_REG 21 |
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#define MV88E1116_MAC_CTRL_REG 21 |
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#define MV88E1116_PGADR_REG 22 |
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) |
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) |
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#endif /* __RD6281A_H */ |
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@ -1,6 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_KIRKWOOD=y |
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CONFIG_TARGET_RD6281A=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_SETEXPR is not set |
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@ -1,96 +0,0 @@ |
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/*
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _CONFIG_RD6281A_H |
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#define _CONFIG_RD6281A_H |
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/*
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* Version number information |
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*/ |
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#define CONFIG_IDENT_STRING "\nMarvell-RD6281A" |
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/*
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* High Level Configuration Options (easy to change) |
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*/ |
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#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ |
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#define CONFIG_KW88F6281 1 /* SOC Name */ |
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#define CONFIG_MACH_RD6281A /* Machine type */ |
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
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/*
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* Commands configuration |
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*/ |
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#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_ENV |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_NAND |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_USB |
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#define CONFIG_CMD_IDE |
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/*
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* mv-common.h should be defined after CMD configs since it used them |
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* to enable certain macros |
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*/ |
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#include "mv-common.h" |
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/*
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* Environment variables configurations |
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*/ |
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#ifdef CONFIG_CMD_NAND |
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#define CONFIG_ENV_IS_IN_NAND 1 |
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ |
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#else |
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#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ |
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#endif |
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/*
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* max 4k env size is enough, but in case of nand |
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* it has to be rounded to sector size |
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*/ |
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#define CONFIG_ENV_SIZE 0x20000 /* 128k */ |
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#define CONFIG_ENV_ADDR 0x40000 |
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#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */ |
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/*
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* Default environment variables |
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*/ |
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#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ |
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"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
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"${x_bootcmd_usb}; bootm 0x6400000;" |
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#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \ |
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"3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0" |
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#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ |
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"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
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"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
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"x_bootcmd_usb=usb start\0" \
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"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" |
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/*
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* Ethernet Driver configuration |
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*/ |
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#ifdef CONFIG_CMD_NET |
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#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ |
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#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE |
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#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */ |
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#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */ |
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#define CONFIG_PHY_BASE_ADR 0x0A |
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#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */ |
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#endif /* CONFIG_CMD_NET */ |
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/*
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* SATA Driver configuration |
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*/ |
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#ifdef CONFIG_MVSATA_IDE |
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#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET |
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#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET |
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#endif /*CONFIG_MVSATA_IDE*/ |
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#endif /* _CONFIG_RD6281A_H */ |
||||
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Reference in new issue