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arm: imx: add i.MX6SLL EVK board support

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Add i.MX6SLL EVK board support.
1. Add imx6sll-evk device tree.
2. Enable SDHC/I2C/UART.
3. Enable REGULATOR/PMIC/I2C/GPIO/SDHC/PINCTRL driver.

Boot Log:
U-Boot 2016.11-00127-gc635871-dirty (Nov 24 2016 - 13:28:19 +0800)

CPU:   Freescale i.MX6SLL rev1.0 at 792MHz
CPU:   Commercial temperature grade (0C to 95C)Reset cause: POR
Model: Freescale i.MX6SLL EVK Board
Board: MX6SLL EVK
DRAM:  2 GiB
i2c bus 0 at 35258368, no gpio pinctrl state.
PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
master
Peng Fan 8 years ago committed by Stefano Babic
parent 3445373691
commit 47f73504d8
9 changed files with 1267 additions and 0 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 7
      arch/arm/cpu/armv7/mx6/Kconfig
  2. 1
      arch/arm/dts/Makefile
  3. 801
      arch/arm/dts/imx6sll-evk.dts
  4. 12
      board/freescale/mx6sllevk/Kconfig
  5. 6
      board/freescale/mx6sllevk/Makefile
  6. 121
      board/freescale/mx6sllevk/imximage.cfg
  7. 131
      board/freescale/mx6sllevk/mx6sllevk.c
  8. 36
      configs/mx6sllevk_defconfig
  9. 152
      include/configs/mx6sllevk.h

7
arch/arm/cpu/armv7/mx6/Kconfig
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@ -146,6 +146,12 @@ config TARGET_MX6SLEVK
bool "mx6slevk"
select SUPPORT_SPL
config TARGET_MX6SLLEVK
bool "mx6sll evk"
select MX6SLL
select DM
select DM_THERMAL
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
select MX6SX
@ -283,6 +289,7 @@ source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sllevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"

1
arch/arm/dts/Makefile
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@ -294,6 +294,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
bk4r1.dtb
dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6sll-evk.dtb \
imx6dl-icore.dtb \
imx6q-icore.dtb

801
arch/arm/dts/imx6sll-evk.dts
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@ -0,0 +1,801 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sll.dtsi"
/ {
model = "Freescale i.MX6SLL EVK Board";
compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
memory {
reg = <0x80000000 0x80000000>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
battery: max8903@0 {
compatible = "fsl,max8903-charger";
pinctrl-names = "default";
dok_input = <&gpio4 13 1>;
uok_input = <&gpio4 13 1>;
chg_input = <&gpio4 15 1>;
flt_input = <&gpio4 14 1>;
fsl,dcm_always_high;
fsl,dc_valid;
fsl,adc_disable;
status = "okay";
};
pxp_v4l2_out {
compatible = "fsl,imx6sl-pxp-v4l2";
status = "okay";
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_aud3v: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "wm8962-supply-3v15";
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-boot-on;
};
reg_aud4v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "wm8962-supply-4v2";
regulator-min-microvolt = <4325000>;
regulator-max-microvolt = <4325000>;
regulator-boot-on;
};
reg_lcd: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-pwr";
gpio = <&gpio4 8 0>;
enable-active-high;
};
reg_sd1_vmmc: sd1_vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_sd2_vmmc: sd2_vmmc {
compatible = "regulator-fixed";
regulator-name = "eMMC-VCCQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
reg_sd3_vmmc: sd3_vmmc {
compatible = "regulator-fixed";
regulator-name = "SD3_WIFI";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
cpu-dai = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
codec-master;
hp-det-gpios = <&gpio4 24 1>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux3>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <393216000>;
};
&cpu0 {
arm-supply = <&sw1a_reg>;
soc-supply = <&sw1c_reg>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
max17135: max17135@48 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_max17135>;
compatible = "maxim,max17135";
reg = <0x48>;
status = "okay";
vneg_pwrup = <1>;
gvee_pwrup = <2>;
vpos_pwrup = <10>;
gvdd_pwrup = <12>;
gvdd_pwrdn = <1>;
vpos_pwrdn = <2>;
gvee_pwrdn = <8>;
vneg_pwrdn = <10>;
gpio_pmic_pwrgood = <&gpio2 13 0>;
gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
gpio_pmic_wakeup = <&gpio2 14 0>;
gpio_pmic_v3p3 = <&gpio2 7 0>;
gpio_pmic_intr = <&gpio2 12 0>;
regulators {
DISPLAY_reg: DISPLAY {
regulator-name = "DISPLAY";
};
GVDD_reg: GVDD {
/* 20v */
regulator-name = "GVDD";
};
GVEE_reg: GVEE {
/* -22v */
regulator-name = "GVEE";
};
HVINN_reg: HVINN {
/* -22v */
regulator-name = "HVINN";
};
HVINP_reg: HVINP {
/* 20v */
regulator-name = "HVINP";
};
VCOM_reg: VCOM {
regulator-name = "VCOM";
/* 2's-compliment, -4325000 */
regulator-min-microvolt = <0xffbe0178>;
/* 2's-compliment, -500000 */
regulator-max-microvolt = <0xfff85ee0>;
};
VNEG_reg: VNEG {
/* -15v */
regulator-name = "VNEG";
};
VPOS_reg: VPOS {
/* 15v */
regulator-name = "VPOS";
};
V3P3_reg: V3P3 {
regulator-name = "V3P3";
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
DCVDD-supply = <&vgen3_reg>;
DBVDD-supply = <&reg_aud3v>;
AVDD-supply = <&vgen3_reg>;
CPVDD-supply = <&vgen3_reg>;
MICVDD-supply = <&reg_aud3v>;
PLLVDD-supply = <&vgen3_reg>;
SPKVDD1-supply = <&reg_aud4v>;
SPKVDD2-supply = <&reg_aud4v>;
amic-mono;
};
};
&gpc {
fsl,ldo-bypass = <1>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6sll-evk {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
/*
* Must set the LVE of pad SD2_RESET, otherwise current
* leakage through eMMC chip will pull high the VCCQ to
* 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch.
*/
MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
/* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */
MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
>;
};
pinctrl_audmux3: audmux3grp {
fsl,pins = <
MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
>;
};
pinctrl_csi1: csi1grp {
fsl,pins = <
MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088
MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088
MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088
MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088
MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088
MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088
MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088
MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088
MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088
MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088
MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088
MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088
MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
>;
};
pinctrl_epdc0: epdcgrp0 {
fsl,pins = <
MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1
MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1
MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1
MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1
MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1
MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1
MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1
MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1
MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1
MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1
MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1
MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1
MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1
MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1
MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1
MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1
MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1
MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1
MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1
MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1
MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1
MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1
MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1
MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1
MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79
MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79
MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79
MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79
MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79
MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79
MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79
MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79
MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79
MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79
MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79
MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79
MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79
MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79
MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79
MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79
MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79
MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79
MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79
MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79
MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79
MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79
MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79
MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79
MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79
MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79
MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79
MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79
MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79
>;
};
pinctrl_max17135: max17135grp-1 {
fsl,pins = <
MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */
MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */
MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */
MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */
MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */
MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1
MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1
MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1
MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart5dte: uart5dtegrp {
fsl,pins = <
MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1
MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1
MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1
MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059
MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9
MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
fsl,pins = <
MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9
MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059
MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059
MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059
MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059
MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9
MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9
MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9
MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9
MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
fsl,pins = <
MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9
MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9
MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9
MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9
MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13059
MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059
MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059
MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059
MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9
MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
fsl,pins = <
MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9
MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1
MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1
>;
};
pinctrl_pwm1: pmw1grp {
fsl,pins = <
MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0
>;
};
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
lcd-supply = <&reg_lcd>;
display = <&display>;
status = "okay";
display: display {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pxp {
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,uart-has-rtscts;
/* for DTE mode, add below change */
/* fsl,dte-mode; */
/* pinctrl-0 = <&pinctrl_uart5dte>; */
status = "disabled";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&reg_sd1_vmmc>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vqmmc-supply = <&reg_sd2_vmmc>;
bus-width = <8>;
no-removable;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&reg_sd3_vmmc>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
disable-over-current;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
};
&epdc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc0>;
V3P3-supply = <&V3P3_reg>;
VCOM-supply = <&VCOM_reg>;
DISPLAY-supply = <&DISPLAY_reg>;
status = "okay";
};
&ssi2 {
status = "okay";
};

12
board/freescale/mx6sllevk/Kconfig
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if TARGET_MX6SLLEVK
config SYS_BOARD
default "mx6sllevk"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "mx6sllevk"
endif

6
board/freescale/mx6sllevk/Makefile
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# (C) Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx6sllevk.o

121
board/freescale/mx6sllevk/imximage.cfg
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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020E0550 0x00080000
DATA 4 0x020E0534 0x00000000
DATA 4 0x020E02AC 0x00000030
DATA 4 0x020E0548 0x00000030
DATA 4 0x020E052C 0x00000030
DATA 4 0x020E0530 0x00020000
DATA 4 0x020E02B0 0x00003030
DATA 4 0x020E02B4 0x00003030
DATA 4 0x020E02B8 0x00003030
DATA 4 0x020E02BC 0x00003030
DATA 4 0x020E0540 0x00020000
DATA 4 0x020E0544 0x00000030
DATA 4 0x020E054C 0x00000030
DATA 4 0x020E0554 0x00000030
DATA 4 0x020E0558 0x00000030
DATA 4 0x020E0294 0x00000030
DATA 4 0x020E0298 0x00000030
DATA 4 0x020E029C 0x00000030
DATA 4 0x020E02A0 0x00000030
DATA 4 0x020E02C0 0x00082030
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B085c 0x084700C7
DATA 4 0x021B0890 0x00400000
DATA 4 0x021B0848 0x3F393B3C
DATA 4 0x021B0850 0x262C3826
DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333
DATA 4 0x021B0824 0x33333333
DATA 4 0x021B0828 0x33333333
DATA 4 0x021B082C 0xf3333333
DATA 4 0x021B0830 0xf3333333
DATA 4 0x021B0834 0xf3333333
DATA 4 0x021B0838 0xf3333333
DATA 4 0x021B08C0 0x24922492
DATA 4 0x021B08b8 0x00000800
DATA 4 0x021B0004 0x00020052
DATA 4 0x021B000C 0x53574333
DATA 4 0x021B0010 0x00100B22
DATA 4 0x021B0038 0x00170778
DATA 4 0x021B0014 0x00C700DB
DATA 4 0x021B0018 0x00201718
DATA 4 0x021B002C 0x0F9F26D2
DATA 4 0x021B0030 0x009F0E10
DATA 4 0x021B0040 0x0000005F
DATA 4 0x021B0000 0xC4190000
DATA 4 0x021B083C 0x20000000
DATA 4 0x021B001C 0x00008050
DATA 4 0x021B001C 0x00008058
DATA 4 0x021B001C 0x003F8030
DATA 4 0x021B001C 0x003F8038
DATA 4 0x021B001C 0xFF0A8030
DATA 4 0x021B001C 0xFF0A8038
DATA 4 0x021B001C 0x04028030
DATA 4 0x021B001C 0x04028038
DATA 4 0x021B001C 0x83018030
DATA 4 0x021B001C 0x83018038
DATA 4 0x021B001C 0x01038030
DATA 4 0x021B001C 0x01038038
DATA 4 0x021B0020 0x00001800
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B0004 0x00020052
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000

131
board/freescale/mx6sllevk/mx6sllevk.c
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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_DM_PMIC_PFUZE100
int power_init_board(void)
{
struct udevice *dev;
int ret;
u32 dev_id, rev_id, i;
u32 switch_num = 6;
u32 offset = PFUZE100_SW1CMODE;
ret = pmic_get("pfuze100", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)
return ret;
dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* Init mode to APS_PFM */
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
for (i = 0; i < switch_num - 1; i++)
pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
/* set SW1AB staby volatage 0.975V */
pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
/* set SW1C staby volatage 0.975V */
pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
return 0;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int board_late_init(void)
{
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
return 0;
}
int checkboard(void)
{
puts("Board: MX6SLL EVK\n");
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int mmc_map_to_kernel_blk(int devno)
{
return devno;
}

36
configs/mx6sllevk_defconfig
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CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SLLEVK=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y

152
include/configs/mx6sllevk.h
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/*
* Copyright 2013-2016 Freescale Semiconductor, Inc.
*
* Configuration settings for the Freescale i.MX6SL EVK board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "mx6_common.h"
#ifdef CONFIG_SECURE_BOOT
#ifndef CONFIG_CSF_SIZE
#define CONFIG_CSF_SIZE 0x4000
#endif
#endif
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/* I2C Configs */
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"epdc_waveform=epdc_splash.bin\0" \
"script=boot.scr\0" \
"image=zImage\0" \
"console=ttymxc0\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=imx6sll-evk.dtb\0" \
"fdt_addr=0x83000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"usb start; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_2G
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Environment organization */
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
#define CONFIG_ENV_OFFSET (12 * SZ_64K)
#define CONFIG_ENV_IS_IN_MMC
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_IMX_THERMAL
#define CONFIG_IOMUX_LPSR
#endif /* __CONFIG_H */
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