Tom Rini
9 years ago
commit
4832e17787
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/*
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* Copyright (c) Xilinx, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/*typedef unsigned int u32; */ |
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/** do we need to make this name more unique ? **/ |
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/*extern u32 ps7_init_data[]; */ |
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extern unsigned long *ps7_ddr_init_data; |
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extern unsigned long *ps7_mio_init_data; |
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extern unsigned long *ps7_pll_init_data; |
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extern unsigned long *ps7_clock_init_data; |
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extern unsigned long *ps7_peripherals_init_data; |
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#define OPCODE_EXIT 0U |
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#define OPCODE_CLEAR 1U |
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#define OPCODE_WRITE 2U |
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#define OPCODE_MASKWRITE 3U |
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#define OPCODE_MASKPOLL 4U |
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#define OPCODE_MASKDELAY 5U |
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#define NEW_PS7_ERR_CODE 1 |
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/* Encode number of arguments in last nibble */ |
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#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0) |
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#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr |
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#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val |
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#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val |
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#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask |
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#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask |
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/* Returns codes of PS7_Init */ |
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#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */ |
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#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */ |
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#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */ |
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#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */ |
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#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */ |
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#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */ |
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/* Silicon Versions */ |
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#define PCW_SILICON_VERSION_1 0 |
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#define PCW_SILICON_VERSION_2 1 |
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#define PCW_SILICON_VERSION_3 2 |
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/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ |
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#define PS7_POST_CONFIG |
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/* Freq of all peripherals */ |
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#define APU_FREQ 650000000 |
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#define DDR_FREQ 525000000 |
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#define DCI_FREQ 10096154 |
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#define QSPI_FREQ 200000000 |
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#define SMC_FREQ 10000000 |
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#define ENET0_FREQ 125000000 |
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#define ENET1_FREQ 10000000 |
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#define USB0_FREQ 60000000 |
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#define USB1_FREQ 60000000 |
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#define SDIO_FREQ 50000000 |
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#define UART_FREQ 50000000 |
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#define SPI_FREQ 10000000 |
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#define I2C_FREQ 108333336 |
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#define WDT_FREQ 108333336 |
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#define TTC_FREQ 50000000 |
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#define CAN_FREQ 10000000 |
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#define PCAP_FREQ 200000000 |
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#define TPIU_FREQ 200000000 |
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#define FPGA0_FREQ 100000000 |
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#define FPGA1_FREQ 175000000 |
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#define FPGA2_FREQ 12264151 |
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#define FPGA3_FREQ 100000000 |
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/* For delay calculation using global registers*/ |
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#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 |
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#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 |
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#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 |
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#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 |
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int ps7_config(unsigned long *); |
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int ps7_init(void); |
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int ps7_post_config(void); |
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int ps7_debug(void); |
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char *getPS7MessageInfo(unsigned key); |
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void perf_start_clock(void); |
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void perf_disable_clock(void); |
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void perf_reset_clock(void); |
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void perf_reset_and_start_timer(void); |
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int get_number_of_cycles_for_delay(unsigned int delay); |
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#ifdef __cplusplus |
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} |
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#endif |
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@ -1,9 +1,9 @@ |
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CONFIG_MICROBLAZE=y |
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
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CONFIG_TARGET_MICROBLAZE_GENERIC=y |
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CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" |
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CONFIG_SPL=y |
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CONFIG_SYS_PROMPT="U-Boot-mONStR> " |
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CONFIG_CMD_GPIO=y |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_OF_CONTROL=y |
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CONFIG_OF_EMBED=y |
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