* 'master' of git://git.denx.de/u-boot-nds32: board/adp-ag102: add configuration of adp-ag102 board/adp-ag102: add board specific files nds32/ag102: add ag102 soc support nds32/ag102: add header support of ag102 socmaster
Wolfgang Denk
13 years ago
commit
4868049309
@ -0,0 +1,58 @@ |
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#
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# (C) Copyright 2009
|
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# Copyright (C) 2011 Andes Technology Corporation
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# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(SOC).o
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COBJS-y := cpu.o timer.o
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ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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SOBJS := lowlevel_init.o
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endif |
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ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG |
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SOBJS += watchdog.o
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endif |
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
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all: $(obj).depend $(LIB) |
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$(LIB): $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,54 @@ |
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* Generate definitions needed by assembly language modules. |
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* This code generates raw asm output which is post-processed to extract |
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* and format the required data. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#include <common.h> |
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#include <linux/kbuild.h> |
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int main(void) |
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{ |
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#ifdef CONFIG_FTSMC020 |
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OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); |
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OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); |
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#endif |
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BLANK(); |
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#ifdef CONFIG_FTAHBC020S |
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OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); |
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OFFSET(FTAHBC020S_CR, ftahbc02s, cr); |
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#endif |
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BLANK(); |
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#ifdef CONFIG_ANDES_PCU |
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OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */ |
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#endif |
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BLANK(); |
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#ifdef CONFIG_DWCDDR21MCTL |
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OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */ |
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OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */ |
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OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */ |
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OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */ |
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OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */ |
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OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */ |
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OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */ |
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OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */ |
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OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */ |
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OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */ |
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OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */ |
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OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */ |
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OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */ |
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OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */ |
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OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */ |
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OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */ |
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OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */ |
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OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */ |
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OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */ |
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#endif |
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return 0; |
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} |
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@ -0,0 +1,195 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
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* |
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* Copyright (C) 2011 Andes Technology Corporation |
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/* CPU specific code */ |
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#include <common.h> |
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#include <command.h> |
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#include <watchdog.h> |
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#include <asm/cache.h> |
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#include <faraday/ftwdt010_wdt.h> |
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/*
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* cleanup_before_linux() is called just before we call linux |
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* it prepares the processor for linux |
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* |
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* we disable interrupt and caches. |
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*/ |
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int cleanup_before_linux(void) |
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{ |
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disable_interrupts(); |
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#ifdef CONFIG_MMU |
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/* turn off I/D-cache */ |
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icache_disable(); |
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dcache_disable(); |
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/* flush I/D-cache */ |
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invalidate_icac(); |
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invalidate_dcac(); |
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#endif |
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return 0; |
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} |
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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disable_interrupts(); |
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/*
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* reset to the base addr of andesboot. |
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* currently no ROM loader at addr 0. |
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* do not use reset_cpu(0); |
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*/ |
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#ifdef CONFIG_FTWDT010_WATCHDOG |
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/*
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* workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead |
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* automatic hardware reset when booting Linux. |
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* Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here. |
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*/ |
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ftwdt010_wdt_reset(); |
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#endif /* CONFIG_FTWDT010_WATCHDOG */ |
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hang(); |
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/*NOTREACHED*/ |
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} |
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static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) |
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{ |
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if (cache == ICACHE) |
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return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
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>> ICM_CFG_OFF_ISZ) - 1); |
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else |
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return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
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>> DCM_CFG_OFF_DSZ) - 1); |
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} |
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void dcache_flush_range(unsigned long start, unsigned long end) |
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{ |
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unsigned long line_size; |
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line_size = CACHE_LINE_SIZE(DCACHE); |
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while (end > start) { |
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start)); |
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)); |
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start += line_size; |
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} |
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} |
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void icache_inval_range(unsigned long start, unsigned long end) |
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{ |
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unsigned long line_size; |
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line_size = CACHE_LINE_SIZE(ICACHE); |
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while (end > start) { |
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__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start)); |
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start += line_size; |
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} |
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} |
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void flush_cache(unsigned long addr, unsigned long size) |
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{ |
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dcache_flush_range(addr, addr + size); |
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icache_inval_range(addr, addr + size); |
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} |
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void icache_enable(void) |
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{ |
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__asm__ __volatile__ ( |
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"mfsr $p0, $mr8\n\t" |
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"ori $p0, $p0, 0x01\n\t" |
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"mtsr $p0, $mr8\n\t" |
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"isb\n\t" |
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); |
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} |
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void icache_disable(void) |
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{ |
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__asm__ __volatile__ ( |
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"mfsr $p0, $mr8\n\t" |
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"li $p1, ~0x01\n\t" |
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"and $p0, $p0, $p1\n\t" |
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"mtsr $p0, $mr8\n\t" |
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"isb\n\t" |
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); |
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} |
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int icache_status(void) |
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{ |
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int ret; |
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__asm__ __volatile__ ( |
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"mfsr $p0, $mr8\n\t" |
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"andi %0, $p0, 0x01\n\t" |
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: "=r" (ret) |
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: |
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: "memory" |
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); |
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return ret; |
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} |
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void dcache_enable(void) |
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{ |
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__asm__ __volatile__ ( |
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"mfsr $p0, $mr8\n\t" |
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"ori $p0, $p0, 0x02\n\t" |
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"mtsr $p0, $mr8\n\t" |
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"isb\n\t" |
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); |
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} |
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void dcache_disable(void) |
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{ |
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__asm__ __volatile__ ( |
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"mfsr $p0, $mr8\n\t" |
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"li $p1, ~0x02\n\t" |
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"and $p0, $p0, $p1\n\t" |
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"mtsr $p0, $mr8\n\t" |
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"isb\n\t" |
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); |
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} |
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int dcache_status(void) |
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{ |
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int ret; |
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__asm__ __volatile__ ( |
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"mfsr $p0, $mr8\n\t" |
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"andi %0, $p0, 0x02\n\t" |
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: "=r" (ret) |
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: |
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: "memory" |
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); |
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return ret; |
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} |
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@ -0,0 +1,297 @@ |
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/* |
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* Copyright (C) 2011 Andes Technology Corporation |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
|
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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.text |
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#include <common.h> |
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#include <config.h> |
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|
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#include <asm/macro.h> |
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#include <generated/asm-offsets.h> |
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|
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/* |
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* parameters for Synopsys DWC DDR2/DDR1 Memory Controller |
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*/ |
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#define DDR2C_BASE_A (CONFIG_DWCDDR21MCTL_BASE) |
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#define DDR2C_CCR_A (DDR2C_BASE_A + DWCDDR21MCTL_CCR) |
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#define DDR2C_DCR_A (DDR2C_BASE_A + DWCDDR21MCTL_DCR) |
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#define DDR2C_IOCR_A (DDR2C_BASE_A + DWCDDR21MCTL_IOCR) |
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#define DDR2C_CSR_A (DDR2C_BASE_A + DWCDDR21MCTL_CSR) |
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#define DDR2C_DRR_A (DDR2C_BASE_A + DWCDDR21MCTL_DRR) |
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#define DDR2C_DLLCR0_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0) |
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#define DDR2C_DLLCR1_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1) |
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#define DDR2C_DLLCR2_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2) |
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#define DDR2C_DLLCR3_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3) |
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#define DDR2C_DLLCR4_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4) |
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#define DDR2C_DLLCR5_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5) |
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#define DDR2C_DLLCR6_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6) |
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#define DDR2C_DLLCR7_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7) |
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#define DDR2C_DLLCR8_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8) |
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#define DDR2C_DLLCR9_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9) |
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#define DDR2C_RSLR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RSLR0) |
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#define DDR2C_RDGR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RDGR0) |
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#define DDR2C_DTAR_A (DDR2C_BASE_A + DWCDDR21MCTL_DTAR) |
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#define DDR2C_MR_A (DDR2C_BASE_A + DWCDDR21MCTL_MR) |
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|
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#define DDR2C_CCR_D CONFIG_SYS_DWCDDR21MCTL_CCR |
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#define DDR2C_CCR_D2 CONFIG_SYS_DWCDDR21MCTL_CCR2 |
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#define DDR2C_DCR_D CONFIG_SYS_DWCDDR21MCTL_DCR |
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#define DDR2C_IOCR_D CONFIG_SYS_DWCDDR21MCTL_IOCR |
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#define DDR2C_CSR_D CONFIG_SYS_DWCDDR21MCTL_CSR |
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#define DDR2C_DRR_D CONFIG_SYS_DWCDDR21MCTL_DRR |
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#define DDR2C_RSLR0_D CONFIG_SYS_DWCDDR21MCTL_RSLR0 |
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#define DDR2C_RDGR0_D CONFIG_SYS_DWCDDR21MCTL_RDGR0 |
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#define DDR2C_DTAR_D CONFIG_SYS_DWCDDR21MCTL_DTAR |
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#define DDR2C_MR_D CONFIG_SYS_DWCDDR21MCTL_MR |
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|
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#define DDR2C_DLLCR0_D CONFIG_SYS_DWCDDR21MCTL_DLLCR0 /* 0-9 are same */ |
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|
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/* |
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* parameters for the ahbc controller |
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*/ |
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#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR) |
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#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6) |
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|
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#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 |
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|
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/* |
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* parameters for the ANDES PCU controller |
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*/ |
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#define PCU_PCS4_A (CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4) |
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#define PCU_PCS4_D CONFIG_SYS_ANDES_CPU_PCS4 |
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|
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/* |
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* numeric 7 segment display |
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*/ |
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.macro led, num |
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write32 CONFIG_DEBUG_LED, \num |
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.endm |
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|
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/* |
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* Waiting for SDRAM to set up |
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*/ |
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/* |
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.macro wait_sdram
|
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li $r0, DDR2C_CSR_A |
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1: |
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lwi $r1, [$r0+FTSDMC021_CR2] |
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bnez $r1, 1b |
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.endm |
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*/ |
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|
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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.globl lowlevel_init
|
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lowlevel_init: |
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move $r10, $lp |
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|
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/* U200 */ |
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! led 0x00 |
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! jal scale_to_500mhz |
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|
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led 0x10 |
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jal mem_init |
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|
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led 0x20 |
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jal remap |
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|
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led 0x30 |
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ret $r10 |
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|
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scale_to_500mhz: |
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move $r11, $lp |
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|
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/* |
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* scale to 500Mhz |
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*/ |
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led 0x01 |
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write32 PCU_PCS4_A, 0x1102000f ! save data to PCS4 |
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|
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move $lp, $r11 |
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ret |
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|
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mem_init: |
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move $r11, $lp |
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|
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/* |
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* config AHB Controller |
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*/ |
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led 0x12 |
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write32 AHBC_BSR6_A, AHBC_BSR6_D |
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|
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/* |
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* config Synopsys DWC DDR2/DDR1 Memory Controller |
||||
*/ |
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ddr2c_init: |
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set_dcr: |
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led 0x14 |
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write32 DDR2C_DCR_A, DDR2C_DCR_D ! 0x000020d4 |
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|
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auto_sizing: |
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/* |
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* ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13 |
||||
*/ |
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set_iocr: |
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led 0x19 |
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write32 DDR2C_IOCR_A, DDR2C_IOCR_D |
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set_drr: |
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led 0x16 |
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write32 DDR2C_DRR_A, DDR2C_DRR_D ! 0x00034812 |
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set_dllcr: |
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led 0x18 |
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write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D |
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write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D |
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write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D |
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write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D |
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write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D |
||||
write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D |
||||
write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D |
||||
write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D |
||||
write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D |
||||
write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D |
||||
set_rslr0: |
||||
write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D ! 0x00000040 |
||||
set_rdgr0: |
||||
write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D ! 0x000055cf |
||||
set_dtar: |
||||
led 0x15 |
||||
write32 DDR2C_DTAR_A, DDR2C_DTAR_D ! 0x00100000 |
||||
set_mode: |
||||
led 0x17 |
||||
write32 DDR2C_MR_A, DDR2C_MR_D ! 0x00000852 |
||||
set_ccr: |
||||
write32 DDR2C_CCR_A, DDR2C_CCR_D |
||||
|
||||
#ifdef TRIGGER_INIT: |
||||
trigger_init: |
||||
write32 DDR2C_CCR_A, DDR2C_CCR_D ! 0x80020000 |
||||
|
||||
/* Wait for ddr init state to be set */ |
||||
msync ALL |
||||
isb |
||||
|
||||
/* Wait until the config initialization is finish */ |
||||
1: |
||||
la $r4, DDR2C_CSR_A |
||||
lwi $r5, [$r4] |
||||
srli $r5, $r5, 23 |
||||
bnez $r5, 1b |
||||
#endif |
||||
|
||||
data_training: |
||||
! write32 DDR2C_CCR_A, DDR2C_CCR_D2 ! 0x40020004 |
||||
|
||||
/* Wait for ddr init state to be set */ |
||||
msync ALL |
||||
isb |
||||
|
||||
/* wait until the ddr data trainning is complete */ |
||||
1: |
||||
la $r4, DDR2C_CSR_A |
||||
lwi $r5, [$r4] |
||||
srli $r6, $r5, 23 |
||||
bnez $r6, 1b |
||||
|
||||
lwi $r1, [$r4] |
||||
srli $r6, $r5, 20 |
||||
li $r5, 0x00ffffff |
||||
swi $r1, [$r4] |
||||
bnez $r6, ddr2c_init |
||||
|
||||
led 0x1a |
||||
move $lp, $r11 |
||||
ret |
||||
|
||||
remap: |
||||
move $r11, $lp |
||||
#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */ |
||||
bal 2f |
||||
relo_base: |
||||
move $r0, $lp |
||||
#else |
||||
relo_base: |
||||
mfusr $r0, $pc |
||||
#endif /* __NDS32_N1213_43U1H__ */ |
||||
|
||||
/* |
||||
* Remapping |
||||
*/ |
||||
#ifdef CONFIG_MEM_REMAP |
||||
/* |
||||
* Copy ROM code to SDRAM base for memory remap layout. |
||||
* This is not the real relocation, the real relocation is the function |
||||
* relocate_code() is start.S which supports the systems is memory |
||||
* remapped or not. |
||||
*/ |
||||
/* |
||||
* Doing memory remap is essential for preparing some non-OS or RTOS |
||||
* applications. |
||||
* |
||||
* This is also a must on ADP-AG101 board. |
||||
* The reason is because the ROM/FLASH circuit on PCB board. |
||||
* AG101-A0 board has 2 jumpers MA17 and SW5 to configure which |
||||
* ROM/FLASH is used to boot. |
||||
* |
||||
* When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0, |
||||
* and the FLASH is connected to BANK1. |
||||
* When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0), |
||||
* and the FLASH is connected to BANK0. |
||||
* It will occur problem when doing flash probing if the flash is at |
||||
* BANK0 (0x00000000) while memory remapping was skipped. |
||||
* |
||||
* Other board like ADP-AG101P may not enable this since there is only |
||||
* a FLASH connected to bank0. |
||||
*/ |
||||
led 0x21 |
||||
li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */ |
||||
li $r5, 0x0 |
||||
la $r1, relo_base /* get $pc or $lp */ |
||||
sub $r2, $r0, $r1 |
||||
sethi $r6, hi20(_end) |
||||
ori $r6, $r6, lo12(_end) |
||||
add $r6, $r6, $r2 |
||||
1: |
||||
lwi.p $r7, [$r5], #4 |
||||
swi.p $r7, [$r4], #4 |
||||
blt $r5, $r6, 1b |
||||
|
||||
/* set remap bit */ |
||||
/* |
||||
* MEM remap bit is operational |
||||
* - use it to map writeable memory at 0x00000000, in place of flash |
||||
* - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff |
||||
* - after remap: flash/rom 0x80000000, sdram: 0x00000000 |
||||
*/ |
||||
led 0x2c |
||||
setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1 |
||||
|
||||
#endif /* #ifdef CONFIG_MEM_REMAP */ |
||||
move $lp, $r11 |
||||
2: |
||||
ret |
||||
|
||||
.globl show_led
|
||||
show_led: |
||||
li $r8, (CONFIG_DEBUG_LED) |
||||
swi $r7, [$r8] |
||||
ret |
||||
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ |
||||
@ -0,0 +1,205 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Faraday Technology |
||||
* Po-Yu Chuang <ratbert@faraday-tech.com> |
||||
* |
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
||||
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <faraday/fttmr010.h> |
||||
|
||||
static ulong timestamp; |
||||
static ulong lastdec; |
||||
|
||||
int timer_init(void) |
||||
{ |
||||
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; |
||||
unsigned int cr; |
||||
|
||||
debug("%s()\n", __func__); |
||||
|
||||
/* disable timers */ |
||||
writel(0, &tmr->cr); |
||||
|
||||
#ifdef CONFIG_FTTMR010_EXT_CLK |
||||
/* use 32768Hz oscillator for RTC, WDT, TIMER */ |
||||
ftpmu010_32768osc_enable(); |
||||
#endif |
||||
|
||||
/* setup timer */ |
||||
writel(TIMER_LOAD_VAL, &tmr->timer3_load); |
||||
writel(TIMER_LOAD_VAL, &tmr->timer3_counter); |
||||
writel(0, &tmr->timer3_match1); |
||||
writel(0, &tmr->timer3_match2); |
||||
|
||||
/* we don't want timer to issue interrupts */ |
||||
writel(FTTMR010_TM3_MATCH1 | |
||||
FTTMR010_TM3_MATCH2 | |
||||
FTTMR010_TM3_OVERFLOW, |
||||
&tmr->interrupt_mask); |
||||
|
||||
cr = readl(&tmr->cr); |
||||
#ifdef CONFIG_FTTMR010_EXT_CLK |
||||
cr |= FTTMR010_TM3_CLOCK; /* use external clock */ |
||||
#endif |
||||
cr |= FTTMR010_TM3_ENABLE; |
||||
writel(cr, &tmr->cr); |
||||
|
||||
/* init the timestamp and lastdec value */ |
||||
reset_timer_masked(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* timer without interrupts |
||||
*/ |
||||
|
||||
/*
|
||||
* reset time |
||||
*/ |
||||
void reset_timer_masked(void) |
||||
{ |
||||
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; |
||||
|
||||
/* capure current decrementer value time */ |
||||
#ifdef CONFIG_FTTMR010_EXT_CLK |
||||
lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); |
||||
#else |
||||
lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2); |
||||
#endif |
||||
timestamp = 0; /* start "advancing" time stamp from 0 */ |
||||
|
||||
debug("%s(): lastdec = %lx\n", __func__, lastdec); |
||||
} |
||||
|
||||
void reset_timer(void) |
||||
{ |
||||
debug("%s()\n", __func__); |
||||
reset_timer_masked(); |
||||
} |
||||
|
||||
/*
|
||||
* return timer ticks |
||||
*/ |
||||
ulong get_timer_masked(void) |
||||
{ |
||||
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; |
||||
|
||||
/* current tick value */ |
||||
#ifdef CONFIG_FTTMR010_EXT_CLK |
||||
ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); |
||||
#else |
||||
ulong now = readl(&tmr->timer3_counter) / \
|
||||
(CONFIG_SYS_CLK_FREQ / 2 / 1024); |
||||
#endif |
||||
|
||||
debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); |
||||
|
||||
if (lastdec >= now) { |
||||
/*
|
||||
* normal mode (non roll) |
||||
* move stamp fordward with absoulte diff ticks |
||||
*/ |
||||
timestamp += lastdec - now; |
||||
} else { |
||||
/*
|
||||
* we have overflow of the count down timer |
||||
* |
||||
* nts = ts + ld + (TLV - now) |
||||
* ts=old stamp, ld=time that passed before passing through -1 |
||||
* (TLV-now) amount of time after passing though -1 |
||||
* nts = new "advancing time stamp"...it could also roll and |
||||
* cause problems. |
||||
*/ |
||||
timestamp += lastdec + TIMER_LOAD_VAL - now; |
||||
} |
||||
|
||||
lastdec = now; |
||||
|
||||
debug("%s() returns %lx\n", __func__, timestamp); |
||||
|
||||
return timestamp; |
||||
} |
||||
|
||||
/*
|
||||
* return difference between timer ticks and base |
||||
*/ |
||||
ulong get_timer(ulong base) |
||||
{ |
||||
debug("%s(%lx)\n", __func__, base); |
||||
return get_timer_masked() - base; |
||||
} |
||||
|
||||
void set_timer(ulong t) |
||||
{ |
||||
debug("%s(%lx)\n", __func__, t); |
||||
timestamp = t; |
||||
} |
||||
|
||||
/* delay x useconds AND preserve advance timestamp value */ |
||||
void __udelay(unsigned long usec) |
||||
{ |
||||
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; |
||||
|
||||
#ifdef CONFIG_FTTMR010_EXT_CLK |
||||
long tmo = usec * (TIMER_CLOCK / 1000) / 1000; |
||||
#else |
||||
long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000; |
||||
#endif |
||||
unsigned long now, last = readl(&tmr->timer3_counter); |
||||
|
||||
debug("%s(%lu)\n", __func__, usec); |
||||
while (tmo > 0) { |
||||
now = readl(&tmr->timer3_counter); |
||||
if (now > last) /* count down timer overflow */ |
||||
tmo -= TIMER_LOAD_VAL + last - now; |
||||
else |
||||
tmo -= last - now; |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long). |
||||
* On ARM it just returns the timer value. |
||||
*/ |
||||
unsigned long long get_ticks(void) |
||||
{ |
||||
debug("%s()\n", __func__); |
||||
return get_timer(0); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency). |
||||
* On ARM it returns the number of timer ticks per second. |
||||
*/ |
||||
ulong get_tbclk(void) |
||||
{ |
||||
debug("%s()\n", __func__); |
||||
#ifdef CONFIG_FTTMR010_EXT_CLK |
||||
return CONFIG_SYS_HZ; |
||||
#else |
||||
return CONFIG_SYS_CLK_FREQ; |
||||
#endif |
||||
} |
||||
@ -0,0 +1,49 @@ |
||||
/* |
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <asm/arch-ag102/ag102.h> |
||||
#include <linux/linkage.h> |
||||
|
||||
.text |
||||
|
||||
#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG |
||||
ENTRY(turnoff_watchdog) |
||||
|
||||
#define WD_CR 0xC |
||||
#define WD_ENABLE 0x1 |
||||
|
||||
! Turn off the watchdog, according to Faraday FTWDT010 spec |
||||
li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR |
||||
lwi $p1, [$p0] ! Get the config of WD |
||||
andi $p1, $p1, 0x1f ! Wipe out useless bits |
||||
li $r0, ~WD_ENABLE |
||||
and $p1, $p1, $r0 ! Set WD disable |
||||
sw $p1, [$p0] ! Write back to WD CR |
||||
|
||||
! Disable Interrupts by clear GIE in $PSW reg |
||||
setgie.d |
||||
|
||||
ret |
||||
|
||||
ENDPROC(turnoff_watchdog) |
||||
#endif |
||||
@ -0,0 +1,97 @@ |
||||
/*
|
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#ifndef __AG102_H |
||||
#define __AG102_H |
||||
|
||||
/*
|
||||
* Hardware register bases |
||||
*/ |
||||
|
||||
/* PCI Controller */ |
||||
#define CONFIG_FTPCI100_BASE 0x90000000 |
||||
/* LPC Controller */ |
||||
#define CONFIG_LPC_IO_BASE 0x90100000 |
||||
/* LPC Controller */ |
||||
#define CONFIG_LPC_BASE 0x90200000 |
||||
|
||||
/* NDS32 Data Local Memory 01 */ |
||||
#define CONFIG_NDS_DLM1_BASE 0x90300000 |
||||
/* NDS32 Data Local Memory 02 */ |
||||
#define CONFIG_NDS_DLM2_BASE 0x90400000 |
||||
|
||||
/* Synopsys DWC DDR2/1 Controller */ |
||||
#define CONFIG_DWCDDR21MCTL_BASE 0x90500000 |
||||
/* DMA Controller */ |
||||
#define CONFIG_FTDMAC020_BASE 0x90600000 |
||||
/* FTIDE020_S IDE (ATA) Controller */ |
||||
#define CONFIG_FTIDE020S_BASE 0x90700000 |
||||
/* USB OTG Controller */ |
||||
#define CONFIG_FZOTG266HD0A_BASE 0x90800000 |
||||
/* Andes L2 Cache Controller */ |
||||
#define CONFIG_NCEL2C100_BASE 0x90900000 |
||||
/* XGI XG22 GPU */ |
||||
#define CONFIG_XGI_XG22_BASE 0x90A00000 |
||||
/* GMAC Ethernet Controller */ |
||||
#define CONFIG_FTGMAC100_BASE 0x90B00000 |
||||
/* AHB Controller */ |
||||
#define CONFIG_FTAHBC020S_BASE 0x90C00000 |
||||
/* AHB-to-APB Bridge Controller */ |
||||
#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000 |
||||
/* External AHB2AHB Controller */ |
||||
#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000 |
||||
/* Andes Multi-core Interrupt Controller */ |
||||
#define CONFIG_NCEMIC100_BASE 0x90F00000 |
||||
|
||||
/*
|
||||
* APB Device definitions |
||||
*/ |
||||
/* Compat Flash Controller */ |
||||
#define CONFIG_FTCFC010_BASE 0x94000000 |
||||
/* APB - SSP (SPI) (without AC97) Controller */ |
||||
#define CONFIG_FTSSP010_01_BASE 0x94100000 |
||||
/* UART1 - APB STUART Controller (UART0 in Linux) */ |
||||
#define CONFIG_FTUART010_01_BASE 0x94200000 |
||||
/* FTSDC010 SD Controller */ |
||||
#define CONFIG_FTSDC010_BASE 0x94400000 |
||||
/* APB - SSP with HDA/AC97 Controller */ |
||||
#define CONFIG_FTSSP010_02_BASE 0x94500000 |
||||
/* UART2 - APB STUART Controller (UART1 in Linux) */ |
||||
#define CONFIG_FTUART010_02_BASE 0x94600000 |
||||
/* PCU Controller */ |
||||
#define CONFIG_ANDES_PCU_BASE 0x94800000 |
||||
/* FTTMR010 Timer */ |
||||
#define CONFIG_FTTMR010_BASE 0x94900000 |
||||
/* Watch Dog Controller */ |
||||
#define CONFIG_FTWDT010_BASE 0x94A00000 |
||||
/* FTRTC010 Real Time Clock */ |
||||
#define CONFIG_FTRTC010_BASE 0x98B00000 |
||||
/* GPIO Controller */ |
||||
#define CONFIG_FTGPIO010_BASE 0x94C00000 |
||||
/* I2C Controller */ |
||||
#define CONFIG_FTIIC010_BASE 0x94E00000 |
||||
/* PWM - Pulse Width Modulator Controller */ |
||||
#define CONFIG_FTPWM010_BASE 0x94F00000 |
||||
|
||||
/* Debug LED */ |
||||
#define CONFIG_DEBUG_LED 0x902FFFFC |
||||
/* Power Management Unit */ |
||||
#define CONFIG_FTPMU010_BASE 0x98100000 |
||||
|
||||
#endif /* __AG102_H */ |
||||
@ -0,0 +1,43 @@ |
||||
#
|
||||
# Copyright (C) 2011 Andes Technology Corporation
|
||||
# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := adp-ag102.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,107 @@ |
||||
/*
|
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> |
||||
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <netdev.h> |
||||
#include <asm/io.h> |
||||
|
||||
#include <faraday/ftsdc010.h> |
||||
#ifdef CONFIG_FTSMC020 |
||||
#include <faraday/ftsmc020.h> |
||||
#endif |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initializations |
||||
*/ |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/*
|
||||
* refer to BOOT_PARAMETER_PA_BASE within |
||||
* "linux/arch/nds32/include/asm/misc_spec.h" |
||||
*/ |
||||
gd->bd->bi_arch_number = MACH_TYPE_ADPAG102; |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; |
||||
|
||||
#if !defined(CONFIG_SYS_NO_FLASH) |
||||
ftsmc020_init(); /* initialize Flash */ |
||||
#endif /* CONFIG_SYS_NO_FLASH */ |
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
unsigned long sdram_base = PHYS_SDRAM_0; |
||||
unsigned long expected_size = PHYS_SDRAM_0_SIZE; |
||||
unsigned long actual_size; |
||||
|
||||
actual_size = get_ram_size((void *)sdram_base, expected_size); |
||||
|
||||
gd->ram_size = actual_size; |
||||
|
||||
if (expected_size != actual_size) { |
||||
printf("Warning: Only %lu of %lu MiB SDRAM is working\n", |
||||
actual_size >> 20, expected_size >> 20); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bd) |
||||
{ |
||||
return ftgmac100_initialize(bd); |
||||
} |
||||
|
||||
#if !defined(CONFIG_SYS_NO_FLASH) |
||||
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) |
||||
{ |
||||
if (banknum == 0) { /* non-CFI boot flash */ |
||||
info->portwidth = FLASH_CFI_8BIT; |
||||
info->chipwidth = FLASH_CFI_BY8; |
||||
info->interface = FLASH_CFI_X8; |
||||
return 1; |
||||
} else { |
||||
return 0; |
||||
} |
||||
} |
||||
#endif /* CONFIG_SYS_NO_FLASH */ |
||||
|
||||
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) |
||||
void pci_init_board(void) |
||||
{ |
||||
/* should be pci_ftpci100_init() */ |
||||
extern void pci_ftpci_init(); |
||||
|
||||
pci_ftpci_init(); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_GENERIC_MMC |
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
ftsdc010_mmc_init(0); |
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,36 @@ |
||||
Andes Technology SoC AG102 |
||||
========================== |
||||
|
||||
AG102 is the second SoC produced by Andes Technology using N1213 CPU core |
||||
with FPU and DDR contoller support. |
||||
AG102 has integrated both AHB and APB bus and many periphals for application |
||||
and product development. |
||||
|
||||
ADP-AG102 |
||||
========= |
||||
|
||||
ADP-AG102 is the SoC with AG102 hardcore CPU. |
||||
|
||||
Configurations |
||||
============== |
||||
|
||||
CONFIG_MEM_REMAP: |
||||
Doing memory remap is essential for preparing some non-OS or RTOS |
||||
applications. |
||||
|
||||
CONFIG_SKIP_LOWLEVEL_INIT: |
||||
If you want to boot this system from SPI ROM and bypass e-bios (the |
||||
other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT |
||||
in "include/configs/adp-ag102.h". |
||||
|
||||
Build and boot steps |
||||
==================== |
||||
|
||||
build: |
||||
1. Prepare the toolchains and make sure the $PATH to toolchains is correct. |
||||
2. Use `make adp-ag102` in u-boot root to build the image. |
||||
|
||||
Burn u-boot to SPI ROM: |
||||
==================== |
||||
|
||||
This section will be added later. |
||||
@ -0,0 +1,375 @@ |
||||
/*
|
||||
* Copyright (C) 2011 Andes Technology Corporation |
||||
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/arch/ag102.h> |
||||
|
||||
/*
|
||||
* CPU and Board Configuration Options |
||||
*/ |
||||
#define CONFIG_ADP_AG102 |
||||
|
||||
#define CONFIG_USE_INTERRUPT |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_MEM_REMAP |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_SYS_TEXT_BASE 0x04200000 |
||||
#else |
||||
#define CONFIG_SYS_TEXT_BASE 0x00000000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Timer |
||||
*/ |
||||
|
||||
/*
|
||||
* According to the discussion in u-boot mailing list before, |
||||
* CONFIG_SYS_HZ at 1000 is mandatory. |
||||
*/ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
#define CONFIG_SYS_CLK_FREQ (66000000 * 2) |
||||
#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ |
||||
|
||||
/*
|
||||
* Use Externel CLOCK or PCLK |
||||
*/ |
||||
#undef CONFIG_FTRTC010_EXTCLK |
||||
|
||||
#ifndef CONFIG_FTRTC010_EXTCLK |
||||
#define CONFIG_FTRTC010_PCLK |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FTRTC010_EXTCLK |
||||
#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ |
||||
#else |
||||
#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ |
||||
#endif |
||||
|
||||
#define TIMER_LOAD_VAL 0xffffffff |
||||
|
||||
/*
|
||||
* Real Time Clock |
||||
*/ |
||||
#define CONFIG_RTC_FTRTC010 |
||||
|
||||
/*
|
||||
* Real Time Clock Divider |
||||
* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) |
||||
*/ |
||||
#define OSC_5MHZ (5*1000000) |
||||
#define OSC_CLK (2*OSC_5MHZ) |
||||
#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) |
||||
|
||||
/*
|
||||
* Serial console configuration |
||||
*/ |
||||
|
||||
/* FTUART is a high speed NS 16C550A compatible UART */ |
||||
#define CONFIG_BAUDRATE 38400 |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE |
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 |
||||
#define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */ |
||||
|
||||
/* valid baudrates */ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Ethernet |
||||
*/ |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */ |
||||
#define CONFIG_SYS_DISCOVER_PHY |
||||
#define CONFIG_FTGMAC100 |
||||
#define CONFIG_FTGMAC100_EGIGA |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
/*
|
||||
* SD (MMC) controller |
||||
*/ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_FTSDC010 |
||||
#define CONFIG_FTSDC010_NUMBER 1 |
||||
#define CONFIG_FTSDC010_SDIO |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_EXT2 |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_ELF |
||||
|
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
/*
|
||||
* PCI |
||||
*/ |
||||
#define CONFIG_PCI |
||||
#define CONFIG_FTPCI100 |
||||
#define CONFIG_FTPCI100_MEM_BASE 0xa0000000 |
||||
#define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */ |
||||
#define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */ |
||||
#define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50 |
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0xa0000000 |
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
||||
#define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */ |
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x90000000 |
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
||||
#define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */ |
||||
|
||||
/*
|
||||
* USB |
||||
*/ |
||||
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) |
||||
#if defined(CONFIG_FTPCI100) |
||||
#define __io /* enable outl & inl */ |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5 |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_PCI_EHCI_DEVICE 0 |
||||
#define CONFIG_USB_EHCI_PCI |
||||
#define CONFIG_PREBOOT "usb start;" |
||||
#endif /* #if defiend(CONFIG_FTPCI100) */ |
||||
#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */ |
||||
|
||||
/*
|
||||
* IDE/ATA stuff |
||||
*/ |
||||
#define __io |
||||
#define CONFIG_IDE_AHB |
||||
#define CONFIG_IDE_FTIDE020 |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
||||
#undef CONFIG_IDE_LED /* no led for ide supported */ |
||||
#define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
||||
#define CONFIG_IDE_PREINIT 1 /* preinit for ide */ |
||||
|
||||
/* max: 2 IDE busses */ |
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */ |
||||
/* max: 2 drives per IDE bus */ |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */ |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE |
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */ |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_SUPPORT_VFAT |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE \ |
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
|
||||
/* max number of command args */ |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
|
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
||||
|
||||
/*
|
||||
* size in bytes reserved for initial data |
||||
*/ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 |
||||
|
||||
/*
|
||||
* AHB Controller configuration |
||||
*/ |
||||
#define CONFIG_FTAHBC020S |
||||
|
||||
#ifdef CONFIG_FTAHBC020S |
||||
#include <faraday/ftahbc020s.h> |
||||
|
||||
/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ |
||||
#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 |
||||
|
||||
/*
|
||||
* CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, |
||||
* hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote |
||||
* in C language. |
||||
*/ |
||||
#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ |
||||
(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
|
||||
FTAHBC020S_SLAVE_BSR_SIZE(0xb)) |
||||
#endif |
||||
|
||||
/*
|
||||
* Watchdog |
||||
*/ |
||||
#define CONFIG_FTWDT010_WATCHDOG |
||||
|
||||
/*
|
||||
* PCU Power Control Unit configuration |
||||
*/ |
||||
#define CONFIG_ANDES_PCU |
||||
|
||||
#ifdef CONFIG_ANDES_PCU |
||||
#include <andestech/andes_pcu.h> |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* DDR DRAM controller configuration |
||||
*/ |
||||
#define CONFIG_DWCDDR21MCTL |
||||
|
||||
#ifdef CONFIG_DWCDDR21MCTL |
||||
#include <synopsys/dwcddr21mctl.h> |
||||
/* DCR:
|
||||
* 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend |
||||
* 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk |
||||
* 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks) |
||||
* 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank) |
||||
* 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks) |
||||
*/ |
||||
#define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004 |
||||
#define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) | \ |
||||
DWCDDR21MCTL_CCR_DFTLM(0x4) | \
|
||||
DWCDDR21MCTL_CCR_HOSTEN(0x1)) |
||||
|
||||
/* 0x04: 0x000020d4 */ |
||||
#define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca |
||||
|
||||
/* 0x08: 0x0000000f */ |
||||
#define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f |
||||
|
||||
/* 0x10: 0x00034812 */ |
||||
#define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) | \ |
||||
DWCDDR21MCTL_DRR_TRFPRD(0x0348)) |
||||
/* 0x24 */ |
||||
#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0) |
||||
|
||||
/* 0x4c: 0x00000040 */ |
||||
#define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040 |
||||
|
||||
/* 0x5c: 0x000055CF */ |
||||
#define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf |
||||
|
||||
/* 0xa4: 0x00100000 */ |
||||
#define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) | \ |
||||
DWCDDR21MCTL_DTAR_DTROW(0x0100) | \
|
||||
DWCDDR21MCTL_DTAR_DTCOL(0x0)) |
||||
/* 0x1f0: 0x00000852 */ |
||||
#define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) | \ |
||||
DWCDDR21MCTL_MR_CL(0x5) | \
|
||||
DWCDDR21MCTL_MR_BL(0x2)) |
||||
#endif |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) |
||||
#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ |
||||
#if defined(CONFIG_MEM_REMAP) |
||||
#define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/ |
||||
#endif |
||||
#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ |
||||
#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ |
||||
#endif |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */ |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 |
||||
|
||||
#ifdef CONFIG_MEM_REMAP |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#else |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#endif /* CONFIG_MEM_REMAP */ |
||||
|
||||
/*
|
||||
* Load address and memory test area should agree with |
||||
* board/faraday/a320/config.mk |
||||
* Be careful not to overwrite U-boot itself. |
||||
*/ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x0CF00000 |
||||
|
||||
/* memtest works on 63 MB in DRAM */ |
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 |
||||
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) |
||||
|
||||
/*
|
||||
* Static memory controller configuration |
||||
*/ |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/*
|
||||
* Env Storage Settings |
||||
*/ |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#define CONFIG_ENV_SIZE 4096 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue