diff --git a/MAINTAINERS b/MAINTAINERS index e2a4ba9..e2c48a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -429,7 +429,7 @@ Heiko Schocher kmeter1 MPC8360 kmsupx5 MPC8321 mgcoge MPC8247 - mgcoge2ne MPC8247 + mgcoge3ne MPC8247 mgcoge2un ARM926EJS (Kirkwood SoC) mucmc52 MPC5200 muas3001 MPC8270 diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index dc96489..25a3850 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -22,7 +22,7 @@ */ #include -#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE) +#if defined(CONFIG_KM82XX) #include #endif #include @@ -398,10 +398,10 @@ int ivm_read_eeprom(void) #define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ #define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) -#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE) +#if defined(CONFIG_KM_82XX) #define SDA_MASK 0x00010000 #define SCL_MASK 0x00020000 -static void set_pin(int state, unsigned long mask) +void set_pin(int state, unsigned long mask) { ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index 6ce992a..cee24d4 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -124,6 +124,7 @@ struct bfticu_iomap { int ethernet_present(void); int ivm_read_eeprom(void); +void set_pin(int state, unsigned long mask); int set_km_env(void); int fdt_set_node_and_value(void *blob, diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c index 01c0bfd..d453d25 100644 --- a/board/keymile/km82xx/km82xx.c +++ b/board/keymile/km82xx/km82xx.c @@ -288,7 +288,7 @@ int checkboard(void) #if defined(CONFIG_MGCOGE) puts("Board: Keymile mgcoge"); #else - puts("Board: Keymile mgcoge2ne"); + puts("Board: Keymile mgcoge3ne"); #endif if (ethernet_present()) puts(" with PIGGY."); @@ -314,6 +314,28 @@ int last_stage_init(void) return 0; } +#ifdef CONFIG_MGCOGE3NE +/* + * For mgcoge3ne boards, the mgcoge3un control is controlled from + * a GPIO line on the PPC CPU. If bobcatreset is set the line + * will toggle once what forces the mgocge3un part to restart + * immediately. + */ +void handle_mgcoge3un_reset(void) +{ + char *bobcatreset = getenv("bobcatreset"); + if (bobcatreset) { + if (strcmp(bobcatreset, "true") == 0) { + puts("Forcing bobcat reset\n"); + set_pin(0, 0x00000004); /* clear PD29 to reset arm */ + udelay(1000); + set_pin(1, 0x00000004); + } else + set_pin(1, 0x00000004); /* set PD29 to not reset arm */ + } +} +#endif + /* * Early board initalization. */ @@ -329,6 +351,9 @@ int board_early_init_r(void) out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA | H_OPORTS_FCC1_PW_DWN)); +#ifdef CONFIG_MGCOGE3NE + handle_mgcoge3un_reset(); +#endif return 0; } diff --git a/boards.cfg b/boards.cfg index e0791fe..f0d3440 100644 --- a/boards.cfg +++ b/boards.cfg @@ -440,7 +440,7 @@ PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260 mpc8260ads freesca PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz mgcoge powerpc mpc8260 km82xx keymile -mgcoge2ne powerpc mpc8260 km82xx keymile +mgcoge3ne powerpc mpc8260 km82xx keymile SCM powerpc mpc8260 - siemens TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h index 345212c..da551c9 100644 --- a/include/configs/km82xx-common.h +++ b/include/configs/km82xx-common.h @@ -243,13 +243,6 @@ ORxG_SCY_5_CLK |\ ORxG_TRLX) - -/* - * Bank 1 - 60x bus SDRAM - */ -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ - #define CONFIG_SYS_MPTPR 0x1800 /* @@ -268,25 +261,6 @@ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 /* - * SDRAM initialization values - */ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_8 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values */ #define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000 diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 3d2ee24..93a6f4a 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -32,6 +32,7 @@ #define CONFIG_MPC8247 #define CONFIG_MGCOGE #define CONFIG_HOSTNAME mgcoge +#define CONFIG_KM_82XX #define CONFIG_SYS_TEXT_BASE 0xFE000000 @@ -58,6 +59,32 @@ CONFIG_SYS_FLASH_BASE_2 } #define MTDIDS_DEFAULT "nor3=app" +/* + * Bank 1 - 60x bus SDRAM + */ +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ + +/* SDRAM initialization values +*/ + +#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ + ORxS_SDAM_MSK) |\ + ORxS_BPD_8 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_5_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + + /* include further common stuff for all keymile 82xx boards */ #include "km82xx-common.h" diff --git a/include/configs/mgcoge2ne.h b/include/configs/mgcoge3ne.h similarity index 62% rename from include/configs/mgcoge2ne.h rename to include/configs/mgcoge3ne.h index 287b717..f080619 100644 --- a/include/configs/mgcoge2ne.h +++ b/include/configs/mgcoge3ne.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2010 + * (C) Copyright 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this @@ -21,16 +21,18 @@ * MA 02111-1307 USA */ -#ifndef __MGCOGE2NE -#define __MGCOGE2NE +#ifndef __MGCOGE3NE +#define __MGCOGE3NE /* * High Level Configuration Options * (easy to change) */ + #define CONFIG_MPC8247 -#define CONFIG_MGCOGE -#define CONFIG_HOSTNAME mgcoge2ne +#define CONFIG_MGCOGE3NE +#define CONFIG_HOSTNAME mgcoge3ne +#define CONFIG_KM_82XX #define CONFIG_SYS_TEXT_BASE 0xFE000000 @@ -43,22 +45,47 @@ #define CONFIG_SYS_FLASH_SIZE 32 #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* * max num of sects on one * chip */ #define CONFIG_SYS_FLASH_BASE_1 0x50000000 -#define CONFIG_SYS_FLASH_SIZE_1 64 -#define CONFIG_SYS_FLASH_SIZE_2 0 +#define CONFIG_SYS_FLASH_SIZE_1 128 + +#define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ CONFIG_SYS_FLASH_BASE_1 } #define MTDIDS_DEFAULT "nor2=app" +/* + * Bank 1 - 60x bus SDRAM + * mgcoge3ne has 256M. + */ +#define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */ + +#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ + ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A4 |\ + ORxS_NUMR_13) + +#define CONFIG_SYS_PSDMR (PSDMR_PBI |\ + PSDMR_SDAM_A17_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A6 |\ + PSDMR_RFRC_5_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) + /* include further common stuff for all keymile 82xx boards */ #include "km82xx-common.h" -#endif /* __MGCOGE2NE */ +#endif /* __MGCOGE3NE */