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@ -7,6 +7,7 @@ |
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#include <common.h> |
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#include <dwmmc.h> |
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#include <malloc.h> |
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#include <asm/arcregs.h> |
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#include "axs10x.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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@ -61,16 +62,32 @@ void smp_kick_all_cpus(void) |
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{ |
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/* CPU start CREG */ |
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#define AXC003_CREG_CPU_START 0xF0001400 |
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/* Bits positions in CPU start CREG */ |
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#define BITS_START 0 |
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#define BITS_POLARITY 8 |
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#define BITS_START_MODE 4 |
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#define BITS_CORE_SEL 9 |
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#define BITS_MULTICORE 12 |
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#define CMD (1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \ |
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(1 << BITS_POLARITY) | (1 << BITS_START) |
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/*
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* In axs103 v1.1 START bits semantics has changed quite a bit. |
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* We used to have a generic START bit for all cores selected by CORE_SEL mask. |
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* But now we don't touch CORE_SEL at all because we have a dedicated START bit |
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* for each core: |
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* bit 0: Core 0 (master) |
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* bit 1: Core 1 (slave) |
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*/ |
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#define BITS_START_CORE1 1 |
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#define ARCVER_HS38_3_0 0x53 |
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int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff; |
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int cmd = readl((void __iomem *)AXC003_CREG_CPU_START); |
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writel(CMD, (void __iomem *)AXC003_CREG_CPU_START); |
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if (core_family < ARCVER_HS38_3_0) { |
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cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START); |
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cmd &= ~(1 << BITS_START_MODE); |
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} else { |
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cmd |= (1 << BITS_START_CORE1); |
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} |
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writel(cmd, (void __iomem *)AXC003_CREG_CPU_START); |
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} |
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#endif |
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