Add Intel Edison board which is using U-Boot. The patch is based on work done by the following people (in alphabetical order): Aiden Park <aiden.park@intel.com> Dukjoon Jeon <dukjoon.jeon@intel.com> eric.park <eric.park@intel.com> Fabien Chereau <fabien.chereau@intel.com> Felipe Balbi <felipe.balbi@linux.intel.com> Scott D Phillips <scott.d.phillips@intel.com> Sebastien Colleur <sebastienx.colleur@intel.com> Steve Sakoman <steve.sakoman@intel.com> Vincent Tinelli <vincent.tinelli@intel.com> In case we're building for Intel Edison, we must have 4096 bytes of zeroes in the beginning on u-boot.bin. This is done in board/intel/edison/config.mk. First run sets hardware_id environment variable which is read from System Controller Unit (SCU). Serial number (serial# environment variable) is generated based on eMMC CID. MAC address on USB network interface is unique to the board but kept the same all over the time. Set mac address from U-Boot using following scheme: OUI = 02:00:86 next 3 bytes of MAC address set from eMMC serial number This allows to have a unique mac address across reboot and flashing. Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> [bmeng: Add MAINTAINERS file for Intel Edison board] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>master
Andy Shevchenko
8 years ago
committed by
Bin Meng
parent
e71de54a49
commit
495f3774be
@ -0,0 +1,89 @@ |
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/* |
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* Copyright (c) 2017 Intel Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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#include <dt-bindings/gpio/x86-gpio.h> |
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#include <dt-bindings/interrupt-router/intel-irq.h> |
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/include/ "skeleton.dtsi" |
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/include/ "rtc.dtsi" |
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/include/ "tsc_timer.dtsi" |
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/ { |
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model = "Intel Edison"; |
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compatible = "intel,edison"; |
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aliases { |
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serial0 = &serial0; |
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}; |
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chosen { |
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stdout-path = &serial0; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "cpu-x86"; |
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reg = <0>; |
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intel,apic-id = <0>; |
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}; |
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "cpu-x86"; |
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reg = <1>; |
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intel,apic-id = <2>; |
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}; |
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}; |
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pci { |
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compatible = "pci-x86"; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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u-boot,dm-pre-reloc; |
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 |
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 |
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0x01000000 0x0 0x2000 0x2000 0 0xe000>; |
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}; |
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serial0: serial@ff010180 { |
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compatible = "intel,mid-uart"; |
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reg = <0xff010180 0x100>; |
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reg-shift = <0>; |
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clock-frequency = <29491200>; |
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current-speed = <115200>; |
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}; |
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emmc: mmc@ff3fc000 { |
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compatible = "intel,sdhci-tangier"; |
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reg = <0xff3fc000 0x1000>; |
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}; |
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/* |
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* FIXME: For now U-Boot DM model doesn't allow to power up this controller. |
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* Enabling it will make U-Boot hang. |
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* |
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sdcard: mmc@ff3fa000 { |
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compatible = "intel,sdhci-tangier"; |
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reg = <0xff3fa000 0x1000>; |
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}; |
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*/ |
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pmu: power@ff00b000 { |
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compatible = "intel,pmu-mid"; |
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reg = <0xff00b000 0x1000>; |
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}; |
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scu: ipc@ff009000 { |
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compatible = "intel,scu-ipc"; |
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reg = <0xff009000 0x1000>; |
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}; |
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}; |
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@ -0,0 +1,26 @@ |
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if TARGET_EDISON |
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config SYS_BOARD |
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default "edison" |
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config SYS_VENDOR |
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default "intel" |
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config SYS_SOC |
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default "tangier" |
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config SYS_CONFIG_NAME |
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default "edison" |
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config SYS_TEXT_BASE |
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default 0x01101000 |
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config BOARD_SPECIFIC_OPTIONS # dummy |
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def_bool y |
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select X86_LOAD_FROM_32_BIT |
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select INTEL_MID |
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select INTEL_TANGIER |
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select BOARD_LATE_INIT |
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select MD5 |
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endif |
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@ -0,0 +1,6 @@ |
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Intel Edison Board |
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M: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
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S: Maintained |
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F: board/intel/edison |
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F: include/configs/edison.h |
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F: configs/edison_defconfig |
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@ -0,0 +1,7 @@ |
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#
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# Copyright (c) 2017 Intel Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += start.o edison.o
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@ -0,0 +1,18 @@ |
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#
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# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
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# Copyright (c) 2017 Intel Corporation
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#
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# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
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#
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# Add 4096 bytes of zeroes to u-boot.bin
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quiet_cmd_mkalign_eds = EDSALGN $@
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cmd_mkalign_eds = \
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dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \
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mv $@ $^
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ALL-y += u-boot-align.bin
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u-boot-align.bin: u-boot.bin |
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$(call if_changed,mkalign_eds)
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HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
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@ -0,0 +1,104 @@ |
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/*
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* Copyright (c) 2017 Intel Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dwc3-uboot.h> |
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#include <mmc.h> |
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#include <u-boot/md5.h> |
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#include <usb.h> |
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#include <watchdog.h> |
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#include <linux/usb/gadget.h> |
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#include <asm/cache.h> |
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#include <asm/scu.h> |
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#include <asm/u-boot-x86.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static struct dwc3_device dwc3_device_data = { |
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.maximum_speed = USB_SPEED_HIGH, |
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.base = CONFIG_SYS_USB_OTG_BASE, |
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.dr_mode = USB_DR_MODE_PERIPHERAL, |
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.index = 0, |
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}; |
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int usb_gadget_handle_interrupts(int controller_index) |
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{ |
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dwc3_uboot_handle_interrupt(controller_index); |
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WATCHDOG_RESET(); |
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return 0; |
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} |
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int board_usb_init(int index, enum usb_init_type init) |
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{ |
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if (index == 0 && init == USB_INIT_DEVICE) |
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return dwc3_uboot_init(&dwc3_device_data); |
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return -EINVAL; |
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} |
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int board_usb_cleanup(int index, enum usb_init_type init) |
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{ |
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if (index == 0 && init == USB_INIT_DEVICE) { |
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dwc3_uboot_exit(index); |
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return 0; |
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} |
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return -EINVAL; |
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} |
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static void assign_serial(void) |
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{ |
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struct mmc *mmc = find_mmc_device(0); |
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unsigned char ssn[16]; |
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char usb0addr[18]; |
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char serial[33]; |
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int i; |
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if (!mmc) |
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return; |
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md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn); |
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snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x", |
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ssn[13], ssn[14], ssn[15]); |
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setenv("usb0addr", usb0addr); |
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for (i = 0; i < 16; i++) |
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snprintf(&serial[2 * i], 3, "%02x", ssn[i]); |
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setenv("serial#", serial); |
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#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) |
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saveenv(); |
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#endif |
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} |
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static void assign_hardware_id(void) |
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{ |
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struct ipc_ifwi_version v; |
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char hardware_id[4]; |
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int ret; |
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ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4); |
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if (ret < 0) |
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printf("Can't retrieve hardware revision\n"); |
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snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id); |
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setenv("hardware_id", hardware_id); |
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#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) |
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saveenv(); |
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#endif |
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} |
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int board_late_init(void) |
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{ |
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if (!getenv("serial#")) |
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assign_serial(); |
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if (!getenv("hardware_id")) |
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assign_hardware_id(); |
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return 0; |
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} |
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@ -0,0 +1,13 @@ |
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/* |
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* Copyright (c) 2011 The Chromium OS Authors. |
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* (C) Copyright 2008 |
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* Graeme Russ, graeme.russ@gmail.com.
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/* board early intialization */ |
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.globl early_board_init
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early_board_init: |
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/* No 32-bit board specific initialisation */ |
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jmp early_board_init_ret |
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@ -0,0 +1,53 @@ |
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CONFIG_X86=y |
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CONFIG_VENDOR_INTEL=y |
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CONFIG_DEFAULT_DEVICE_TREE="edison" |
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CONFIG_TARGET_EDISON=y |
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CONFIG_SMP=y |
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# CONFIG_ARCH_EARLY_INIT_R is not set |
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# CONFIG_BOARD_EARLY_INIT_F is not set |
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CONFIG_HUSH_PARSER=y |
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CONFIG_CMD_CPU=y |
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# CONFIG_CMD_IMLS is not set |
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CONFIG_CMD_ASKENV=y |
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CONFIG_CMD_GREPENV=y |
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CONFIG_CMD_ENV_CALLBACK=y |
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CONFIG_CMD_ENV_FLAGS=y |
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CONFIG_CMD_MEMINFO=y |
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# CONFIG_CMD_FLASH is not set |
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CONFIG_CMD_GPT=y |
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CONFIG_CMD_MMC=y |
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CONFIG_CMD_PART=y |
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CONFIG_CMD_DFU=y |
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# CONFIG_CMD_NFS is not set |
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CONFIG_CMD_TIMER=y |
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CONFIG_CMD_HASH=y |
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CONFIG_CMD_EXT4=y |
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CONFIG_CMD_EXT4_WRITE=y |
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CONFIG_CMD_FAT=y |
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CONFIG_CMD_FS_GENERIC=y |
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CONFIG_OF_CONTROL=y |
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CONFIG_OF_EMBED=y |
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CONFIG_CPU=y |
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CONFIG_DFU_MMC=y |
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CONFIG_DFU_RAM=y |
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CONFIG_MMC=y |
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CONFIG_DM_MMC=y |
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CONFIG_MMC_SDHCI=y |
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CONFIG_MMC_SDHCI_SDMA=y |
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CONFIG_MMC_SDHCI_TANGIER=y |
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CONFIG_DM_PCI=y |
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CONFIG_DM_PCI_COMPAT=y |
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CONFIG_DM_RTC=y |
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CONFIG_INTEL_MID_SERIAL=y |
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CONFIG_TIMER=y |
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CONFIG_USB_DWC3=y |
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CONFIG_USB_DWC3_GADGET=y |
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CONFIG_USB_GADGET=y |
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CONFIG_USB_GADGET_DOWNLOAD=y |
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CONFIG_G_DNL_MANUFACTURER="Intel" |
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CONFIG_G_DNL_VENDOR_NUM=0x8087 |
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CONFIG_G_DNL_PRODUCT_NUM=0x0a99 |
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CONFIG_TANGIER_WATCHDOG=y |
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CONFIG_FAT_WRITE=y |
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CONFIG_USE_PRIVATE_LIBGCC=y |
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CONFIG_SHA1=y |
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@ -0,0 +1,61 @@ |
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/*
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* Copyright (c) 2017 Intel Corp. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <asm/ibmpc.h> |
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/* Boot */ |
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#define CONFIG_CMD_ZBOOT |
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#define CONFIG_BOOTCOMMAND "run bootcmd" |
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/* DISK Partition support */ |
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#define CONFIG_RANDOM_UUID |
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/* Miscellaneous configurable options */ |
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#define CONFIG_SYS_LONGHELP |
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#define CONFIG_SYS_CBSIZE 2048 |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
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#define CONFIG_SYS_MAXARGS 128 |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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#define CONFIG_AUTO_COMPLETE |
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/* Memory */ |
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#define CONFIG_SYS_LOAD_ADDR 0x100000 |
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#define CONFIG_PHYSMEM |
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#define CONFIG_NR_DRAM_BANKS 3 |
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#define CONFIG_SYS_STACK_SIZE (32 * 1024) |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) |
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#define CONFIG_SYS_MEMTEST_START 0x00100000 |
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#define CONFIG_SYS_MEMTEST_END 0x01000000 |
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/* Environment */ |
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#define CONFIG_ENV_IS_IN_MMC |
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#define CONFIG_SYS_MMC_ENV_DEV 0 |
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#define CONFIG_SYS_MMC_ENV_PART 0 |
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#define CONFIG_ENV_SIZE (64 * 1024) |
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#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) |
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#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024) |
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#define CONFIG_SUPPORT_EMMC_BOOT |
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/* PCI */ |
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#define CONFIG_CMD_PCI |
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/* RTC */ |
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 |
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#define CONFIG_RTC_MC146818 |
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#endif |
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