From c1446ac6c11dab19490a552f16ab39df8d5b3de3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 8 Sep 2015 17:52:45 -0600 Subject: [PATCH 1/2] x86: chromebook_link: Expand early malloc() memory Now that PCI bridges are probed before relocation we need additional memory. Each PCI bridge takes 240 bytes at present since it uses the same uclass as the PCI controller. Probably we should split this out so that bridges have their own uclass. Expand the memory on link so that it works correctly. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- configs/chromebook_link_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 1c10124..21e85f3 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -1,4 +1,5 @@ CONFIG_X86=y +CONFIG_SYS_MALLOC_F_LEN=0x1800 CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y From 196193a4d4963a8dde00c7cdd0ec83b60ea61e61 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 28 Sep 2015 02:11:59 -0700 Subject: [PATCH 2/2] x86: fsp: Report correct number of E820 table entries The logic to calculate the number of E820 table entries is wrong when walking through the FSP HOB tables. Fix it. Signed-off-by: Bin Meng Tested-by: Jian Luo Acked-by: Simon Glass --- arch/x86/lib/fsp/fsp_dram.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 28552fa..e51ca96 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -72,9 +72,10 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) entries[num_entries].type = E820_RAM; else if (res_desc->type == RES_MEM_RESERVED) entries[num_entries].type = E820_RESERVED; + + num_entries++; } hdr = get_next_hob(hdr); - num_entries++; } /* Mark PCIe ECAM address range as reserved */