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@ -3091,21 +3091,24 @@ static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g, |
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return 1; |
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} |
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/* precharge all banks and activate row 0 in bank "000..." and bank "111..." */ |
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/**
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* mem_precharge_and_activate() - Precharge all banks and activate |
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* |
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* Precharge all banks and activate row 0 in bank "000..." and bank "111...". |
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*/ |
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static void mem_precharge_and_activate(void) |
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{ |
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uint32_t r; |
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int r; |
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for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) { |
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if (param->skip_ranks[r]) { |
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/* request to skip the rank */ |
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/* Test if the rank should be skipped. */ |
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if (param->skip_ranks[r]) |
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continue; |
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} |
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/* set rank */ |
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/* Set rank. */ |
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set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); |
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/* precharge all banks ... */ |
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/* Precharge all banks. */ |
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writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS | |
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RW_MGR_RUN_SINGLE_GROUP_OFFSET); |
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@ -3117,7 +3120,7 @@ static void mem_precharge_and_activate(void) |
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writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, |
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&sdr_rw_load_jump_mgr_regs->load_jump_add1); |
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/* activate rows */ |
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/* Activate rows. */ |
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writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS | |
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RW_MGR_RUN_SINGLE_GROUP_OFFSET); |
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} |
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