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@ -1,10 +1,10 @@ |
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/*
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* Chip-specific header file for the AT91SAM9M1x family |
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* |
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* Copyright (C) 2008 Atmel Corporation. |
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* (C) 2008 Atmel Corporation. |
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* |
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* Common definitions. |
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* Based on AT91SAM9G45 preliminary datasheet. |
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* Definitions for the SoC: |
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* AT91SAM9G45 |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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@ -16,137 +16,126 @@ |
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#define AT91SAM9G45_H |
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/*
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* Peripheral identifiers/interrupts. |
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* defines to be used in other places |
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*/ |
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#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
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#define AT91_ID_SYS 1 /* System Controller Interrupt */ |
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#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ |
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#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ |
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#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ |
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#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ |
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#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ |
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#define AT91SAM9G45_ID_US0 7 /* USART 0 */ |
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#define AT91SAM9G45_ID_US1 8 /* USART 1 */ |
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#define AT91SAM9G45_ID_US2 9 /* USART 2 */ |
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#define AT91SAM9G45_ID_US3 10 /* USART 3 */ |
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#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ |
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#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ |
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#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ |
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#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ |
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#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ |
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#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ |
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#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ |
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#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ |
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#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ |
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#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ |
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#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ |
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#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ |
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#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ |
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#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ |
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#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ |
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#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ |
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#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ |
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#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ |
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#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ |
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#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ |
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#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ |
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#define AT91_EMAC_BASE 0xfffbc000 |
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#define AT91_SMC_BASE 0xffffe800 |
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#define AT91_MATRIX_BASE 0xffffea00 |
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#define AT91_PIO_BASE 0xfffff200 |
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#define AT91_PMC_BASE 0xfffffc00 |
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#define AT91_RSTC_BASE 0xfffffd00 |
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#define AT91_PIT_BASE 0xfffffd30 |
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#define AT91_WDT_BASE 0xfffffd40 |
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#ifdef CONFIG_AT91_LEGACY |
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#define CONFIG_ARM926EJS /* ARM926EJS Core */ |
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#define CONFIG_AT91FAMILY /* it's a member of AT91 */ |
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/*
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* User Peripheral physical base addresses. |
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* Peripheral identifiers/interrupts. |
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*/ |
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#define AT91SAM9G45_BASE_UDPHS 0xfff78000 |
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#define AT91SAM9G45_BASE_TC0 0xfff7c000 |
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#define AT91SAM9G45_BASE_TC1 0xfff7c040 |
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#define AT91SAM9G45_BASE_TC2 0xfff7c080 |
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#define AT91SAM9G45_BASE_MCI0 0xfff80000 |
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#define AT91SAM9G45_BASE_TWI0 0xfff84000 |
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#define AT91SAM9G45_BASE_TWI1 0xfff88000 |
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#define AT91SAM9G45_BASE_US0 0xfff8c000 |
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#define AT91SAM9G45_BASE_US1 0xfff90000 |
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#define AT91SAM9G45_BASE_US2 0xfff94000 |
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#define AT91SAM9G45_BASE_US3 0xfff98000 |
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#define AT91SAM9G45_BASE_SSC0 0xfff9c000 |
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#define AT91SAM9G45_BASE_SSC1 0xfffa0000 |
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#define AT91SAM9G45_BASE_SPI0 0xfffa4000 |
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#define AT91SAM9G45_BASE_SPI1 0xfffa8000 |
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#define AT91SAM9G45_BASE_AC97C 0xfffac000 |
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#define AT91SAM9G45_BASE_TSC 0xfffb0000 |
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#define AT91SAM9G45_BASE_ISI 0xfffb4000 |
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#define AT91SAM9G45_BASE_PWMC 0xfffb8000 |
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#define AT91SAM9G45_BASE_EMAC 0xfffbc000 |
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#define AT91SAM9G45_BASE_AES 0xfffc0000 |
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#define AT91SAM9G45_BASE_TDES 0xfffc4000 |
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#define AT91SAM9G45_BASE_SHA 0xfffc8000 |
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#define AT91SAM9G45_BASE_TRNG 0xfffcc000 |
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#define AT91SAM9G45_BASE_MCI1 0xfffd0000 |
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#define AT91SAM9G45_BASE_TC3 0xfffd4000 |
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#define AT91SAM9G45_BASE_TC4 0xfffd4040 |
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#define AT91SAM9G45_BASE_TC5 0xfffd4080 |
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#define AT91_BASE_SYS 0xffffe200 |
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#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
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#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ |
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#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */ |
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#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */ |
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#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */ |
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#define ATMEL_ID_PIODE 5 /* Parallel I/O Controller D and E */ |
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#define ATMEL_ID_TRNG 6 /* True Random Number Generator */ |
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#define ATMEL_ID_USART0 7 /* USART 0 */ |
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#define ATMEL_ID_USART1 8 /* USART 1 */ |
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#define ATMEL_ID_USART2 9 /* USART 2 */ |
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#define ATMEL_ID_USART3 10 /* USART 3 */ |
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#define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ |
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#define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */ |
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#define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */ |
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#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ |
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#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ |
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#define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */ |
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#define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */ |
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#define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ |
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#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ |
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#define ATMEL_ID_TSC 20 /* Touch Screen ADC Controller */ |
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#define ATMEL_ID_DMA 21 /* DMA Controller */ |
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#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ |
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#define ATMEL_ID_LCDC 23 /* LCD Controller */ |
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#define ATMEL_ID_AC97C 24 /* AC97 Controller */ |
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#define ATMEL_ID_EMAC 25 /* Ethernet MAC */ |
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#define ATMEL_ID_ISI 26 /* Image Sensor Interface */ |
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#define ATMEL_ID_UDPHS 27 /* USB Device High Speed */ |
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#define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ |
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#define ATMEL_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ |
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#define ATMEL_ID_VDEC 30 /* Video Decoder */ |
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#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller */ |
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/*
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* System Peripherals (offset from AT91_BASE_SYS) |
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* User Peripherals physical base addresses. |
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*/ |
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#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) |
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#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) |
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#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) |
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#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) |
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#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
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#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) |
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#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) |
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#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) |
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#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) |
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#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) |
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#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) |
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#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) |
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#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) |
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) |
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) |
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#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) |
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) |
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) |
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#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
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#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) |
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#define AT91_USART0 AT91SAM9G45_BASE_US0 |
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#define AT91_USART1 AT91SAM9G45_BASE_US1 |
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#define AT91_USART2 AT91SAM9G45_BASE_US2 |
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#define AT91_USART3 AT91SAM9G45_BASE_US3 |
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#define ATMEL_BASE_UDPHS 0xfff78000 |
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#define ATMEL_BASE_TC0 0xfff7c000 |
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#define ATMEL_BASE_TC1 0xfff7c040 |
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#define ATMEL_BASE_TC2 0xfff7c080 |
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#define ATMEL_BASE_MCI0 0xfff80000 |
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#define ATMEL_BASE_TWI0 0xfff84000 |
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#define ATMEL_BASE_TWI1 0xfff88000 |
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#define ATMEL_BASE_USART0 0xfff8c000 |
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#define ATMEL_BASE_USART1 0xfff90000 |
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#define ATMEL_BASE_USART2 0xfff94000 |
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#define ATMEL_BASE_USART3 0xfff98000 |
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#define ATMEL_BASE_SSC0 0xfff9c000 |
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#define ATMEL_BASE_SSC1 0xfffa0000 |
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#define ATMEL_BASE_SPI0 0xfffa4000 |
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#define ATMEL_BASE_SPI1 0xfffa8000 |
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#define ATMEL_BASE_AC97C 0xfffac000 |
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#define ATMEL_BASE_TSC 0xfffb0000 |
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#define ATMEL_BASE_ISI 0xfffb4000 |
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#define ATMEL_BASE_PWMC 0xfffb8000 |
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#define ATMEL_BASE_EMAC 0xfffbc000 |
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#define ATMEL_BASE_AES 0xfffc0000 |
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#define ATMEL_BASE_TDES 0xfffc4000 |
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#define ATMEL_BASE_SHA 0xfffc8000 |
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#define ATMEL_BASE_TRNG 0xfffcc000 |
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#define ATMEL_BASE_MCI1 0xfffd0000 |
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#define ATMEL_BASE_TC3 0xfffd4000 |
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#define ATMEL_BASE_TC4 0xfffd4040 |
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#define ATMEL_BASE_TC5 0xfffd4080 |
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/* Reserved: 0xfffd8000 - 0xffffe1ff */ |
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#endif |
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/*
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* System Peripherals physical base addresses. |
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*/ |
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#define ATMEL_BASE_SYS 0xffffe200 |
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#define ATMEL_BASE_ECC 0xffffe200 |
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#define ATMEL_BASE_DDRSDRC1 0xffffe400 |
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#define ATMEL_BASE_DDRSDRC0 0xffffe600 |
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#define ATMEL_BASE_SMC 0xffffe800 |
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#define ATMEL_BASE_MATRIX 0xffffea00 |
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#define ATMEL_BASE_DMA 0xffffec00 |
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#define ATMEL_BASE_DBGU 0xffffee00 |
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#define ATMEL_BASE_AIC 0xfffff000 |
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#define ATMEL_BASE_PIOA 0xfffff200 |
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#define ATMEL_BASE_PIOB 0xfffff400 |
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#define ATMEL_BASE_PIOC 0xfffff600 |
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#define ATMEL_BASE_PIOD 0xfffff800 |
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#define ATMEL_BASE_PIOE 0xfffffa00 |
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#define ATMEL_BASE_PMC 0xfffffc00 |
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#define ATMEL_BASE_RSTC 0xfffffd00 |
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#define ATMEL_BASE_SHDWN 0xfffffd10 |
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#define ATMEL_BASE_RTT 0xfffffd20 |
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#define ATMEL_BASE_PIT 0xfffffd30 |
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#define ATMEL_BASE_WDT 0xfffffd40 |
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#define ATMEL_BASE_GPBR 0xfffffd60 |
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#define ATMEL_BASE_RTC 0xfffffdb0 |
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/* Reserved: 0xfffffdc0 - 0xffffffff */ |
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/*
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* Internal Memory. |
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*/ |
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#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
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#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ |
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#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ |
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#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ |
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#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ |
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#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ |
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#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ |
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#define ATMEL_BASE_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ |
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#define ATMEL_BASE_HCI 0x00700000 /* USB Host controller (OHCI) */ |
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#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */ |
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#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */ |
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#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ |
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#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ |
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#define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */ |
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#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ |
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#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ |
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#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 |
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/*
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* Other misc defines |
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*/ |
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#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ |
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/*
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* Cpu Name |
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*/ |
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#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" |
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#define ATMEL_CPU_NAME "AT91SAM9G45" |
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#endif |
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Reinhard Meyer
14 years ago
committed by
Albert ARIBAUD