@ -29,12 +29,16 @@ ENTRY(lowlevel_init)
bl d e b u g _ l l _ i n i t
# endif
bl s e t u p _ i n i t _ r a m @ RAM area for stack and page talbe
/ *
* Now w e a r e u s i n g t h e p a g e t a b l e e m b e d d e d i n t h e B o o t R O M .
* It i s n o t h a n d y s i n c e i t i s n o t a s t r a i g h t m a p p e d t a b l e f o r s L D 3 .
* What w e n e e d t o d o n e x t i s t o s w i t c h o v e r t o t h e p a g e t a b l e i n S P L .
* Also, t h e a c c e s s t o t h e e x t e r n a l b u s i s p r o h i b i t e d . W h a t w e n e e d
* to d o n e x t i s t o c r e a t e a p a g e t a b l e a n d s w i t c h o v e r t o i t .
* /
ldr r3 , =init_page_table @ page table must be 16KB aligned
bl c r e a t e _ p a g e _ t a b l e
bl v7 _ f l u s h _ d c a c h e _ a l l
/* Disable MMU and Dcache before switching Page Table */
mrc p15 , 0 , r0 , c1 , c0 , 0 @ SCTLR (System Control Register)
@ -43,8 +47,6 @@ ENTRY(lowlevel_init)
bl e n a b l e _ m m u
bl s e t u p _ i n i t _ r a m @ RAM area for temporary stack pointer
mov l r , r8 @ restore link
mov p c , l r @ back to my caller
ENDPROC( l o w l e v e l _ i n i t )
@ -55,7 +57,7 @@ ENTRY(enable_mmu)
orr r0 , r0 , #0x20 @ disable TTBR1
mcr p15 , 0 , r0 , c2 , c0 , 2
orr r0 , r3 , #0x8 @ Outer Cacheability for table walks: WBWA
orr r0 , r12 , #0x8 @ Outer Cacheability for table walks: WBWA
mcr p15 , 0 , r0 , c2 , c0 , 0 @ TTBR0
mov r0 , #0
@ -82,8 +84,9 @@ ENDPROC(enable_mmu)
* For P H 1 - P r o 4 o r o l d e r S o C s , t h e s i z e o f W A Y i s 3 2 K B .
* It i s l a r g e e n o u g h f o r t m p R A M .
* /
# define B O O T _ R A M _ S I Z E ( S Z _ 3 2 K )
# define B O O T _ W A Y _ B I T S ( 0 x00 0 0 0 1 0 0 ) / * w a y 8 * /
# define B O O T _ R A M _ S I Z E ( S Z _ 3 2 K )
# define B O O T _ R A M _ B A S E ( ( C O N F I G _ S P L _ S T A C K ) - ( B O O T _ R A M _ S I Z E ) )
# define B O O T _ W A Y _ B I T S ( 0 x00 0 0 0 1 0 0 ) / * w a y 8 * /
ENTRY( s e t u p _ i n i t _ r a m )
/ *
@ -96,7 +99,7 @@ ENTRY(setup_init_ram)
ldr r0 , = 0 x00 4 0 8 0 0 6 @ touch to zero with address range
ldr r1 , = S S C O Q M
str r0 , [ r1 ]
ldr r0 , = ( C O N F I G _ S P L _ S T A C K - B O O T _ R A M _ S I Z E ) @ base address
ldr r0 , = B O O T _ R A M _ B A S E
ldr r1 , = S S C O Q A D
str r0 , [ r1 ]
ldr r0 , = B O O T _ R A M _ S I Z E
@ -119,3 +122,86 @@ ENTRY(setup_init_ram)
mov p c , l r
ENDPROC( s e t u p _ i n i t _ r a m )
# define D E V I C E 0 x00 0 0 2 0 0 2 / * N o n - s h a r e a b l e D e v i c e * /
# define N O R M A L 0 x00 0 0 0 0 0 e / * N o r m a l M e m o r y W r i t e - B a c k , N o W r i t e - A l l o c a t e * /
ENTRY( c r e a t e _ p a g e _ t a b l e )
ldr r0 , = D E V I C E
ldr r1 , = B O O T _ R A M _ B A S E
mov r12 , r1 @ r12 is preserved during D-cache flush
0 : str r0 , [ r1 ] , #4 @ specify all the sections as Device
adds r0 , r0 , #0x00100000
bcc 0 b
ldr r0 , = N O R M A L
str r0 , [ r12 ] @ mark the first section as Normal
add r0 , r0 , #0x00100000
str r0 , [ r12 , #4 ] @ mark the second section as Normal
mov p c , l r
ENDPROC( c r e a t e _ p a g e _ t a b l e )
/* We don't use Thumb instructions for now */
# define A R M ( x . . . ) x
# define T H U M B ( x . . . )
/ *
* v7 _ f l u s h _ d c a c h e _ a l l ( )
*
* Flush t h e w h o l e D - c a c h e .
*
* Corrupted r e g i s t e r s : r0 - r7 , r9 - r11 ( r6 o n l y i n T h u m b m o d e )
*
* - mm - m m _ s t r u c t d e s c r i b i n g a d d r e s s s p a c e
*
* Note : copied f r o m a r c h / a r m / m m / c a c h e - v7 . S o f L i n u x 4 . 4
* /
ENTRY( v7 _ f l u s h _ d c a c h e _ a l l )
dmb @ ensure ordering with previous memory accesses
mrc p15 , 1 , r0 , c0 , c0 , 1 @ read clidr
mov r3 , r0 , l s r #23 @ move LoC into position
ands r3 , r3 , #7 < < 1 @ extract LoC*2 from clidr
beq f i n i s h e d @ if loc is 0, then no need to clean
start_flush_levels :
mov r10 , #0 @ start clean at cache level 0
flush_levels :
add r2 , r10 , r10 , l s r #1 @ work out 3x current cache level
mov r1 , r0 , l s r r2 @ extract cache type bits from clidr
and r1 , r1 , #7 @ mask of the bits for current cache only
cmp r1 , #2 @ see what cache we have at this level
blt s k i p @ skip if no cache, or just i-cache
mcr p15 , 2 , r10 , c0 , c0 , 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr
mrc p15 , 1 , r1 , c0 , c0 , 0 @ read the new csidr
and r2 , r1 , #7 @ extract the length of the cache lines
add r2 , r2 , #4 @ add 4 (line length offset)
movw r4 , #0x3ff
ands r4 , r4 , r1 , l s r #3 @ find maximum number on the way size
clz r5 , r4 @ find bit position of way size increment
movw r7 , #0x7fff
ands r7 , r7 , r1 , l s r #13 @ extract max number of the index size
loop1 :
mov r9 , r7 @ create working copy of max index
loop2 :
ARM( o r r r11 , r10 , r4 , l s l r5 ) @ factor way and cache number into r11
THUMB( l s l r6 , r4 , r5 )
THUMB( o r r r11 , r10 , r6 ) @ factor way and cache number into r11
ARM( o r r r11 , r11 , r9 , l s l r2 ) @ factor index number into r11
THUMB( l s l r6 , r9 , r2 )
THUMB( o r r r11 , r11 , r6 ) @ factor index number into r11
mcr p15 , 0 , r11 , c7 , c14 , 2 @ clean & invalidate by set/way
subs r9 , r9 , #1 @ decrement the index
bge l o o p2
subs r4 , r4 , #1 @ decrement the way
bge l o o p1
skip :
add r10 , r10 , #2 @ increment cache number
cmp r3 , r10
bgt f l u s h _ l e v e l s
finished :
mov r10 , #0 @ swith back to cache level 0
mcr p15 , 2 , r10 , c0 , c0 , 0 @ select current cache level in cssr
dsb s t
isb
mov p c , l r
ENDPROC( v7 _ f l u s h _ d c a c h e _ a l l )
Masahiro Yamada
8 years ago