From 4bfacad4e796f2e121ee7432705ecc9c61e7b6ca Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Fri, 15 Jan 2010 19:15:51 +0530
Subject: [PATCH] SPEAr : emi controller initialization for CFI driver support

SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface
Paraller NOR flashes. This patch adds the support for this IP

The standard CFI driver is used to interface with NOR flashes

Signed-off-by: Vipin <vipin.kumar@st.com>
---
 board/spear/common/spr_misc.c        | 59 ++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-spear/spr_emi.h | 54 +++++++++++++++++++++++++++++++++
 2 files changed, 113 insertions(+)
 create mode 100644 include/asm-arm/arch-spear/spr_emi.h

diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index 204ccf2..e356912 100755
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -27,6 +27,7 @@
 #include <net.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/spr_emi.h>
 #include <asm/arch/spr_xloader_table.h>
 #include <asm/arch/spr_defs.h>
 
@@ -83,6 +84,61 @@ int misc_init_r(void)
 	return 0;
 }
 
+#ifdef CONFIG_SPEAR_EMI
+struct cust_emi_para {
+	unsigned int tap;
+	unsigned int tsdp;
+	unsigned int tdpw;
+	unsigned int tdpr;
+	unsigned int tdcs;
+};
+
+/* EMI timing setting of m28w640hc of linux kernel */
+const struct cust_emi_para emi_timing_m28w640hc = {
+	.tap = 0x10,
+	.tsdp = 0x05,
+	.tdpw = 0x0a,
+	.tdpr = 0x0a,
+	.tdcs = 0x05,
+};
+
+/* EMI timing setting of bootrom */
+const struct cust_emi_para emi_timing_bootrom = {
+	.tap = 0xf,
+	.tsdp = 0x0,
+	.tdpw = 0xff,
+	.tdpr = 0x111,
+	.tdcs = 0x02,
+};
+
+void spear_emi_init(void)
+{
+	const struct cust_emi_para *p = &emi_timing_m28w640hc;
+	struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
+	unsigned int cs;
+	unsigned int val, tmp;
+
+	val = readl(CONFIG_SPEAR_RASBASE);
+
+	if (val & EMI_ACKMSK)
+		tmp = 0x3f;
+	else
+		tmp = 0x0;
+
+	writel(tmp, &emi_regs_p->ack);
+
+	for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
+		writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
+		writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
+		writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
+		writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
+		writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
+		writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
+		       &emi_regs_p->bank_regs[cs].control);
+	}
+}
+#endif
+
 int spear_board_init(ulong mach_type)
 {
 	struct xloader_table *xloader_tb =
@@ -104,6 +160,9 @@ int spear_board_init(ulong mach_type)
 		       sizeof(chip->version));
 	}
 
+#ifdef CONFIG_SPEAR_EMI
+	spear_emi_init();
+#endif
 	return 0;
 }
 
diff --git a/include/asm-arm/arch-spear/spr_emi.h b/include/asm-arm/arch-spear/spr_emi.h
new file mode 100644
index 0000000..c1f1c2a
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_emi.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPEAR_EMI_H__
+#define __SPEAR_EMI_H__
+
+#ifdef CONFIG_SPEAR_EMI
+
+struct emi_bank_regs {
+	u32 tap;
+	u32 tsdp;
+	u32 tdpw;
+	u32 tdpr;
+	u32 tdcs;
+	u32 control;
+};
+
+struct emi_regs {
+	struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS];
+	u32 tout;
+	u32 ack;
+	u32 irq;
+};
+
+#define EMI_ACKMSK		0x40
+
+/* control register definitions */
+#define EMI_CNTL_ENBBYTEW	(1 << 2)
+#define EMI_CNTL_ENBBYTER	(1 << 3)
+#define EMI_CNTL_ENBBYTERW	(EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
+
+#endif
+
+#endif