Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs by moving SPL related functions into separate file. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com> Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>master
Ladislav Michl
7 years ago
committed by
Tom Rini
parent
ea8c7fcacc
commit
4c699a4747
@ -0,0 +1,80 @@ |
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/*
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <twl4030.h> |
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#include <asm/io.h> |
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#include <asm/omap_mmc.h> |
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#include <asm/arch/mux.h> |
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#include <asm/arch/sys_proto.h> |
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#include <jffs2/load_kernel.h> |
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#include <linux/mtd/nand.h> |
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#include "igep00x0.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Routine: set_muxconf_regs |
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* Description: Setting up the configuration Mux registers specific to the |
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* hardware. Many pins need to be moved from protect to primary |
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* mode. |
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*/ |
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void set_muxconf_regs(void) |
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{ |
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MUX_DEFAULT(); |
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) |
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MUX_IGEP0020(); |
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#endif |
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) |
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MUX_IGEP0030(); |
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#endif |
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} |
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/*
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* Routine: board_init |
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* Description: Early hardware init. |
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*/ |
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int board_init(void) |
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{ |
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int loops = 100; |
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/* find out flash memory type, assume NAND first */ |
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gpmc_cs0_flash = MTD_DEV_TYPE_NAND; |
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gpmc_init(); |
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/* Issue a RESET and then READID */ |
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writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); |
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writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); |
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while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) |
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!= NAND_STATUS_READY) { |
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udelay(1); |
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if (--loops == 0) { |
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gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; |
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gpmc_init(); /* reinitialize for OneNAND */ |
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break; |
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} |
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} |
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/* boot param addr */ |
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
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#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) |
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status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON); |
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#endif |
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return 0; |
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} |
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#if defined(CONFIG_MMC) |
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int board_mmc_init(bd_t *bis) |
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{ |
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return omap_mmc_init(0, 0, 0, -1, -1); |
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} |
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void board_mmc_power_init(void) |
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{ |
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twl4030_power_mmc_init(0); |
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} |
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#endif |
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@ -0,0 +1,64 @@ |
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/*
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/io.h> |
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#include <asm/arch/mem.h> |
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#include <asm/arch/sys_proto.h> |
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#include <jffs2/load_kernel.h> |
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#include <linux/mtd/nand.h> |
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#include "igep00x0.h" |
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/*
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* Routine: get_board_mem_timings |
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* Description: If we use SPL then there is no x-loader nor config header |
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* so we have to setup the DDR timings ourself on both banks. |
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*/ |
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void get_board_mem_timings(struct board_sdrc_timings *timings) |
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{ |
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int mfr, id, err = identify_nand_chip(&mfr, &id); |
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timings->mr = MICRON_V_MR_165; |
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if (!err) { |
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switch (mfr) { |
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case NAND_MFR_HYNIX: |
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timings->mcfg = HYNIX_V_MCFG_200(256 << 20); |
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timings->ctrla = HYNIX_V_ACTIMA_200; |
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timings->ctrlb = HYNIX_V_ACTIMB_200; |
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break; |
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case NAND_MFR_MICRON: |
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timings->mcfg = MICRON_V_MCFG_200(256 << 20); |
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timings->ctrla = MICRON_V_ACTIMA_200; |
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timings->ctrlb = MICRON_V_ACTIMB_200; |
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break; |
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default: |
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/* Should not happen... */ |
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break; |
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} |
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
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gpmc_cs0_flash = MTD_DEV_TYPE_NAND; |
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} else { |
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if (get_cpu_family() == CPU_OMAP34XX) { |
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timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); |
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timings->ctrla = NUMONYX_V_ACTIMA_165; |
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timings->ctrlb = NUMONYX_V_ACTIMB_165; |
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; |
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} else { |
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timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); |
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timings->ctrla = NUMONYX_V_ACTIMA_200; |
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timings->ctrlb = NUMONYX_V_ACTIMB_200; |
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
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} |
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gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; |
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} |
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} |
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#ifdef CONFIG_SPL_OS_BOOT |
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int spl_start_uboot(void) |
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{ |
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/* break into full u-boot on 'c' */ |
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if (serial_tstc() && serial_getc() == 'c') |
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return 1; |
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return 0; |
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} |
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#endif |
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