Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xx

Browse Source
master
Wolfgang Denk 18 years ago
parent 5e918a98c2 16c3cde050
commit 4c9e98ace7
8 changed files with 128 additions and 138 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 15
      board/freescale/common/Makefile
  2. 3
      board/freescale/common/fsl_diu_fb.c
  3. 218
      board/freescale/common/pixis.c
  4. 3
      board/freescale/common/pq-mds-pib.c
  5. 2
      board/freescale/common/sys_eeprom.c
  6. 12
      board/freescale/mpc8610hpcd/Makefile
  7. 10
      include/configs/MPC8610HPCD.h
  8. 3
      include/configs/MPC8641HPCN.h

15
board/freescale/common/Makefile
Unescape View File

@ -29,14 +29,13 @@ endif
LIB = $(obj)lib$(VENDOR).a
COBJS := sys_eeprom.o \
pixis.o \
pq-mds-pib.o \
fsl_logo_bmp.o \
fsl_diu_fb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
COBJS-${CONFIG_FSL_PIXIS} += pixis.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)

3
board/freescale/common/fsl_diu_fb.c
Unescape View File

@ -27,8 +27,6 @@
#include <i2c.h>
#include <malloc.h>
#ifdef CONFIG_FSL_DIU_FB
#include "fsl_diu_fb.h"
#ifdef DEBUG
@ -615,4 +613,3 @@ void fsl_diu_clear_screen(void)
memset(info->screen_base, 0, info->smem_len);
}
#endif /* CONFIG_FSL_DIU_FB */

218
board/freescale/common/pixis.c
Unescape View File

@ -25,9 +25,8 @@
#include <common.h>
#include <command.h>
#include <watchdog.h>
#ifdef CONFIG_FSL_PIXIS
#include <asm/cache.h>
#include "pixis.h"
@ -184,7 +183,7 @@ int set_px_corepll(ulong corepll)
void read_from_px_regs(int set)
{
u8 mask = 0x1C;
u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
if (set)
@ -197,7 +196,7 @@ void read_from_px_regs(int set)
void read_from_px_regs_altbank(int set)
{
u8 mask = 0x04;
u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
if (set)
@ -208,15 +207,26 @@ void read_from_px_regs_altbank(int set)
}
#ifndef CFG_PIXIS_VBOOT_MASK
#define CFG_PIXIS_VBOOT_MASK 0x40
#define CFG_PIXIS_VBOOT_MASK (0x40)
#endif
void clear_altbank(void)
{
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
tmp &= ~CFG_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}
void set_altbank(void)
{
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
tmp ^= CFG_PIXIS_VBOOT_MASK;
tmp |= CFG_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}
@ -227,11 +237,11 @@ void set_px_go(void)
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
tmp = tmp & 0x1E;
tmp = tmp & 0x1E; /* clear GO bit */
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
tmp = tmp | 0x01;
tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
}
@ -293,7 +303,7 @@ static ulong strfractoint(uchar *strptr)
* simply create the intarr.
*/
i = 0;
while (strptr[i] != 46) {
while (strptr[i] != '.') {
if (strptr[i] == 0) {
no_dec = 1;
break;
@ -313,7 +323,7 @@ static ulong strfractoint(uchar *strptr)
} else {
j = 0;
i++; /* Skipping the decimal point */
while ((strptr[i] > 47) && (strptr[i] < 58)) {
while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
decarr[j] = strptr[i];
i++;
j++;
@ -340,8 +350,14 @@ static ulong strfractoint(uchar *strptr)
int
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong val;
ulong corepll;
unsigned int i;
char *p_cf = NULL;
char *p_cf_sysclk = NULL;
char *p_cf_corepll = NULL;
char *p_cf_mpxpll = NULL;
char *p_altbank = NULL;
char *p_wd = NULL;
unsigned int unknown_param = 0;
/*
* No args is a simple reset request.
@ -351,116 +367,97 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* not reached */
}
if (strcmp(argv[1], "cf") == 0) {
for (i = 1; i < argc; i++) {
if (strcmp(argv[i], "cf") == 0) {
p_cf = argv[i];
if (i + 3 >= argc) {
break;
}
p_cf_sysclk = argv[i+1];
p_cf_corepll = argv[i+2];
p_cf_mpxpll = argv[i+3];
i += 3;
continue;
}
/*
* Reset with frequency changed:
* cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
*/
if (argc < 5) {
puts(cmdtp->usage);
return 1;
if (strcmp(argv[i], "altbank") == 0) {
p_altbank = argv[i];
continue;
}
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
corepll = strfractoint((uchar *)argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
puts("Resetting board with values from ");
puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
set_px_go();
} else {
puts(cmdtp->usage);
return 1;
if (strcmp(argv[i], "wd") == 0) {
p_wd = argv[i];
continue;
}
while (1) ; /* Not reached */
} else if (strcmp(argv[1], "altbank") == 0) {
/*
* Reset using alternate flash bank:
*/
if (argv[2] == 0) {
/*
* Reset from alternate bank without changing
* frequency and without watchdog timer enabled.
* altbank
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if (argc > 2) {
puts(cmdtp->usage);
return 1;
}
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Resetting board to boot from the other bank.\n");
set_px_go();
} else if (strcmp(argv[2], "cf") == 0) {
/*
* Reset with frequency changed
* altbank cf <SYSCLK freq> <COREPLL ratio>
* <MPXPLL ratio>
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
corepll = strfractoint((uchar *)argv[4]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[5],
NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1);
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA\n");
puts("Resetting board with values from ");
puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
puts("to boot from the other bank.\n");
set_px_go_with_watchdog();
} else {
puts(cmdtp->usage);
return 1;
}
unknown_param = 1;
}
while (1) ; /* Not reached */
} else if (strcmp(argv[2], "wd") == 0) {
/*
* Reset from alternate bank without changing
* frequencies but with watchdog timer enabled:
* altbank wd
*/
read_from_px_regs(0);
read_from_px_regs_altbank(0);
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA\n");
puts("Resetting board to boot from the other bank.\n");
set_px_go_with_watchdog();
while (1) ; /* Not reached */
} else {
puts(cmdtp->usage);
/*
* Check that cf has all required parms
*/
if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
|| unknown_param) {
puts(cmdtp->help);
return 1;
}
/*
* PIXIS seems to be sensitive to the ordering of
* the registers that are touched.
*/
read_from_px_regs(0);
if (p_altbank) {
read_from_px_regs_altbank(0);
}
clear_altbank();
/*
* Clock configuration specified.
*/
if (p_cf) {
unsigned long sysclk;
unsigned long corepll;
unsigned long mpxpll;
sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
corepll = strfractoint((uchar *) p_cf_corepll);
mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
if (!(set_px_sysclk(sysclk)
&& set_px_corepll(corepll)
&& set_px_mpxpll(mpxpll))) {
puts(cmdtp->help);
return 1;
}
read_from_px_regs(1);
}
/*
* Altbank specified
*
* NOTE CHANGE IN BEHAVIOR: previous code would default
* to enabling watchdog if altbank is specified.
* Now the watchdog must be enabled explicitly using 'wd'.
*/
if (p_altbank) {
set_altbank();
read_from_px_regs_altbank(1);
}
/*
* Reset with watchdog specified.
*/
if (p_wd) {
set_px_go_with_watchdog();
} else {
puts(cmdtp->usage);
return 1;
set_px_go();
}
/*
* Shouldn't be reached.
*/
return 0;
}
@ -474,4 +471,3 @@ U_BOOT_CMD(
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
);
#endif /* CONFIG_FSL_PIXIS */

3
board/freescale/common/pq-mds-pib.c
Unescape View File

@ -12,8 +12,6 @@
#include <i2c.h>
#include <asm/io.h>
#ifdef CONFIG_PQ_MDS_PIB
#include "pq-mds-pib.h"
int pib_init(void)
@ -102,4 +100,3 @@ int pib_init(void)
i2c_set_bus_num(orig_i2c_bus);
return 0;
}
#endif /* CONFIG_PQ_MDS_PIB */

2
board/freescale/common/sys_eeprom.c
Unescape View File

@ -27,7 +27,6 @@
#include <i2c.h>
#include <linux/ctype.h>
#ifdef CFG_ID_EEPROM
typedef struct {
unsigned char id[4]; /* 0x0000 - 0x0003 */
unsigned char sn[12]; /* 0x0004 - 0x000F */
@ -253,4 +252,3 @@ int mac_read_from_eeprom(void)
}
return 0;
}
#endif /* CFG_ID_EEPROM */

12
board/freescale/mpc8610hpcd/Makefile
Unescape View File

@ -27,14 +27,14 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o \
../common/sys_eeprom.o \
../common/pixis.o \
mpc8610hpcd_diu.o \
../common/fsl_diu_fb.o
SOBJS := init.o
COBJS := $(BOARD).o
COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o
COBJS += ${COBJS-y}
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

10
include/configs/MPC8610HPCD.h
Unescape View File

@ -141,6 +141,9 @@
#endif
#define CFG_ID_EEPROM
#ifdef CFG_ID_EEPROM
#define CONFIG_ID_EEPROM
#endif
#define ID_EEPROM_ADDR 0x57
@ -312,11 +315,8 @@
#define CONFIG_CMD_NET
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_RTL8139
#define CONFIG_SK98
#define CONFIG_EEPRO100
#define CONFIG_TULIP
#ifdef CONFIG_TULIP
#define CONFIG_ULI526X
#ifdef CONFIG_ULI526X
#define CONFIG_ETHADDR 00:E0:0C:00:00:01
#endif

3
include/configs/MPC8641HPCN.h
Unescape View File

@ -152,6 +152,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CFG_ID_EEPROM 1
#ifdef CFG_ID_EEPROM
#define CONFIG_ID_EEPROM
#endif
#define ID_EEPROM_ADDR 0x57
/*

Write Preview
Loading…
Cancel
Save