This patch add support for a new Samsung board Trats2. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>master
Piotr Wilczek
11 years ago
committed by
Minkyu Kang
parent
ecda331463
commit
4d6c96711b
@ -0,0 +1,34 @@ |
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#
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# Copyright (c) 2000 - 2013 Samsung Electronics Co., Ltd. All rights reserved.
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# Sanghee Kim <sh0130.kim@samsung.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS-y := trats2.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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$(LIB): $(obj).depend $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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clean: |
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rm -f $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,513 @@ |
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved. |
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* Sanghee Kim <sh0130.kim@samsung.com> |
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* Piotr Wilczek <p.wilczek@samsung.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <lcd.h> |
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#include <asm/io.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/mmc.h> |
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#include <asm/arch/power.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/mipi_dsim.h> |
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#include <asm/arch/pinmux.h> |
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#include <asm/arch/power.h> |
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#include <power/pmic.h> |
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#include <power/max77686_pmic.h> |
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#include <power/battery.h> |
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#include <power/max77693_pmic.h> |
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#include <power/max77693_muic.h> |
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#include <power/max77693_fg.h> |
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#include <libtizen.h> |
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#include <errno.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static struct exynos4x12_gpio_part1 *gpio1; |
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static struct exynos4x12_gpio_part2 *gpio2; |
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static unsigned int board_rev = -1; |
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static inline u32 get_model_rev(void); |
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static void check_hw_revision(void) |
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{ |
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int modelrev = 0; |
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int i; |
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gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; |
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/*
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* GPM1[1:0]: MODEL_REV[1:0] |
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* Don't set as pull-none for these N/C pin. |
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* TRM say that it may cause unexcepted state and leakage current. |
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* and pull-none is only for output function. |
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*/ |
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for (i = 0; i < 2; i++) |
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s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); |
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/* GPM1[5:2]: HW_REV[3:0] */ |
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for (i = 2; i < 6; i++) { |
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s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); |
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s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE); |
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} |
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/* GPM1[1:0]: MODEL_REV[1:0] */ |
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for (i = 0; i < 2; i++) |
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modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i); |
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/* board_rev[15:8] = model */ |
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board_rev = modelrev << 8; |
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} |
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#ifdef CONFIG_DISPLAY_BOARDINFO |
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int checkboard(void) |
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{ |
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puts("Board:\tTRATS2\n"); |
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return 0; |
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} |
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#endif |
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static void show_hw_revision(void) |
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{ |
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printf("HW Revision:\t0x%04x\n", board_rev); |
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} |
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u32 get_board_rev(void) |
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{ |
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return board_rev; |
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} |
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static inline u32 get_model_rev(void) |
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{ |
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return (board_rev >> 8) & 0xff; |
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} |
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static void board_external_gpio_init(void) |
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{ |
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gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; |
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/*
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* some pins which in alive block are connected with external pull-up |
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* but it's default setting is pull-down. |
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* if that pin set as input then that floated |
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*/ |
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s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */ |
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s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */ |
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s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/ |
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s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/ |
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s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */ |
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s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */ |
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s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */ |
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s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */ |
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s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */ |
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s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */ |
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s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */ |
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s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */ |
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} |
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#ifdef CONFIG_SYS_I2C_INIT_BOARD |
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static void board_init_i2c(void) |
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{ |
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gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE; |
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gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; |
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/* I2C_7 */ |
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s5p_gpio_direction_output(&gpio1->d0, 2, 1); |
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s5p_gpio_direction_output(&gpio1->d0, 3, 1); |
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/* I2C_8 */ |
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s5p_gpio_direction_output(&gpio1->f1, 4, 1); |
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s5p_gpio_direction_output(&gpio1->f1, 5, 1); |
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/* I2C_9 */ |
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s5p_gpio_direction_output(&gpio2->m2, 1, 1); |
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s5p_gpio_direction_output(&gpio2->m2, 0, 1); |
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} |
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#endif |
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int board_early_init_f(void) |
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{ |
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check_hw_revision(); |
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board_external_gpio_init(); |
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gd->flags |= GD_FLG_DISABLE_CONSOLE; |
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return 0; |
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} |
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static int pmic_init_max77686(void); |
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int board_init(void) |
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{ |
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struct exynos4_power *pwr = |
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(struct exynos4_power *)EXYNOS4X12_POWER_BASE; |
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
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/* workaround: clear INFORM4..5 */ |
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writel(0, (unsigned int)&pwr->inform4); |
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writel(0, (unsigned int)&pwr->inform5); |
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return 0; |
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} |
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int power_init_board(void) |
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{ |
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int chrg; |
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struct power_battery *pb; |
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struct pmic *p_chrg, *p_muic, *p_fg, *p_bat; |
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#ifdef CONFIG_SYS_I2C_INIT_BOARD |
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board_init_i2c(); |
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#endif |
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pmic_init(I2C_0); /* I2C adapter 0 - bus name I2C_5 */ |
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pmic_init_max77686(); |
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pmic_init_max77693(I2C_2); /* I2C adapter 2 - bus name I2C_10 */ |
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power_muic_init(I2C_2); /* I2C adapter 2 - bus name I2C_10 */ |
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power_fg_init(I2C_1); /* I2C adapter 1 - bus name I2C_9 */ |
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power_bat_init(0); |
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p_chrg = pmic_get("MAX77693_PMIC"); |
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if (!p_chrg) { |
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puts("MAX77693_PMIC: Not found\n"); |
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return -ENODEV; |
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} |
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p_muic = pmic_get("MAX77693_MUIC"); |
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if (!p_muic) { |
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puts("MAX77693_MUIC: Not found\n"); |
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return -ENODEV; |
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} |
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p_fg = pmic_get("MAX77693_FG"); |
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if (!p_fg) { |
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puts("MAX17042_FG: Not found\n"); |
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return -ENODEV; |
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} |
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if (p_chrg->chrg->chrg_bat_present(p_chrg) == 0) |
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puts("No battery detected\n"); |
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p_bat = pmic_get("BAT_TRATS2"); |
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if (!p_bat) { |
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puts("BAT_TRATS2: Not found\n"); |
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return -ENODEV; |
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} |
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p_fg->parent = p_bat; |
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p_chrg->parent = p_bat; |
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p_muic->parent = p_bat; |
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p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); |
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pb = p_bat->pbat; |
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chrg = p_muic->chrg->chrg_type(p_muic); |
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debug("CHARGER TYPE: %d\n", chrg); |
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if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { |
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puts("No battery detected\n"); |
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return -1; |
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} |
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p_fg->fg->fg_battery_check(p_fg, p_bat); |
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if (pb->bat->state == CHARGE && chrg == CHARGER_USB) |
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puts("CHARGE Battery !\n"); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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u32 size_mb; |
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size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + |
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get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + |
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get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + |
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get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20; |
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gd->ram_size = size_mb << 20; |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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int err0, err2 = 0; |
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gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; |
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/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ |
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s5p_gpio_direction_output(&gpio2->k0, 2, 1); |
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s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE); |
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/*
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* eMMC GPIO: |
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* SDR 8-bit@48MHz at MMC0 |
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* GPK0[0] SD_0_CLK(2) |
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* GPK0[1] SD_0_CMD(2) |
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* GPK0[2] SD_0_CDn -> Not used |
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* GPK0[3:6] SD_0_DATA[0:3](2) |
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* GPK1[3:6] SD_0_DATA[0:3](3) |
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* |
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* DDR 4-bit@26MHz at MMC4 |
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* GPK0[0] SD_4_CLK(3) |
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* GPK0[1] SD_4_CMD(3) |
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* GPK0[2] SD_4_CDn -> Not used |
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* GPK0[3:6] SD_4_DATA[0:3](3) |
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* GPK1[3:6] SD_4_DATA[4:7](4) |
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*/ |
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err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); |
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/*
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* MMC device init |
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* mmc0 : eMMC (8-bit buswidth) |
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* mmc2 : SD card (4-bit buswidth) |
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*/ |
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if (err0) |
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debug("SDMMC0 not configured\n"); |
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else |
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err0 = s5p_mmc_init(0, 8); |
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/* T-flash detect */ |
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s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); |
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s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); |
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/*
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* Check the T-flash detect pin |
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* GPX3[4] T-flash detect pin |
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*/ |
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if (!s5p_gpio_get_value(&gpio2->x3, 4)) { |
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err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); |
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if (err2) |
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debug("SDMMC2 not configured\n"); |
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else |
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err2 = s5p_mmc_init(2, 4); |
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} |
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return err0 & err2; |
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} |
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static int pmic_init_max77686(void) |
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{ |
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struct pmic *p = pmic_get("MAX77686_PMIC"); |
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if (pmic_probe(p)) |
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return -1; |
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/* BUCK/LDO Output Voltage */ |
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max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 VTF_2.8V */ |
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max77686_set_ldo_voltage(p, 23, 3300000); /* LDO23 TSP_AVDD_3.3V*/ |
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max77686_set_ldo_voltage(p, 24, 1800000); /* LDO24 TSP_VDD_1.8V */ |
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/* BUCK/LDO Output Mode */ |
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max77686_set_buck_mode(p, 1, OPMODE_STANDBY); /* BUCK1 VMIF_1.1V_AP */ |
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max77686_set_buck_mode(p, 2, OPMODE_ON); /* BUCK2 VARM_1.0V_AP */ |
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max77686_set_buck_mode(p, 3, OPMODE_ON); /* BUCK3 VINT_1.0V_AP */ |
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max77686_set_buck_mode(p, 4, OPMODE_ON); /* BUCK4 VG3D_1.0V_AP */ |
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max77686_set_buck_mode(p, 5, OPMODE_ON); /* BUCK5 VMEM_1.2V_AP */ |
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max77686_set_buck_mode(p, 6, OPMODE_ON); /* BUCK6 VCC_SUB_1.35V*/ |
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max77686_set_buck_mode(p, 7, OPMODE_ON); /* BUCK7 VCC_SUB_2.0V */ |
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max77686_set_buck_mode(p, 8, OPMODE_OFF); /* VMEM_VDDF_2.85V */ |
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max77686_set_buck_mode(p, 9, OPMODE_OFF); /* CAM_ISP_CORE_1.2V*/ |
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max77686_set_ldo_mode(p, 1, OPMODE_LPM); /* LDO1 VALIVE_1.0V_AP*/ |
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max77686_set_ldo_mode(p, 2, OPMODE_STANDBY); /* LDO2 VM1M2_1.2V_AP */ |
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max77686_set_ldo_mode(p, 3, OPMODE_LPM); /* LDO3 VCC_1.8V_AP */ |
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max77686_set_ldo_mode(p, 4, OPMODE_LPM); /* LDO4 VCC_2.8V_AP */ |
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max77686_set_ldo_mode(p, 5, OPMODE_OFF); /* LDO5_VCC_1.8V_IO */ |
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max77686_set_ldo_mode(p, 6, OPMODE_STANDBY); /* LDO6 VMPLL_1.0V_AP */ |
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max77686_set_ldo_mode(p, 7, OPMODE_STANDBY); /* LDO7 VPLL_1.0V_AP */ |
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max77686_set_ldo_mode(p, 8, OPMODE_LPM); /* LDO8 VMIPI_1.0V_AP */ |
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max77686_set_ldo_mode(p, 9, OPMODE_OFF); /* CAM_ISP_MIPI_1.2*/ |
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max77686_set_ldo_mode(p, 10, OPMODE_LPM); /* LDO10 VMIPI_1.8V_AP*/ |
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max77686_set_ldo_mode(p, 11, OPMODE_STANDBY); /* LDO11 VABB1_1.8V_AP*/ |
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max77686_set_ldo_mode(p, 12, OPMODE_LPM); /* LDO12 VUOTG_3.0V_AP*/ |
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max77686_set_ldo_mode(p, 13, OPMODE_OFF); /* LDO13 VC2C_1.8V_AP */ |
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max77686_set_ldo_mode(p, 14, OPMODE_STANDBY); /* VABB02_1.8V_AP */ |
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max77686_set_ldo_mode(p, 15, OPMODE_STANDBY); /* LDO15 VHSIC_1.0V_AP*/ |
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max77686_set_ldo_mode(p, 16, OPMODE_STANDBY); /* LDO16 VHSIC_1.8V_AP*/ |
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max77686_set_ldo_mode(p, 17, OPMODE_OFF); /* CAM_SENSOR_CORE_1.2*/ |
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max77686_set_ldo_mode(p, 18, OPMODE_OFF); /* CAM_ISP_SEN_IO_1.8V*/ |
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max77686_set_ldo_mode(p, 19, OPMODE_OFF); /* LDO19 VT_CAM_1.8V */ |
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max77686_set_ldo_mode(p, 20, OPMODE_ON); /* LDO20 VDDQ_PRE_1.8V*/ |
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max77686_set_ldo_mode(p, 21, OPMODE_OFF); /* LDO21 VTF_2.8V */ |
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max77686_set_ldo_mode(p, 22, OPMODE_OFF); /* LDO22 VMEM_VDD_2.8V*/ |
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max77686_set_ldo_mode(p, 23, OPMODE_OFF); /* LDO23 TSP_AVDD_3.3V*/ |
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max77686_set_ldo_mode(p, 24, OPMODE_OFF); /* LDO24 TSP_VDD_1.8V */ |
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max77686_set_ldo_mode(p, 25, OPMODE_OFF); /* LDO25 VCC_3.3V_LCD */ |
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max77686_set_ldo_mode(p, 26, OPMODE_OFF); /*LDO26 VCC_3.0V_MOTOR*/ |
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return 0; |
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} |
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/*
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* LCD |
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*/ |
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#ifdef CONFIG_LCD |
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static struct mipi_dsim_config dsim_config = { |
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.e_interface = DSIM_VIDEO, |
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.e_virtual_ch = DSIM_VIRTUAL_CH_0, |
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.e_pixel_format = DSIM_24BPP_888, |
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.e_burst_mode = DSIM_BURST_SYNC_EVENT, |
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.e_no_data_lane = DSIM_DATA_LANE_4, |
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.e_byte_clk = DSIM_PLL_OUT_DIV8, |
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.hfp = 1, |
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.p = 3, |
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.m = 120, |
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.s = 1, |
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/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ |
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.pll_stable_time = 500, |
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/* escape clk : 10MHz */ |
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.esc_clk = 20 * 1000000, |
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/* stop state holding counter after bta change count 0 ~ 0xfff */ |
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.stop_holding_cnt = 0x7ff, |
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/* bta timeout 0 ~ 0xff */ |
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.bta_timeout = 0xff, |
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/* lp rx timeout 0 ~ 0xffff */ |
||||
.rx_timeout = 0xffff, |
||||
}; |
||||
|
||||
static struct exynos_platform_mipi_dsim dsim_platform_data = { |
||||
.lcd_panel_info = NULL, |
||||
.dsim_config = &dsim_config, |
||||
}; |
||||
|
||||
static struct mipi_dsim_lcd_device mipi_lcd_device = { |
||||
.name = "s6e8ax0", |
||||
.id = -1, |
||||
.bus_id = 0, |
||||
.platform_data = (void *)&dsim_platform_data, |
||||
}; |
||||
|
||||
static int mipi_power(void) |
||||
{ |
||||
struct pmic *p = pmic_get("MAX77686_PMIC"); |
||||
|
||||
/* LDO8 VMIPI_1.0V_AP */ |
||||
max77686_set_ldo_mode(p, 8, OPMODE_ON); |
||||
/* LDO10 VMIPI_1.8V_AP */ |
||||
max77686_set_ldo_mode(p, 10, OPMODE_ON); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void exynos_lcd_power_on(void) |
||||
{ |
||||
struct pmic *p = pmic_get("MAX77686_PMIC"); |
||||
|
||||
gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE; |
||||
|
||||
/* LCD_2.2V_EN: GPC0[1] */ |
||||
s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP); |
||||
s5p_gpio_direction_output(&gpio1->c0, 1, 1); |
||||
|
||||
/* LDO25 VCC_3.1V_LCD */ |
||||
pmic_probe(p); |
||||
max77686_set_ldo_voltage(p, 25, 3100000); |
||||
max77686_set_ldo_mode(p, 25, OPMODE_LPM); |
||||
} |
||||
|
||||
void exynos_reset_lcd(void) |
||||
{ |
||||
gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE; |
||||
|
||||
/* reset lcd */ |
||||
s5p_gpio_direction_output(&gpio1->f2, 1, 0); |
||||
udelay(10); |
||||
s5p_gpio_set_value(&gpio1->f2, 1, 1); |
||||
} |
||||
|
||||
vidinfo_t panel_info = { |
||||
.vl_freq = 60, |
||||
.vl_col = 720, |
||||
.vl_row = 1280, |
||||
.vl_width = 720, |
||||
.vl_height = 1280, |
||||
.vl_clkp = CONFIG_SYS_HIGH, |
||||
.vl_hsp = CONFIG_SYS_LOW, |
||||
.vl_vsp = CONFIG_SYS_LOW, |
||||
.vl_dp = CONFIG_SYS_LOW, |
||||
.vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ |
||||
|
||||
/* s6e8ax0 Panel infomation */ |
||||
.vl_hspw = 5, |
||||
.vl_hbpd = 10, |
||||
.vl_hfpd = 10, |
||||
|
||||
.vl_vspw = 2, |
||||
.vl_vbpd = 1, |
||||
.vl_vfpd = 13, |
||||
.vl_cmd_allow_len = 0xf, |
||||
.mipi_enabled = 1, |
||||
|
||||
.dual_lcd_enabled = 0, |
||||
|
||||
.init_delay = 0, |
||||
.power_on_delay = 25, |
||||
.reset_delay = 0, |
||||
.interface_mode = FIMD_RGB_INTERFACE, |
||||
}; |
||||
|
||||
void init_panel_info(vidinfo_t *vid) |
||||
{ |
||||
vid->logo_on = 1; |
||||
vid->resolution = HD_RESOLUTION; |
||||
vid->rgb_mode = MODE_RGB_P; |
||||
|
||||
vid->power_on_delay = 30; |
||||
|
||||
mipi_lcd_device.reverse_panel = 1; |
||||
|
||||
#ifdef CONFIG_TIZEN |
||||
get_tizen_logo_info(vid); |
||||
#endif |
||||
|
||||
strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name); |
||||
dsim_platform_data.mipi_power = mipi_power; |
||||
dsim_platform_data.phy_enable = set_mipi_phy_ctrl; |
||||
dsim_platform_data.lcd_panel_info = (void *)vid; |
||||
exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); |
||||
|
||||
s6e8ax0_init(); |
||||
|
||||
exynos_set_dsim_platform_data(&dsim_platform_data); |
||||
} |
||||
#endif /* LCD */ |
||||
|
||||
#ifdef CONFIG_MISC_INIT_R |
||||
int misc_init_r(void) |
||||
{ |
||||
setenv("model", "GT-I8800"); |
||||
setenv("board", "TRATS2"); |
||||
|
||||
show_hw_revision(); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,311 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Samsung Electronics |
||||
* Sanghee Kim <sh0130.kim@samsung.com> |
||||
* Piotr Wilczek <p.wilczek@samsung.com> |
||||
* |
||||
* Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */ |
||||
#define CONFIG_S5P /* which is in a S5P Family */ |
||||
#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */ |
||||
#define CONFIG_TIZEN /* TIZEN lib */ |
||||
|
||||
#define PLATFORM_NO_UNALIGNED |
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */ |
||||
|
||||
#define CONFIG_ARCH_CPU_INIT |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 |
||||
|
||||
#ifndef CONFIG_SYS_L2CACHE_OFF |
||||
#define CONFIG_SYS_L2_PL310 |
||||
#define CONFIG_SYS_PL310_BASE 0x10502000 |
||||
#endif |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 4 |
||||
#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */ |
||||
#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */ |
||||
#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ |
||||
#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */ |
||||
#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */ |
||||
#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */ |
||||
#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */ |
||||
#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */ |
||||
#define PHYS_SDRAM_END 0x80000000 |
||||
|
||||
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) |
||||
#define CONFIG_SYS_TEXT_BASE 0x78100000 |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 24000000 |
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
|
||||
/* MACH_TYPE_TRATS2 */ |
||||
#define MACH_TYPE_TRATS2 3765 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_TRATS2 |
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20)) |
||||
|
||||
/* select serial console configuration */ |
||||
#define CONFIG_SERIAL2 |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* It should define before config_cmd_default.h */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/***********************************************************
|
||||
* Command definition |
||||
***********************************************************/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#undef CONFIG_CMD_ECHO |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
#undef CONFIG_CMD_NAND |
||||
#undef CONFIG_CMD_MISC |
||||
#undef CONFIG_CMD_NFS |
||||
#undef CONFIG_CMD_SOURCE |
||||
#undef CONFIG_CMD_XIMG |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_GPT |
||||
#define CONFIG_CMD_PMIC |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK |
||||
|
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_FAT_WRITE |
||||
|
||||
/* EXT4 */ |
||||
#define CONFIG_CMD_EXT4 |
||||
#define CONFIG_CMD_EXT4_WRITE |
||||
|
||||
/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */ |
||||
#undef CONFIG_CMD_NET |
||||
|
||||
/* MMC */ |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_MMC |
||||
#define CONFIG_S5P_SDHCI |
||||
#define CONFIG_SDHCI |
||||
#define CONFIG_MMC_SDMA |
||||
#define CONFIG_MMC_DEFAULT_DEV 0 |
||||
|
||||
/* PWM */ |
||||
#define CONFIG_PWM |
||||
|
||||
#define CONFIG_BOOTARGS "Please use defined boot" |
||||
#define CONFIG_BOOTCOMMAND "run mmcboot" |
||||
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
|
||||
/* Tizen - partitions definitions */ |
||||
#define PARTS_CSA "csa-mmc" |
||||
#define PARTS_BOOTLOADER "u-boot" |
||||
#define PARTS_BOOT "boot" |
||||
#define PARTS_ROOT "platform" |
||||
#define PARTS_DATA "data" |
||||
#define PARTS_CSC "csc" |
||||
#define PARTS_UMS "ums" |
||||
|
||||
#define PARTS_DEFAULT \ |
||||
"uuid_disk=${uuid_gpt_disk};" \
|
||||
"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
|
||||
"name="PARTS_BOOTLOADER",size=60MiB," \
|
||||
"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
|
||||
"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
|
||||
"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
|
||||
"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
|
||||
"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
|
||||
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"bootk=" \
|
||||
"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
|
||||
"updatemmc=" \
|
||||
"mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
|
||||
"mmc boot 0 1 1 0\0" \
|
||||
"updatebackup=" \
|
||||
"mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \
|
||||
" mmc boot 0 1 1 0\0" \
|
||||
"updatebootb=" \
|
||||
"mmc read 0x51000000 0x80 0x200; run updatebackup\0" \
|
||||
"updateuboot=" \
|
||||
"mmc write 0x50000000 0x80 0x400\0" \
|
||||
"mmcboot=" \
|
||||
"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
|
||||
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
|
||||
"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
|
||||
"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
|
||||
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
|
||||
"verify=n\0" \
|
||||
"rootfstype=ext4\0" \
|
||||
"console=" CONFIG_DEFAULT_CONSOLE \
|
||||
"kernelname=uImage\0" \
|
||||
"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
|
||||
"0x40007FC0 ${kernelname}\0" \
|
||||
"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
|
||||
"${fdtfile}\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcbootpart=2\0" \
|
||||
"mmcrootpart=5\0" \
|
||||
"opts=always_resume=1\0" \
|
||||
"partitions=" PARTS_DEFAULT \
|
||||
"uartpath=ap\0" \
|
||||
"usbpath=ap\0" \
|
||||
"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
|
||||
"consoleoff=set console console=ram; save; reset\0" \
|
||||
"spladdr=0x40000100\0" \
|
||||
"splsize=0x200\0" \
|
||||
"splfile=falcon.bin\0" \
|
||||
"spl_export=" \
|
||||
"setexpr spl_imgsize ${splsize} + 8 ;" \
|
||||
"setenv spl_imgsize 0x${spl_imgsize};" \
|
||||
"setexpr spl_imgaddr ${spladdr} - 8 ;" \
|
||||
"setexpr spl_addr_tmp ${spladdr} - 4 ;" \
|
||||
"mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
|
||||
"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
|
||||
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
|
||||
"spl export atags 0x40007FC0;" \
|
||||
"crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
|
||||
"mw.l ${spl_addr_tmp} ${splsize};" \
|
||||
"ext4write mmc ${mmcdev}:${mmcbootpart}" \
|
||||
" /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
|
||||
"setenv spl_imgsize;" \
|
||||
"setenv spl_imgaddr;" \
|
||||
"setenv spl_addr_tmp;\0" \
|
||||
"fdtaddr=40800000\0" \
|
||||
"fdtfile=exynos4412-trats2.dtb\0" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
||||
|
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) |
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) |
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ |
||||
- GENERATED_GBL_DATA_SIZE) |
||||
|
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/* valid baudrates */ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV |
||||
#define CONFIG_ENV_SIZE 4096 |
||||
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ |
||||
#define CONFIG_EFI_PARTITION |
||||
#define CONFIG_PARTITION_UUIDS |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
/* I2C */ |
||||
#include <asm/arch/gpio.h> |
||||
|
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 |
||||
#define I2C_SOFT_DECLARATIONS2 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00 |
||||
#define I2C_SOFT_DECLARATIONS3 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x00 |
||||
#define CONFIG_SOFT_I2C_READ_REPEATED_START |
||||
#define CONFIG_SYS_I2C_INIT_BOARD |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_SOFT_I2C_MULTI_BUS |
||||
#define CONFIG_SYS_MAX_I2C_BUS 15 |
||||
|
||||
#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3) |
||||
#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2) |
||||
#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4) |
||||
#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5) |
||||
#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1) |
||||
#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0) |
||||
#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin() |
||||
#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin() |
||||
#define I2C_INIT multi_i2c_init() |
||||
|
||||
/* POWER */ |
||||
#define CONFIG_POWER |
||||
#define CONFIG_POWER_I2C |
||||
#define CONFIG_POWER_MAX77686 |
||||
#define CONFIG_POWER_PMIC_MAX77693 |
||||
#define CONFIG_POWER_MUIC_MAX77693 |
||||
#define CONFIG_POWER_FG_MAX77693 |
||||
#define CONFIG_POWER_BATTERY_TRATS2 |
||||
|
||||
/* LCD */ |
||||
#define CONFIG_EXYNOS_FB |
||||
#define CONFIG_LCD |
||||
#define CONFIG_CMD_BMP |
||||
#define CONFIG_BMP_32BPP |
||||
#define CONFIG_FB_ADDR 0x52504000 |
||||
#define CONFIG_S6E8AX0 |
||||
#define CONFIG_EXYNOS_MIPI_DSIM |
||||
#define CONFIG_VIDEO_BMP_GZIP |
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12)) |
||||
|
||||
/* Pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue