Tom Rini
9 years ago
commit
4ed6ed3c27
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,6 @@ |
||||
XILINX_ZYNQMP_EP BOARD |
||||
XILINX_ZYNQMP BOARDS |
||||
M: Michal Simek <michal.simek@xilinx.com> |
||||
S: Maintained |
||||
F: board/xilinx/zynqmp/ |
||||
F: include/configs/xilinx_zynqmp.h |
||||
F: include/configs/xilinx_zynqmp_ep.h |
||||
F: configs/xilinx_zynqmp_ep_defconfig |
||||
F: include/configs/xilinx_zynqmp* |
||||
F: configs/xilinx_zynqmp* |
||||
|
||||
@ -0,0 +1,113 @@ |
||||
/*
|
||||
* (C) Copyright 2015 - 2016 Xilinx, Inc. |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#include <common.h> |
||||
#include <netdev.h> |
||||
#include <ahci.h> |
||||
#include <scsi.h> |
||||
#include <asm/arch/hardware.h> |
||||
|
||||
#include <asm/io.h> |
||||
|
||||
/* Vendor Specific Register Offsets */ |
||||
#define AHCI_VEND_PCFG 0xA4 |
||||
#define AHCI_VEND_PPCFG 0xA8 |
||||
#define AHCI_VEND_PP2C 0xAC |
||||
#define AHCI_VEND_PP3C 0xB0 |
||||
#define AHCI_VEND_PP4C 0xB4 |
||||
#define AHCI_VEND_PP5C 0xB8 |
||||
#define AHCI_VEND_PAXIC 0xC0 |
||||
#define AHCI_VEND_PTC 0xC8 |
||||
|
||||
/* Vendor Specific Register bit definitions */ |
||||
#define PAXIC_ADBW_BW64 0x1 |
||||
#define PAXIC_MAWIDD (1 << 8) |
||||
#define PAXIC_MARIDD (1 << 16) |
||||
#define PAXIC_OTL (0x4 << 20) |
||||
|
||||
#define PCFG_TPSS_VAL (0x32 << 16) |
||||
#define PCFG_TPRS_VAL (0x2 << 12) |
||||
#define PCFG_PAD_VAL 0x2 |
||||
|
||||
#define PPCFG_TTA 0x1FFFE |
||||
#define PPCFG_PSSO_EN (1 << 28) |
||||
#define PPCFG_PSS_EN (1 << 29) |
||||
#define PPCFG_ESDF_EN (1 << 31) |
||||
|
||||
#define PP2C_CIBGMN 0x0F |
||||
#define PP2C_CIBGMX (0x25 << 8) |
||||
#define PP2C_CIBGN (0x18 << 16) |
||||
#define PP2C_CINMP (0x29 << 24) |
||||
|
||||
#define PP3C_CWBGMN 0x04 |
||||
#define PP3C_CWBGMX (0x0B << 8) |
||||
#define PP3C_CWBGN (0x08 << 16) |
||||
#define PP3C_CWNMP (0x0F << 24) |
||||
|
||||
#define PP4C_BMX 0x0a |
||||
#define PP4C_BNM (0x08 << 8) |
||||
#define PP4C_SFD (0x4a << 16) |
||||
#define PP4C_PTST (0x06 << 24) |
||||
|
||||
#define PP5C_RIT 0x60216 |
||||
#define PP5C_RCT (0x7f0 << 20) |
||||
|
||||
#define PTC_RX_WM_VAL 0x40 |
||||
#define PTC_RSVD (1 << 27) |
||||
|
||||
#define PORT0_BASE 0x100 |
||||
#define PORT1_BASE 0x180 |
||||
|
||||
/* Port Control Register Bit Definitions */ |
||||
#define PORT_SCTL_SPD_GEN3 (0x3 << 4) |
||||
#define PORT_SCTL_SPD_GEN2 (0x2 << 4) |
||||
#define PORT_SCTL_SPD_GEN1 (0x1 << 4) |
||||
#define PORT_SCTL_IPM (0x3 << 8) |
||||
|
||||
#define PORT_BASE 0x100 |
||||
#define PORT_OFFSET 0x80 |
||||
#define NR_PORTS 2 |
||||
#define DRV_NAME "ahci-ceva" |
||||
#define CEVA_FLAG_BROKEN_GEN2 1 |
||||
|
||||
int init_sata(int dev) |
||||
{ |
||||
ulong tmp; |
||||
ulong mmio = ZYNQMP_SATA_BASEADDR; |
||||
int i; |
||||
|
||||
/*
|
||||
* AXI Data bus width to 64 |
||||
* Set Mem Addr Read, Write ID for data transfers |
||||
* Transfer limit to 72 DWord |
||||
*/ |
||||
tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL; |
||||
writel(tmp, mmio + AHCI_VEND_PAXIC); |
||||
|
||||
/* Set AHCI Enable */ |
||||
tmp = readl(mmio + HOST_CTL); |
||||
tmp |= HOST_AHCI_EN; |
||||
writel(tmp, mmio + HOST_CTL); |
||||
|
||||
for (i = 0; i < NR_PORTS; i++) { |
||||
/* TPSS TPRS scalars, CISE and Port Addr */ |
||||
tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); |
||||
writel(tmp, mmio + AHCI_VEND_PCFG); |
||||
|
||||
/* Port Phy Cfg register enables */ |
||||
tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN; |
||||
writel(tmp, mmio + AHCI_VEND_PPCFG); |
||||
|
||||
/* Rx Watermark setting */ |
||||
tmp = PTC_RX_WM_VAL | PTC_RSVD; |
||||
writel(tmp, mmio + AHCI_VEND_PTC); |
||||
|
||||
/* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */ |
||||
tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM; |
||||
writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); |
||||
} |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,144 @@ |
||||
/*
|
||||
* Xilinx PCS/PMA Core phy driver |
||||
* |
||||
* Copyright (C) 2015 - 2016 Xilinx, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <phy.h> |
||||
#include <dm.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define MII_PHY_STATUS_SPD_MASK 0x0C00 |
||||
#define MII_PHY_STATUS_FULLDUPLEX 0x1000 |
||||
#define MII_PHY_STATUS_1000 0x0800 |
||||
#define MII_PHY_STATUS_100 0x0400 |
||||
#define XPCSPMA_PHY_CTRL_ISOLATE_DISABLE 0xFBFF |
||||
|
||||
/* Mask used for ID comparisons */ |
||||
#define XILINX_PHY_ID_MASK 0xfffffff0 |
||||
|
||||
/* Known PHY IDs */ |
||||
#define XILINX_PHY_ID 0x01740c00 |
||||
|
||||
/* struct phy_device dev_flags definitions */ |
||||
#define XAE_PHY_TYPE_MII 0 |
||||
#define XAE_PHY_TYPE_GMII 1 |
||||
#define XAE_PHY_TYPE_RGMII_1_3 2 |
||||
#define XAE_PHY_TYPE_RGMII_2_0 3 |
||||
#define XAE_PHY_TYPE_SGMII 4 |
||||
#define XAE_PHY_TYPE_1000BASE_X 5 |
||||
|
||||
static int xilinxphy_startup(struct phy_device *phydev) |
||||
{ |
||||
int err; |
||||
int status = 0; |
||||
|
||||
debug("%s\n", __func__); |
||||
/* Update the link, but return if there
|
||||
* was an error |
||||
*/ |
||||
err = genphy_update_link(phydev); |
||||
if (err) |
||||
return err; |
||||
|
||||
if (AUTONEG_ENABLE == phydev->autoneg) { |
||||
status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); |
||||
status = status & MII_PHY_STATUS_SPD_MASK; |
||||
|
||||
if (status & MII_PHY_STATUS_FULLDUPLEX) |
||||
phydev->duplex = DUPLEX_FULL; |
||||
else |
||||
phydev->duplex = DUPLEX_HALF; |
||||
|
||||
switch (status) { |
||||
case MII_PHY_STATUS_1000: |
||||
phydev->speed = SPEED_1000; |
||||
break; |
||||
|
||||
case MII_PHY_STATUS_100: |
||||
phydev->speed = SPEED_100; |
||||
break; |
||||
|
||||
default: |
||||
phydev->speed = SPEED_10; |
||||
break; |
||||
} |
||||
} else { |
||||
int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); |
||||
|
||||
if (bmcr < 0) |
||||
return bmcr; |
||||
|
||||
if (bmcr & BMCR_FULLDPLX) |
||||
phydev->duplex = DUPLEX_FULL; |
||||
else |
||||
phydev->duplex = DUPLEX_HALF; |
||||
|
||||
if (bmcr & BMCR_SPEED1000) |
||||
phydev->speed = SPEED_1000; |
||||
else if (bmcr & BMCR_SPEED100) |
||||
phydev->speed = SPEED_100; |
||||
else |
||||
phydev->speed = SPEED_10; |
||||
} |
||||
|
||||
/*
|
||||
* For 1000BASE-X Phy Mode the speed/duplex will always be |
||||
* 1000Mbps/fullduplex |
||||
*/ |
||||
if (phydev->flags == XAE_PHY_TYPE_1000BASE_X) { |
||||
phydev->duplex = DUPLEX_FULL; |
||||
phydev->speed = SPEED_1000; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int xilinxphy_of_init(struct phy_device *phydev) |
||||
{ |
||||
struct udevice *dev = (struct udevice *)&phydev->dev; |
||||
u32 phytype; |
||||
|
||||
debug("%s\n", __func__); |
||||
phytype = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "phy-type", -1); |
||||
if (phytype == XAE_PHY_TYPE_1000BASE_X) |
||||
phydev->flags |= XAE_PHY_TYPE_1000BASE_X; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int xilinxphy_config(struct phy_device *phydev) |
||||
{ |
||||
int temp; |
||||
|
||||
debug("%s\n", __func__); |
||||
xilinxphy_of_init(phydev); |
||||
temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); |
||||
temp &= XPCSPMA_PHY_CTRL_ISOLATE_DISABLE; |
||||
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct phy_driver xilinxphy_driver = { |
||||
.uid = XILINX_PHY_ID, |
||||
.mask = XILINX_PHY_ID_MASK, |
||||
.name = "Xilinx PCS/PMA PHY", |
||||
.features = PHY_GBIT_FEATURES, |
||||
.config = &xilinxphy_config, |
||||
.startup = &xilinxphy_startup, |
||||
.shutdown = &genphy_shutdown, |
||||
}; |
||||
|
||||
int phy_xilinx_init(void) |
||||
{ |
||||
debug("%s\n", __func__); |
||||
phy_register(&xilinxphy_driver); |
||||
|
||||
return 0; |
||||
} |
||||
Loading…
Reference in new issue