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@ -1,5 +1,5 @@ |
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/*
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* Memory Setup stuff - taken from blob memsetup.S |
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* Copyright (C) 2013 Bo Shen <voice.shen@atmel.com> |
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* |
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* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) |
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* |
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@ -8,16 +8,6 @@ |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* WARNING: |
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* |
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* As the code is right now, it expects all PIO ports A,B,C,... |
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* to be evenly spaced in the memory map: |
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* ATMEL_BASE_PIOA + port * sizeof at91pio_t |
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* This might not necessaryly be true in future Atmel SoCs. |
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* This code should be fixed to use a pointer array to the ports. |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <asm/io.h> |
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@ -25,19 +15,42 @@ |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/at91_pio.h> |
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static struct at91_port *at91_pio_get_port(unsigned port) |
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{ |
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switch (port) { |
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case AT91_PIO_PORTA: |
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return (struct at91_port *)ATMEL_BASE_PIOA; |
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case AT91_PIO_PORTB: |
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return (struct at91_port *)ATMEL_BASE_PIOB; |
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case AT91_PIO_PORTC: |
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return (struct at91_port *)ATMEL_BASE_PIOC; |
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#if (ATMEL_PIO_PORTS > 3) |
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case AT91_PIO_PORTD: |
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return (struct at91_port *)ATMEL_BASE_PIOD; |
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#if (ATMEL_PIO_PORTS > 4) |
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case AT91_PIO_PORTE: |
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return (struct at91_port *)ATMEL_BASE_PIOE; |
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#endif |
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#endif |
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default: |
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return NULL; |
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} |
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} |
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int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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if (use_pullup) |
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writel(1 << pin, &pio->port[port].puer); |
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writel(1 << pin, &at91_port->puer); |
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else |
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writel(1 << pin, &pio->port[port].pudr); |
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writel(mask, &pio->port[port].per); |
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writel(1 << pin, &at91_port->pudr); |
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writel(mask, &at91_port->per); |
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} |
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return 0; |
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} |
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@ -46,15 +59,16 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) |
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*/ |
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int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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writel(mask, &pio->port[port].idr); |
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writel(mask, &at91_port->idr); |
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at91_set_pio_pullup(port, pin, use_pullup); |
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writel(mask, &pio->port[port].per); |
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writel(mask, &at91_port->per); |
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} |
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return 0; |
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} |
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@ -63,23 +77,24 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) |
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*/ |
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int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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writel(mask, &pio->port[port].idr); |
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writel(mask, &at91_port->idr); |
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at91_set_pio_pullup(port, pin, use_pullup); |
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#if defined(CPU_HAS_PIO3) |
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writel(readl(&pio->port[port].abcdsr1) & ~mask, |
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&pio->port[port].abcdsr1); |
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writel(readl(&pio->port[port].abcdsr2) & ~mask, |
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&pio->port[port].abcdsr2); |
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writel(readl(&at91_port->abcdsr1) & ~mask, |
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&at91_port->abcdsr1); |
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writel(readl(&at91_port->abcdsr2) & ~mask, |
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&at91_port->abcdsr2); |
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#else |
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writel(mask, &pio->port[port].asr); |
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writel(mask, &at91_port->asr); |
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#endif |
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writel(mask, &pio->port[port].pdr); |
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writel(mask, &at91_port->pdr); |
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} |
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return 0; |
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} |
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@ -88,23 +103,24 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) |
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*/ |
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int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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writel(mask, &pio->port[port].idr); |
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writel(mask, &at91_port->idr); |
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at91_set_pio_pullup(port, pin, use_pullup); |
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#if defined(CPU_HAS_PIO3) |
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writel(readl(&pio->port[port].abcdsr1) | mask, |
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&pio->port[port].abcdsr1); |
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writel(readl(&pio->port[port].abcdsr2) & ~mask, |
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&pio->port[port].abcdsr2); |
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writel(readl(&at91_port->abcdsr1) | mask, |
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&at91_port->abcdsr1); |
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writel(readl(&at91_port->abcdsr2) & ~mask, |
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&at91_port->abcdsr2); |
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#else |
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writel(mask, &pio->port[port].bsr); |
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writel(mask, &at91_port->bsr); |
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#endif |
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writel(mask, &pio->port[port].pdr); |
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writel(mask, &at91_port->pdr); |
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} |
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return 0; |
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} |
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@ -114,19 +130,20 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) |
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*/ |
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int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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writel(mask, &pio->port[port].idr); |
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writel(mask, &at91_port->idr); |
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at91_set_pio_pullup(port, pin, use_pullup); |
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writel(readl(&pio->port[port].abcdsr1) & ~mask, |
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&pio->port[port].abcdsr1); |
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writel(readl(&pio->port[port].abcdsr2) | mask, |
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&pio->port[port].abcdsr2); |
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writel(mask, &pio->port[port].pdr); |
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writel(readl(&at91_port->abcdsr1) & ~mask, |
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&at91_port->abcdsr1); |
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writel(readl(&at91_port->abcdsr2) | mask, |
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&at91_port->abcdsr2); |
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writel(mask, &at91_port->pdr); |
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} |
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return 0; |
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} |
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@ -135,19 +152,20 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) |
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*/ |
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int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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writel(mask, &pio->port[port].idr); |
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writel(mask, &at91_port->idr); |
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at91_set_pio_pullup(port, pin, use_pullup); |
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writel(readl(&pio->port[port].abcdsr1) | mask, |
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&pio->port[port].abcdsr1); |
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writel(readl(&pio->port[port].abcdsr2) | mask, |
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&pio->port[port].abcdsr2); |
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writel(mask, &pio->port[port].pdr); |
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writel(readl(&at91_port->abcdsr1) | mask, |
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&at91_port->abcdsr1); |
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writel(readl(&at91_port->abcdsr2) | mask, |
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&at91_port->abcdsr2); |
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writel(mask, &at91_port->pdr); |
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} |
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return 0; |
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} |
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#endif |
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@ -158,16 +176,17 @@ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) |
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*/ |
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int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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writel(mask, &pio->port[port].idr); |
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writel(mask, &at91_port->idr); |
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at91_set_pio_pullup(port, pin, use_pullup); |
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writel(mask, &pio->port[port].odr); |
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writel(mask, &pio->port[port].per); |
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writel(mask, &at91_port->odr); |
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writel(mask, &at91_port->per); |
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} |
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return 0; |
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} |
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@ -177,20 +196,21 @@ int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) |
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*/ |
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int at91_set_pio_output(unsigned port, u32 pin, int value) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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mask = 1 << pin; |
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writel(mask, &pio->port[port].idr); |
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writel(mask, &pio->port[port].pudr); |
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writel(mask, &at91_port->idr); |
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writel(mask, &at91_port->pudr); |
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if (value) |
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writel(mask, &pio->port[port].sodr); |
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writel(mask, &at91_port->sodr); |
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else |
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writel(mask, &pio->port[port].codr); |
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writel(mask, &pio->port[port].oer); |
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writel(mask, &pio->port[port].per); |
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writel(mask, &at91_port->codr); |
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writel(mask, &at91_port->oer); |
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writel(mask, &at91_port->per); |
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} |
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return 0; |
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} |
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@ -199,20 +219,21 @@ int at91_set_pio_output(unsigned port, u32 pin, int value) |
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*/ |
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int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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if (is_on) { |
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#if defined(CPU_HAS_PIO3) |
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writel(mask, &pio->port[port].ifscdr); |
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writel(mask, &at91_port->ifscdr); |
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#endif |
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writel(mask, &pio->port[port].ifer); |
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writel(mask, &at91_port->ifer); |
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} else { |
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writel(mask, &pio->port[port].ifdr); |
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writel(mask, &at91_port->ifdr); |
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} |
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} |
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return 0; |
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} |
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@ -222,19 +243,20 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) |
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*/ |
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int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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if (is_on) { |
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writel(mask, &pio->port[port].ifscer); |
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writel(div & PIO_SCDR_DIV, &pio->port[port].scdr); |
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writel(mask, &pio->port[port].ifer); |
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writel(mask, &at91_port->ifscer); |
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writel(div & PIO_SCDR_DIV, &at91_port->scdr); |
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writel(mask, &at91_port->ifer); |
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} else { |
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writel(mask, &pio->port[port].ifdr); |
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writel(mask, &at91_port->ifdr); |
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} |
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} |
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return 0; |
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} |
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@ -244,17 +266,18 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) |
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*/ |
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int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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if (at91_port && (pin < 32)) { |
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mask = 1 << pin; |
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writel(mask, &pio->port[port].pudr); |
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writel(mask, &at91_port->pudr); |
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if (is_on) |
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writel(mask, &pio->port[port].ppder); |
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writel(mask, &at91_port->ppder); |
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else |
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writel(mask, &pio->port[port].ppddr); |
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writel(mask, &at91_port->ppddr); |
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} |
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return 0; |
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} |
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@ -263,14 +286,15 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on) |
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*/ |
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int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) |
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{ |
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at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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u32 mask; |
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struct at91_port *at91_port = at91_pio_get_port(port); |
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u32 mask; |
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if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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|
if (at91_port && (pin < 32)) { |
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|
mask = 1 << pin; |
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writel(readl(&pio->port[port].schmitt) | mask, |
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&pio->port[port].schmitt); |
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|
writel(readl(&at91_port->schmitt) | mask, |
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|
&at91_port->schmitt); |
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} |
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return 0; |
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} |
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#endif |
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@ -281,16 +305,17 @@ int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) |
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*/ |
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int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) |
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|
|
{ |
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|
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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|
|
u32 mask; |
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|
|
struct at91_port *at91_port = at91_pio_get_port(port); |
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|
|
u32 mask; |
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|
|
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|
|
|
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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|
|
|
if (at91_port && (pin < 32)) { |
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|
|
mask = 1 << pin; |
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|
|
if (is_on) |
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|
|
writel(mask, &pio->port[port].mder); |
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|
|
writel(mask, &at91_port->mder); |
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|
else |
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|
|
writel(mask, &pio->port[port].mddr); |
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|
|
writel(mask, &at91_port->mddr); |
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|
} |
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return 0; |
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|
|
} |
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|
@ -299,16 +324,17 @@ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) |
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*/ |
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|
int at91_set_pio_value(unsigned port, unsigned pin, int value) |
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|
|
|
{ |
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|
|
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
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|
|
|
u32 mask; |
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|
|
struct at91_port *at91_port = at91_pio_get_port(port); |
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|
|
u32 mask; |
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|
|
|
|
|
|
|
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
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|
|
|
if (at91_port && (pin < 32)) { |
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|
|
mask = 1 << pin; |
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|
|
if (value) |
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|
|
writel(mask, &pio->port[port].sodr); |
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|
|
writel(mask, &at91_port->sodr); |
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|
|
else |
|
|
|
|
writel(mask, &pio->port[port].codr); |
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|
|
writel(mask, &at91_port->codr); |
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|
|
} |
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|
|
return 0; |
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|
|
|
} |
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|
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|
|
@ -317,13 +343,56 @@ int at91_set_pio_value(unsigned port, unsigned pin, int value) |
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|
|
*/ |
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|
|
int at91_get_pio_value(unsigned port, unsigned pin) |
|
|
|
|
{ |
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|
|
|
u32 pdsr = 0; |
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|
|
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
|
|
|
|
u32 mask; |
|
|
|
|
struct at91_port *at91_port = at91_pio_get_port(port); |
|
|
|
|
u32 pdsr = 0, mask; |
|
|
|
|
|
|
|
|
|
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { |
|
|
|
|
if (at91_port && (pin < 32)) { |
|
|
|
|
mask = 1 << pin; |
|
|
|
|
pdsr = readl(&pio->port[port].pdsr) & mask; |
|
|
|
|
pdsr = readl(&at91_port->pdsr) & mask; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
return pdsr != 0; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* Common GPIO API */ |
|
|
|
|
|
|
|
|
|
#define at91_gpio_to_port(gpio) (gpio / 32) |
|
|
|
|
#define at91_gpio_to_pin(gpio) (gpio % 32) |
|
|
|
|
|
|
|
|
|
int gpio_request(unsigned gpio, const char *label) |
|
|
|
|
{ |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
int gpio_free(unsigned gpio) |
|
|
|
|
{ |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
int gpio_direction_input(unsigned gpio) |
|
|
|
|
{ |
|
|
|
|
at91_set_pio_input(at91_gpio_to_port(gpio), |
|
|
|
|
at91_gpio_to_pin(gpio), 0); |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
int gpio_direction_output(unsigned gpio, int value) |
|
|
|
|
{ |
|
|
|
|
at91_set_pio_output(at91_gpio_to_port(gpio), |
|
|
|
|
at91_gpio_to_pin(gpio), value); |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
int gpio_get_value(unsigned gpio) |
|
|
|
|
{ |
|
|
|
|
return at91_get_pio_value(at91_gpio_to_port(gpio), |
|
|
|
|
at91_gpio_to_pin(gpio)); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
int gpio_set_value(unsigned gpio, int value) |
|
|
|
|
{ |
|
|
|
|
at91_set_pio_value(at91_gpio_to_port(gpio), |
|
|
|
|
at91_gpio_to_pin(gpio), value); |
|
|
|
|
|
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|