Kirkwood family controllers are highly integrated SOCs based on Feroceon-88FR131/Sheeva-88SV131/arm926ejs cpu core. SOC versions supported:- 1) 88F6281-A0 define CONFIG_KW88F6281_A0 2) 88F6192-A0 define CONFIG_KW88F6192_A0 Other supported features:- 1) get_random_hex() fucntion 2) PCI Express port initialization 3) NS16550 driver support Contributors: Yotam Admon <yotam@marvell.com> Michael Blostein <michaelbl@marvell.com Reviewed-by: Ronen Shitrit <rshitrit@marvell.com> Acked-by: Stefan Rose <sr@denx.de> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>master
Prafulla Wadaskar
16 years ago
committed by
Jean-Christophe PLAGNIOL-VILLARD
parent
5c3d5817e5
commit
4efb77d41f
@ -0,0 +1,49 @@ |
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(SOC).a
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COBJS-y = dram.o
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COBJS-y += cpu.o
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COBJS-y += mpp.o
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COBJS-y += timer.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
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all: $(obj).depend $(LIB) |
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$(LIB): $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,315 @@ |
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/*
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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* MA 02110-1301 USA |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/cache.h> |
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#include <u-boot/md5.h> |
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#include <asm/arch/kirkwood.h> |
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#define BUFLEN 16 |
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void reset_cpu(unsigned long ignored) |
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{ |
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struct kwcpu_registers *cpureg = |
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(struct kwcpu_registers *)KW_CPU_REG_BASE; |
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writel(readl(&cpureg->rstoutn_mask) | (1 << 2), |
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&cpureg->rstoutn_mask); |
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writel(readl(&cpureg->sys_soft_rst) | 1, |
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&cpureg->sys_soft_rst); |
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while (1) ; |
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} |
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/*
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* Generates Ramdom hex number reading some time varient system registers |
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* and using md5 algorithm |
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*/ |
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unsigned char get_random_hex(void) |
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{ |
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int i; |
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u32 inbuf[BUFLEN]; |
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u8 outbuf[BUFLEN]; |
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|
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/*
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* in case of 88F6281/88F6192 A0, |
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* Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470 |
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* Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and |
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* Does not have names at this moment (no errata available) |
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*/ |
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writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478); |
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for (i = 0; i < BUFLEN; i++) { |
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inbuf[i] = readl(KW_REG_UNDOC_0x1470); |
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} |
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md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf); |
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return outbuf[outbuf[7] % 0x0f]; |
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} |
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/*
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* Window Size |
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* Used with the Base register to set the address window size and location. |
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* Must be programmed from LSB to MSB as sequence of ones followed by |
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* sequence of zeros. The number of ones specifies the size of the window in |
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* 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). |
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* NOTE: A value of 0x0 specifies 64-KByte size. |
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*/ |
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static unsigned int kw_winctrl_calcsize(unsigned int sizeval) |
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{ |
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int i; |
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unsigned int j = 0; |
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u32 val = sizeval >> 1; |
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for (i = 0; val > 0x10000; i++) { |
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j |= (1 << i); |
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val = val >> 1; |
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} |
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return (0x0000ffff & j); |
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} |
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/* prepares data to be loaded in win_Ctrl register */ |
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#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ |
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| (attr << 8) | (kw_winctrl_calcsize(size) << 16)) |
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/*
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* kw_config_adr_windows - Configure address Windows |
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* |
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* There are 8 address windows supported by Kirkwood Soc to addess different |
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* devices. Each window can be configured for size, BAR and remap addr |
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* Below configuration is standard for most of the cases |
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* |
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* If remap function not used, remap_lo must be set as base |
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* |
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* Reference Documentation: |
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* Mbus-L to Mbus Bridge Registers Configuration. |
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* (Sec 25.1 and 25.3 of Datasheet) |
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*/ |
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int kw_config_adr_windows(void) |
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{ |
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struct kwwin_registers *winregs = |
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(struct kwwin_registers *)KW_CPU_WIN_BASE; |
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/* Window 0: PCIE MEM address space */ |
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writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE, |
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KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl); |
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writel(KW_DEFADR_PCI_MEM, &winregs[0].base); |
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writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo); |
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writel(0x0, &winregs[0].remap_hi); |
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/* Window 1: PCIE IO address space */ |
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writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE, |
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KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl); |
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writel(KW_DEFADR_PCI_IO, &winregs[1].base); |
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writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo); |
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writel(0x0, &winregs[1].remap_hi); |
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/* Window 2: NAND Flash address space */ |
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writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, |
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KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl); |
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writel(KW_DEFADR_NANDF, &winregs[2].base); |
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writel(KW_DEFADR_NANDF, &winregs[2].remap_lo); |
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writel(0x0, &winregs[2].remap_hi); |
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/* Window 3: SPI Flash address space */ |
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writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, |
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KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl); |
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writel(KW_DEFADR_SPIF, &winregs[3].base); |
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writel(KW_DEFADR_SPIF, &winregs[3].remap_lo); |
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writel(0x0, &winregs[3].remap_hi); |
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/* Window 4: BOOT Memory address space */ |
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writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, |
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KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl); |
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writel(KW_DEFADR_BOOTROM, &winregs[4].base); |
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/* Window 5: Security SRAM address space */ |
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writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM, |
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KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl); |
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writel(KW_DEFADR_SASRAM, &winregs[5].base); |
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/* Window 6-7: Disabled */ |
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writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl); |
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writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl); |
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return 0; |
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} |
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/*
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* kw_config_gpio - GPIO configuration |
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*/ |
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void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe) |
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{ |
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struct kwgpio_registers *gpio0reg = |
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(struct kwgpio_registers *)KW_GPIO0_BASE; |
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struct kwgpio_registers *gpio1reg = |
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(struct kwgpio_registers *)KW_GPIO1_BASE; |
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/* Init GPIOS to default values as per board requirement */ |
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writel(gpp0_oe_val, &gpio0reg->dout); |
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writel(gpp1_oe_val, &gpio1reg->dout); |
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writel(gpp0_oe, &gpio0reg->oe); |
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writel(gpp1_oe, &gpio1reg->oe); |
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} |
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/*
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* kw_config_mpp - Multi-Purpose Pins Functionality configuration |
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* |
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* Each MPP can be configured to different functionality through |
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* MPP control register, ref (sec 6.1 of kirkwood h/w specification) |
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* |
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* There are maximum 64 Multi-Pourpose Pins on Kirkwood |
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* Each MPP functionality can be configuration by a 4bit value |
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* of MPP control reg, the value and associated functionality depends |
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* upon used SoC varient |
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*/ |
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int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31, |
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u32 mpp32_39, u32 mpp40_47, u32 mpp48_55) |
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{ |
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u32 *mppreg = (u32 *) KW_MPP_BASE; |
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/* program mpp registers */ |
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writel(mpp0_7, &mppreg[0]); |
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writel(mpp8_15, &mppreg[1]); |
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writel(mpp16_23, &mppreg[2]); |
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writel(mpp24_31, &mppreg[3]); |
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writel(mpp32_39, &mppreg[4]); |
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writel(mpp40_47, &mppreg[5]); |
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writel(mpp48_55, &mppreg[6]); |
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return 0; |
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} |
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#if defined(CONFIG_DISPLAY_CPUINFO) |
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int print_cpuinfo(void) |
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{ |
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char *name = "Unknown"; |
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switch (readl(KW_REG_DEVICE_ID) & 0x03) { |
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case 1: |
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name = "88F6192_A0"; |
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break; |
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case 2: |
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name = "88F6281_A0"; |
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break; |
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default: |
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printf("SoC: Unsupported Kirkwood\n"); |
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return -1; |
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} |
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printf("SoC: Kirkwood %s\n", name); |
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return 0; |
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} |
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#endif /* CONFIG_DISPLAY_CPUINFO */ |
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#ifdef CONFIG_ARCH_CPU_INIT |
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int arch_cpu_init(void) |
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{ |
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u32 reg; |
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struct kwcpu_registers *cpureg = |
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(struct kwcpu_registers *)KW_CPU_REG_BASE; |
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/* Linux expects` the internal registers to be at 0xf1000000 */ |
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writel(KW_REGS_PHY_BASE, KW_OFFSET_REG); |
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/* Enable and invalidate L2 cache in write through mode */ |
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writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg); |
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invalidate_l2_cache(); |
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kw_config_adr_windows(); |
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#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8 |
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/*
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* Configures the I/O voltage of the pads connected to Egigabit |
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* Ethernet interface to 1.8V |
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* By defult it is set to 3.3V |
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*/ |
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reg = readl(KW_REG_MPP_OUT_DRV_REG); |
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reg |= (1 << 7); |
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writel(reg, KW_REG_MPP_OUT_DRV_REG); |
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#endif |
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#ifdef CONFIG_KIRKWOOD_EGIGA_INIT |
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/*
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* Set egiga port0/1 in normal functional mode |
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* This is required becasue on kirkwood by default ports are in reset mode |
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* OS egiga driver may not have provision to set them in normal mode |
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* and if u-boot is build without network support, network may fail at OS level |
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*/ |
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reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0)); |
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reg &= ~(1 << 4); /* Clear PortReset Bit */ |
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writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0))); |
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reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1)); |
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reg &= ~(1 << 4); /* Clear PortReset Bit */ |
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writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1))); |
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#endif |
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#ifdef CONFIG_KIRKWOOD_PCIE_INIT |
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/*
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* Enable PCI Express Port0 |
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*/ |
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reg = readl(&cpureg->ctrl_stat); |
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reg |= (1 << 0); /* Set PEX0En Bit */ |
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writel(reg, &cpureg->ctrl_stat); |
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#endif |
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return 0; |
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} |
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#endif /* CONFIG_ARCH_CPU_INIT */ |
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/*
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* SOC specific misc init |
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*/ |
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#if defined(CONFIG_ARCH_MISC_INIT) |
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int arch_misc_init(void) |
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{ |
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volatile u32 temp; |
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/*CPU streaming & write allocate */ |
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temp = readfr_extra_feature_reg(); |
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temp &= ~(1 << 28); /* disable wr alloc */ |
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writefr_extra_feature_reg(temp); |
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temp = readfr_extra_feature_reg(); |
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temp &= ~(1 << 29); /* streaming disabled */ |
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writefr_extra_feature_reg(temp); |
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/* L2Cache settings */ |
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temp = readfr_extra_feature_reg(); |
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/* Disable L2C pre fetch - Set bit 24 */ |
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temp |= (1 << 24); |
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/* enable L2C - Set bit 22 */ |
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temp |= (1 << 22); |
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writefr_extra_feature_reg(temp); |
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icache_enable(); |
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/* Change reset vector to address 0x0 */ |
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temp = get_cr(); |
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set_cr(temp & ~CR_V); |
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return 0; |
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} |
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#endif /* CONFIG_ARCH_MISC_INIT */ |
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#ifdef CONFIG_KIRKWOOD_EGIGA |
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int cpu_eth_init(bd_t *bis) |
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{ |
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kirkwood_egiga_initialize(bis); |
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return 0; |
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} |
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#endif |
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@ -0,0 +1,58 @@ |
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/*
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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* MA 02110-1301 USA |
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*/ |
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#include <config.h> |
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#include <asm/arch/kirkwood.h> |
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#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08)) |
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#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08)) |
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/*
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* kw_sdram_bar - reads SDRAM Base Address Register |
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*/ |
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u32 kw_sdram_bar(enum memory_bank bank) |
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{ |
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u32 result = 0; |
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u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank)); |
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|
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if ((!enable) || (bank > BANK3)) |
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return 0; |
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|
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result = readl(KW_REG_CPUCS_WIN_BAR(bank)); |
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return result; |
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} |
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|
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/*
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* kw_sdram_bs - reads SDRAM Bank size |
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*/ |
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u32 kw_sdram_bs(enum memory_bank bank) |
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{ |
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u32 result = 0; |
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u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank)); |
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|
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if ((!enable) || (bank > BANK3)) |
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return 0; |
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result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank)); |
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result += 0x01000000; |
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return result; |
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} |
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@ -0,0 +1,80 @@ |
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/*
|
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* arch/arm/mach-kirkwood/mpp.c |
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* |
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* MPP functions for Marvell Kirkwood SoCs |
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* Referenced from Linux kernel source |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/kirkwood.h> |
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#include <asm/arch/mpp.h> |
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|
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static u32 kirkwood_variant(void) |
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{ |
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switch (readl(KW_REG_DEVICE_ID) & 0x03) { |
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case 1: |
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return MPP_F6192_MASK; |
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case 2: |
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return MPP_F6281_MASK; |
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default: |
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debug("MPP setup: unknown kirkwood variant\n"); |
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return 0; |
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} |
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} |
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|
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#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4)) |
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#define MPP_NR_REGS (1 + MPP_MAX/8) |
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|
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void kirkwood_mpp_conf(u32 *mpp_list) |
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{ |
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u32 mpp_ctrl[MPP_NR_REGS]; |
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unsigned int variant_mask; |
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int i; |
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|
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variant_mask = kirkwood_variant(); |
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if (!variant_mask) |
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return; |
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|
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debug( "initial MPP regs:"); |
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for (i = 0; i < MPP_NR_REGS; i++) { |
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mpp_ctrl[i] = readl(MPP_CTRL(i)); |
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debug(" %08x", mpp_ctrl[i]); |
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} |
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debug("\n"); |
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|
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|
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while (*mpp_list) { |
||||
unsigned int num = MPP_NUM(*mpp_list); |
||||
unsigned int sel = MPP_SEL(*mpp_list); |
||||
int shift; |
||||
|
||||
if (num > MPP_MAX) { |
||||
debug("kirkwood_mpp_conf: invalid MPP " |
||||
"number (%u)\n", num); |
||||
continue; |
||||
} |
||||
if (!(*mpp_list & variant_mask)) { |
||||
debug("kirkwood_mpp_conf: requested MPP%u config " |
||||
"unavailable on this hardware\n", num); |
||||
continue; |
||||
} |
||||
|
||||
shift = (num & 7) << 2; |
||||
mpp_ctrl[num / 8] &= ~(0xf << shift); |
||||
mpp_ctrl[num / 8] |= sel << shift; |
||||
|
||||
mpp_list++; |
||||
} |
||||
|
||||
debug(" final MPP regs:"); |
||||
for (i = 0; i < MPP_NR_REGS; i++) { |
||||
writel(mpp_ctrl[i], MPP_CTRL(i)); |
||||
debug(" %08x", mpp_ctrl[i]); |
||||
} |
||||
debug("\n"); |
||||
|
||||
} |
||||
@ -0,0 +1,168 @@ |
||||
/*
|
||||
* Copyright (C) Marvell International Ltd. and its affiliates |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/kirkwood.h> |
||||
|
||||
#define UBOOT_CNTR 0 /* counter to use for uboot timer */ |
||||
|
||||
/* Timer reload and current value registers */ |
||||
struct kwtmr_val { |
||||
u32 reload; /* Timer reload reg */ |
||||
u32 val; /* Timer value reg */ |
||||
}; |
||||
|
||||
/* Timer registers */ |
||||
struct kwtmr_registers { |
||||
u32 ctrl; /* Timer control reg */ |
||||
u32 pad[3]; |
||||
struct kwtmr_val tmr[2]; |
||||
u32 wdt_reload; |
||||
u32 wdt_val; |
||||
}; |
||||
|
||||
struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE; |
||||
|
||||
/*
|
||||
* ARM Timers Registers Map |
||||
*/ |
||||
#define CNTMR_CTRL_REG &kwtmr_regs->ctrl |
||||
#define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload |
||||
#define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val |
||||
|
||||
/*
|
||||
* ARM Timers Control Register |
||||
* CPU_TIMERS_CTRL_REG (CTCR) |
||||
*/ |
||||
#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) |
||||
#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) |
||||
#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) |
||||
#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) |
||||
|
||||
#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) |
||||
#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) |
||||
#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) |
||||
#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) |
||||
|
||||
/*
|
||||
* ARM Timer\Watchdog Reload Register |
||||
* CNTMR_RELOAD_REG (TRR) |
||||
*/ |
||||
#define TRG_ARM_TIMER_REL_OFFS 0 |
||||
#define TRG_ARM_TIMER_REL_MASK 0xffffffff |
||||
|
||||
/*
|
||||
* ARM Timer\Watchdog Register |
||||
* CNTMR_VAL_REG (TVRG) |
||||
*/ |
||||
#define TVR_ARM_TIMER_OFFS 0 |
||||
#define TVR_ARM_TIMER_MASK 0xffffffff |
||||
#define TVR_ARM_TIMER_MAX 0xffffffff |
||||
#define TIMER_LOAD_VAL 0xffffffff |
||||
|
||||
#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \ |
||||
(CONFIG_SYS_TCLK / 1000)) |
||||
|
||||
static ulong timestamp; |
||||
static ulong lastdec; |
||||
|
||||
void reset_timer_masked(void) |
||||
{ |
||||
/* reset time */ |
||||
lastdec = READ_TIMER; |
||||
timestamp = 0; |
||||
} |
||||
|
||||
ulong get_timer_masked(void) |
||||
{ |
||||
ulong now = READ_TIMER; |
||||
|
||||
if (lastdec >= now) { |
||||
/* normal mode */ |
||||
timestamp += lastdec - now; |
||||
} else { |
||||
/* we have an overflow ... */ |
||||
timestamp += lastdec + |
||||
(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; |
||||
} |
||||
lastdec = now; |
||||
|
||||
return timestamp; |
||||
} |
||||
|
||||
void reset_timer(void) |
||||
{ |
||||
reset_timer_masked(); |
||||
} |
||||
|
||||
ulong get_timer(ulong base) |
||||
{ |
||||
return get_timer_masked() - base; |
||||
} |
||||
|
||||
void set_timer(ulong t) |
||||
{ |
||||
timestamp = t; |
||||
} |
||||
|
||||
void udelay(unsigned long usec) |
||||
{ |
||||
uint current; |
||||
ulong delayticks; |
||||
|
||||
current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); |
||||
delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); |
||||
|
||||
if (current < delayticks) { |
||||
delayticks -= current; |
||||
while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; |
||||
while ((TIMER_LOAD_VAL - delayticks) < |
||||
readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; |
||||
} else { |
||||
while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > |
||||
(current - delayticks)) ; |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* init the counter |
||||
*/ |
||||
int timer_init(void) |
||||
{ |
||||
unsigned int cntmrctrl; |
||||
|
||||
/* load value into timer */ |
||||
writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); |
||||
writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); |
||||
|
||||
/* enable timer in auto reload mode */ |
||||
cntmrctrl = readl(CNTMR_CTRL_REG); |
||||
cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); |
||||
cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); |
||||
writel(cntmrctrl, CNTMR_CTRL_REG); |
||||
|
||||
/* init the timestamp and lastdec value */ |
||||
reset_timer_masked(); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,159 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#ifndef _KWCPU_H |
||||
#define _KWCPU_H |
||||
|
||||
#include <asm/system.h> |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ |
||||
((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) |
||||
|
||||
#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) |
||||
#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0) |
||||
|
||||
enum memory_bank { |
||||
BANK0, |
||||
BANK1, |
||||
BANK2, |
||||
BANK3 |
||||
}; |
||||
|
||||
enum kwcpu_winen { |
||||
KWCPU_WIN_DISABLE, |
||||
KWCPU_WIN_ENABLE |
||||
}; |
||||
|
||||
enum kwcpu_target { |
||||
KWCPU_TARGET_RESERVED, |
||||
KWCPU_TARGET_MEMORY, |
||||
KWCPU_TARGET_1RESERVED, |
||||
KWCPU_TARGET_SASRAM, |
||||
KWCPU_TARGET_PCIE |
||||
}; |
||||
|
||||
enum kwcpu_attrib { |
||||
KWCPU_ATTR_SASRAM = 0x01, |
||||
KWCPU_ATTR_NANDFLASH = 0x2f, |
||||
KWCPU_ATTR_SPIFLASH = 0x1e, |
||||
KWCPU_ATTR_BOOTROM = 0x1d, |
||||
KWCPU_ATTR_PCIE_IO = 0xe0, |
||||
KWCPU_ATTR_PCIE_MEM = 0xe8 |
||||
}; |
||||
|
||||
/*
|
||||
* Default Device Address MAP BAR values |
||||
*/ |
||||
#define KW_DEFADR_PCI_MEM 0x90000000 |
||||
#define KW_DEFADR_PCI_IO 0xC0000000 |
||||
#define KW_DEFADR_PCI_IO_REMAP 0xC0000000 |
||||
#define KW_DEFADR_SASRAM 0xC8010000 |
||||
#define KW_DEFADR_NANDF 0xD8000000 |
||||
#define KW_DEFADR_SPIF 0xE8000000 |
||||
#define KW_DEFADR_BOOTROM 0xF8000000 |
||||
|
||||
/*
|
||||
* read feroceon/sheeva core extra feature register |
||||
* using co-proc instruction |
||||
*/ |
||||
static inline unsigned int readfr_extra_feature_reg(void) |
||||
{ |
||||
unsigned int val; |
||||
asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" |
||||
(val)::"cc"); |
||||
return val; |
||||
} |
||||
|
||||
/*
|
||||
* write feroceon/sheeva core extra feature register |
||||
* using co-proc instruction |
||||
*/ |
||||
static inline void writefr_extra_feature_reg(unsigned int val) |
||||
{ |
||||
asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" |
||||
(val):"cc"); |
||||
isb(); |
||||
} |
||||
|
||||
/*
|
||||
* MBus-L to Mbus Bridge Registers |
||||
* Ref: Datasheet sec:A.3 |
||||
*/ |
||||
struct kwwin_registers { |
||||
u32 ctrl; |
||||
u32 base; |
||||
u32 remap_lo; |
||||
u32 remap_hi; |
||||
}; |
||||
|
||||
/*
|
||||
* CPU control and status Registers |
||||
* Ref: Datasheet sec:A.3.2 |
||||
*/ |
||||
struct kwcpu_registers { |
||||
u32 config; /*0x20100 */ |
||||
u32 ctrl_stat; /*0x20104 */ |
||||
u32 rstoutn_mask; /* 0x20108 */ |
||||
u32 sys_soft_rst; /* 0x2010C */ |
||||
u32 ahb_mbus_cause_irq; /* 0x20110 */ |
||||
u32 ahb_mbus_mask_irq; /* 0x20114 */ |
||||
u32 pad1[2]; |
||||
u32 ftdll_config; /* 0x20120 */ |
||||
u32 pad2; |
||||
u32 l2_cfg; /* 0x20128 */ |
||||
}; |
||||
|
||||
/*
|
||||
* GPIO Registers |
||||
* Ref: Datasheet sec:A.19 |
||||
*/ |
||||
struct kwgpio_registers { |
||||
u32 dout; |
||||
u32 oe; |
||||
u32 blink_en; |
||||
u32 din_pol; |
||||
u32 din; |
||||
u32 irq_cause; |
||||
u32 irq_mask; |
||||
u32 irq_level; |
||||
}; |
||||
|
||||
/*
|
||||
* functions |
||||
*/ |
||||
void reset_cpu(unsigned long ignored); |
||||
unsigned char get_random_hex(void); |
||||
unsigned int kw_sdram_bar(enum memory_bank bank); |
||||
unsigned int kw_sdram_bs(enum memory_bank bank); |
||||
int kw_config_adr_windows(void); |
||||
void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, |
||||
unsigned int gpp0_oe, unsigned int gpp1_oe); |
||||
int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, |
||||
unsigned int mpp16_23, unsigned int mpp24_31, |
||||
unsigned int mpp32_39, unsigned int mpp40_47, |
||||
unsigned int mpp48_55); |
||||
#endif /* __ASSEMBLY__ */ |
||||
#endif /* _KWCPU_H */ |
||||
@ -0,0 +1,69 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* Header file for the Marvell's Feroceon CPU core. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#ifndef _ASM_ARCH_KIRKWOOD_H |
||||
#define _ASM_ARCH_KIRKWOOD_H |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
#include <asm/types.h> |
||||
#include <asm/io.h> |
||||
#endif /* __ASSEMBLY__ */ |
||||
|
||||
#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) |
||||
#include <asm/arch/cpu.h> |
||||
|
||||
/* SOC specific definations */ |
||||
#define INTREG_BASE 0xd0000000 |
||||
#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) |
||||
#define KW_OFFSET_REG (INTREG_BASE + 0x20080) |
||||
|
||||
/* undocumented registers */ |
||||
#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) |
||||
#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) |
||||
|
||||
#define KW_UART0_BASE (KW_REGISTER(0x12000)) |
||||
#define KW_UART1_BASE (KW_REGISTER(0x13000)) |
||||
#define KW_MPP_BASE (KW_REGISTER(0x10000)) |
||||
#define KW_GPIO0_BASE (KW_REGISTER(0x10100)) |
||||
#define KW_GPIO1_BASE (KW_REGISTER(0x10140)) |
||||
#define KW_NANDF_BASE (KW_REGISTER(0x10418)) |
||||
#define KW_SPI_BASE (KW_REGISTER(0x10600)) |
||||
#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) |
||||
#define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) |
||||
#define KW_TIMER_BASE (KW_REGISTER(0x20300)) |
||||
#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) |
||||
#define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) |
||||
#define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) |
||||
|
||||
#if defined (CONFIG_KW88F6281) |
||||
#include <asm/arch/kw88f6281.h> |
||||
#elif defined (CONFIG_KW88F6192) |
||||
#include <asm/arch/kw88f6192.h> |
||||
#else |
||||
#error "SOC Name not defined" |
||||
#endif /* CONFIG_KW88F6281 */ |
||||
#endif /* CONFIG_FEROCEON_88FR131 */ |
||||
#endif /* _ASM_ARCH_KIRKWOOD_H */ |
||||
@ -0,0 +1,37 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#ifndef _CONFIG_KW88F6192_H |
||||
#define _CONFIG_KW88F6192_H |
||||
|
||||
/* SOC specific definations */ |
||||
#define KW88F6192_REGS_PHYS_BASE 0xf1000000 |
||||
#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE |
||||
|
||||
/* TCLK Core Clock defination */ |
||||
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ |
||||
|
||||
#endif /* _CONFIG_KW88F6192_H */ |
||||
@ -0,0 +1,37 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#ifndef _ASM_ARCH_KW88F6281_H |
||||
#define _ASM_ARCH_KW88F6281_H |
||||
|
||||
/* SOC specific definations */ |
||||
#define KW88F6281_REGS_PHYS_BASE 0xf1000000 |
||||
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE |
||||
|
||||
/* TCLK Core Clock defination*/ |
||||
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ |
||||
|
||||
#endif /* _ASM_ARCH_KW88F6281_H */ |
||||
@ -0,0 +1,303 @@ |
||||
/*
|
||||
* linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins |
||||
* |
||||
* Copyright 2009: Marvell Technology Group Ltd. |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public |
||||
* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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|
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#ifndef __KIRKWOOD_MPP_H |
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#define __KIRKWOOD_MPP_H |
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|
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#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ |
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/* MPP number */ ((_num) & 0xff) | \
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/* MPP select value */ (((_sel) & 0xf) << 8) | \
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/* may be input signal */ ((!!(_in)) << 12) | \
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/* may be output signal */ ((!!(_out)) << 13) | \
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/* available on F6180 */ ((!!(_F6180)) << 14) | \
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/* available on F6190 */ ((!!(_F6190)) << 15) | \
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/* available on F6192 */ ((!!(_F6192)) << 16) | \
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/* available on F6281 */ ((!!(_F6281)) << 17)) |
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|
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#define MPP_NUM(x) ((x) & 0xff) |
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#define MPP_SEL(x) (((x) >> 8) & 0xf) |
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|
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/* num sel i o 6180 6190 6192 6281 */ |
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|
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#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) |
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#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) |
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#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) |
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#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) |
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#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) |
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#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) |
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#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) |
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#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) |
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#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) |
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#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) |
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#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) |
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#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) |
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#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) |
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#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) |
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#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) |
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#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) |
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|
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#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) |
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#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) |
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#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) |
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#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) |
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|
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#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) |
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#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) |
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#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) |
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|
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#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) |
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#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) |
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#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) |
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#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) |
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|
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#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) |
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#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) |
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#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) |
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#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) |
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#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) |
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#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) |
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|
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#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) |
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#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) |
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#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) |
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#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) |
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#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) |
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|
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#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) |
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#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) |
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#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) |
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#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) |
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#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) |
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|
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#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) |
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#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) |
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#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) |
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#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) |
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#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) |
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#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) |
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|
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#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) |
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#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) |
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|
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#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) |
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|
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#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) |
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#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) |
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#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) |
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|
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#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) |
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#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) |
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#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) |
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|
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#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) |
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#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) |
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#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) |
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#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) |
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#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) |
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#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) |
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#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) |
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#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) |
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#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) |
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#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) |
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#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) |
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#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) |
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#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) |
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#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) |
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#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) |
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#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) |
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#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) |
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#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) |
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#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) |
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#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) |
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#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) |
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#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) |
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#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) |
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#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) |
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#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) |
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#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) |
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#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) |
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#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) |
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#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) |
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#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) |
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#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) |
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#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) |
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#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) |
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#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) |
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#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) |
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#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) |
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#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) |
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#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) |
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#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) |
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|
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#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) |
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#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) |
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#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) |
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#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) |
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#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) |
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|
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#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) |
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#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) |
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#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) |
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|
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#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) |
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#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) |
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#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) |
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|
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#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) |
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#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) |
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#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) |
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|
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#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) |
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#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) |
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#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) |
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|
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#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) |
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#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) |
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#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) |
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|
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#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) |
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#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) |
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#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) |
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|
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#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) |
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#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) |
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#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) |
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#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) |
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#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) |
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#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) |
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#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) |
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#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) |
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#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) |
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#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) |
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#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) |
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#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) |
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#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) |
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#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) |
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#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) |
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#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) |
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#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP48_TDM_DTX MPP( 48. 0x2, 0, 1, 0, 0, 0, 1 ) |
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#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) |
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#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) |
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#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) |
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#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) |
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#define MPP_MAX 49 |
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void kirkwood_mpp_conf(unsigned int *mpp_list); |
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#endif |
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Loading…
Reference in new issue