Serial driver via the EmbeddedICE macrocell's DCC channel using co-processor 14. It does include a timeout to ensure that the system does not totally freeze when there is nothing connected to read. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>master
Jean-Christophe PLAGNIOL-VILLARD
16 years ago
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4f5728987f
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/*
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* Copyright (C) 2004-2007 ARM Limited. |
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* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License version 2 |
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* as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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* As a special exception, if other files instantiate templates or use macros |
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* or inline functions from this file, or you compile this file and link it |
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* with other works to produce a work based on this file, this file does not |
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* by itself cause the resulting work to be covered by the GNU General Public |
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* License. However the source code for this file must still be made available |
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* in accordance with section (3) of the GNU General Public License. |
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* This exception does not invalidate any other reasons why a work based on |
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* this file might be covered by the GNU General Public License. |
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*/ |
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#include <common.h> |
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#include <devices.h> |
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#define DCC_ARM9_RBIT (1 << 0) |
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#define DCC_ARM9_WBIT (1 << 1) |
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#define DCC_ARM11_RBIT (1 << 30) |
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#define DCC_ARM11_WBIT (1 << 29) |
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#define read_core_id(x) do { \ |
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__asm__ ("mrc p15, 0, %0, c0, c0, 0\n" : "=r" (x)); \
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x = (x >> 4) & 0xFFF; \
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} while (0); |
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/*
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* ARM9 |
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*/ |
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#define write_arm9_dcc(x) \ |
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__asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x)) |
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#define read_arm9_dcc(x) \ |
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__asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x)) |
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#define status_arm9_dcc(x) \ |
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__asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x)) |
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#define can_read_arm9_dcc(x) do { \ |
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status_arm9_dcc(x); \
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x &= DCC_ARM9_RBIT; \
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} while (0); |
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#define can_write_arm9_dcc(x) do { \ |
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status_arm9_dcc(x); \
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x &= DCC_ARM9_WBIT; \
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x = (x == 0); \
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} while (0); |
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/*
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* ARM11 |
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*/ |
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#define write_arm11_dcc(x) \ |
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__asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x)) |
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#define read_arm11_dcc(x) \ |
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__asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x)) |
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#define status_arm11_dcc(x) \ |
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__asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x)) |
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#define can_read_arm11_dcc(x) do { \ |
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status_arm11_dcc(x); \
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x &= DCC_ARM11_RBIT; \
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} while (0); |
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#define can_write_arm11_dcc(x) do { \ |
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status_arm11_dcc(x); \
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x &= DCC_ARM11_WBIT; \
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x = (x == 0); \
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} while (0); |
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#define TIMEOUT_COUNT 0x4000000 |
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static enum { |
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arm9_and_earlier, |
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arm11_and_later |
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} arm_type = arm9_and_earlier; |
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#ifndef CONFIG_ARM_DCC_MULTI |
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#define arm_dcc_init serial_init |
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void serial_setbrg(void) {} |
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#define arm_dcc_getc serial_getc |
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#define arm_dcc_putc serial_putc |
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#define arm_dcc_puts serial_puts |
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#define arm_dcc_tstc serial_tstc |
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#endif |
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int arm_dcc_init(void) |
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{ |
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register unsigned int id; |
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read_core_id(id); |
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if (id >= 0xb00) |
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arm_type = arm11_and_later; |
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else |
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arm_type = arm9_and_earlier; |
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return 0; |
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} |
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int arm_dcc_getc(void) |
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{ |
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int ch; |
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register unsigned int reg; |
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switch (arm_type) { |
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case arm11_and_later: |
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do { |
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can_read_arm11_dcc(reg); |
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} while (!reg); |
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read_arm11_dcc(ch); |
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break; |
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case arm9_and_earlier: |
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default: |
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do { |
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can_read_arm9_dcc(reg); |
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} while (!reg); |
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read_arm9_dcc(ch); |
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break; |
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} |
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return ch; |
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} |
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void arm_dcc_putc(char ch) |
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{ |
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register unsigned int reg; |
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unsigned int timeout_count = TIMEOUT_COUNT; |
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switch (arm_type) { |
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case arm11_and_later: |
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while (--timeout_count) { |
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can_write_arm11_dcc(reg); |
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if (reg) |
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break; |
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} |
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if (timeout_count == 0) |
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return; |
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else |
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write_arm11_dcc(ch); |
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break; |
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case arm9_and_earlier: |
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default: |
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while (--timeout_count) { |
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can_write_arm9_dcc(reg); |
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if (reg) |
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break; |
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} |
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if (timeout_count == 0) |
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return; |
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else |
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write_arm9_dcc(ch); |
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break; |
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} |
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} |
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void arm_dcc_puts(const char *s) |
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{ |
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while (*s) |
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arm_dcc_putc(*s++); |
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} |
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int arm_dcc_tstc(void) |
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{ |
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register unsigned int reg; |
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switch (arm_type) { |
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case arm11_and_later: |
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can_read_arm11_dcc(reg); |
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break; |
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case arm9_and_earlier: |
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default: |
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can_read_arm9_dcc(reg); |
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break; |
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} |
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return reg; |
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} |
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#ifdef CONFIG_ARM_DCC_MULTI |
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static device_t arm_dcc_dev; |
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int drv_arm_dcc_init(void) |
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{ |
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int rc; |
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/* Device initialization */ |
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memset(&arm_dcc_dev, 0, sizeof(arm_dcc_dev)); |
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strcpy(arm_dcc_dev.name, "dcc"); |
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arm_dcc_dev.ext = 0; /* No extensions */ |
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arm_dcc_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT; |
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arm_dcc_dev.tstc = arm_dcc_tstc; /* 'tstc' function */ |
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arm_dcc_dev.getc = arm_dcc_getc; /* 'getc' function */ |
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arm_dcc_dev.putc = arm_dcc_putc; /* 'putc' function */ |
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arm_dcc_dev.puts = arm_dcc_puts; /* 'puts' function */ |
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rc = device_register(&arm_dcc_dev); |
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if (rc == 0) { |
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arm_dcc_init(); |
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return 1; |
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} |
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return 0; |
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} |
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#endif |
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