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imx: mx53ard: Convert to iomux-v3

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There is no change of behavior.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
master
Benoît Thébaudeau 12 years ago committed by Stefano Babic
parent 48f0108df9
commit 5053b59300
1 changed files with 141 additions and 186 deletions
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  1. 327
      board/freescale/mx53ard/mx53ard.c

327
board/freescale/mx53ard/mx53ard.c
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@ -23,11 +23,10 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/errno.h>
#include <netdev.h>
#include <mmc.h>
@ -61,6 +60,41 @@ void dram_init_banksize(void)
#ifdef CONFIG_NAND_MXC
static void setup_iomux_nand(void)
{
static const iomux_v3_cfg_t nand_pads[] = {
NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
PAD_CTL_PUS_100K_UP),
NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
PAD_CTL_PUS_100K_UP),
NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
};
u32 i, reg;
reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
@ -72,48 +106,7 @@ static void setup_iomux_nand(void)
__raw_writel(reg, WEIM_BASE_ADDR + i);
}
mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}
#else
static void setup_iomux_nand(void)
@ -121,24 +114,17 @@ static void setup_iomux_nand(void)
}
#endif
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
static void setup_iomux_uart(void)
{
/* UART1 RXD */
mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
/* UART1 TXD */
mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
static const iomux_v3_cfg_t uart_pads[] = {
NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#ifdef CONFIG_FSL_ESDHC
@ -152,9 +138,9 @@ int board_mmc_getcd(struct mmc *mmc)
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
gpio_direction_input(IMX_GPIO_NR(1, 1));
mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
gpio_direction_input(IMX_GPIO_NR(1, 4));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
@ -165,8 +151,36 @@ int board_mmc_getcd(struct mmc *mmc)
return ret;
}
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)
#define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
PAD_CTL_DSE_HIGH)
int board_mmc_init(bd_t *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
};
static const iomux_v3_cfg_t sd2_pads[] = {
NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
};
u32 index;
s32 status = 0;
@ -176,56 +190,12 @@ int board_mmc_init(bd_t *bis)
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA0,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA1,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA2,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA3,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
imx_iomux_v3_setup_multiple_pads(sd1_pads,
ARRAY_SIZE(sd1_pads));
break;
case 1:
mxc_request_iomux(MX53_PIN_SD2_CMD,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX53_PIN_SD2_CLK,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_request_iomux(MX53_PIN_SD2_DATA0,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD2_DATA1,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD2_DATA2,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD2_DATA3,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_ATA_DATA12,
IOMUX_CONFIG_ALT2);
mxc_request_iomux(MX53_PIN_ATA_DATA13,
IOMUX_CONFIG_ALT2);
mxc_request_iomux(MX53_PIN_ATA_DATA14,
IOMUX_CONFIG_ALT2);
mxc_request_iomux(MX53_PIN_ATA_DATA15,
IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
imx_iomux_v3_setup_multiple_pads(sd2_pads,
ARRAY_SIZE(sd2_pads));
break;
default:
printf("Warning: you configured more ESDHC controller"
@ -242,85 +212,70 @@ int board_mmc_init(bd_t *bis)
static void weim_smc911x_iomux(void)
{
static const iomux_v3_cfg_t weim_smc911x_pads[] = {
/* Data bus */
NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
/* Address lines */
NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
/* other EIM signals for ethernet */
MX53_PAD_EIM_OE__EMI_WEIM_OE,
MX53_PAD_EIM_RW__EMI_WEIM_RW,
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
};
/* ETHERNET_INT as GPIO2_31 */
mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
gpio_direction_input(ETHERNET_INT);
/* Data bus */
mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
/* Address lines */
mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
/* other EIM signals for ethernet */
mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
/* WEIM bus */
imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
ARRAY_SIZE(weim_smc911x_pads));
}
static void weim_cs1_settings(void)

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