The gdsys hrcon board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 1x GbE (optional) - Lattice ECP3 FPGA connected via eLBC and PCIe Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>master
Dirk Eibach
10 years ago
committed by
Stefan Roese
parent
a8cb9d0b17
commit
50dcf89d90
@ -0,0 +1,295 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <gdsys_fpga.h> |
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enum { |
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STATE_TX_PACKET_BUILDING = 1<<0, |
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STATE_TX_TRANSMITTING = 1<<1, |
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STATE_TX_BUFFER_FULL = 1<<2, |
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STATE_TX_ERR = 1<<3, |
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STATE_RECEIVE_TIMEOUT = 1<<4, |
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STATE_PROC_RX_STORE_TIMEOUT = 1<<5, |
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STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6, |
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STATE_RX_DIST_ERR = 1<<7, |
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STATE_RX_LENGTH_ERR = 1<<8, |
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STATE_RX_FRAME_CTR_ERR = 1<<9, |
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STATE_RX_FCS_ERR = 1<<10, |
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STATE_RX_PACKET_DROPPED = 1<<11, |
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STATE_RX_DATA_LAST = 1<<12, |
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STATE_RX_DATA_FIRST = 1<<13, |
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STATE_RX_DATA_AVAILABLE = 1<<15, |
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}; |
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enum { |
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CTRL_PROC_RECEIVE_ENABLE = 1<<12, |
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CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15, |
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}; |
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enum { |
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IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5, |
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IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6, |
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IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7, |
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IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8, |
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}; |
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struct io_generic_packet { |
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u16 target_address; |
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u16 source_address; |
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u8 packet_type; |
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u8 bc; |
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u16 packet_length; |
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} __attribute__((__packed__)); |
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unsigned long long rx_ctr; |
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unsigned long long tx_ctr; |
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unsigned long long err_ctr; |
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static void io_check_status(unsigned int fpga, u16 status, bool silent) |
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{ |
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u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | |
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STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR | |
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STATE_RX_PACKET_DROPPED | STATE_TX_ERR; |
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if (!(status & mask)) { |
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FPGA_SET_REG(fpga, ep.rx_tx_status, status); |
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return; |
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} |
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err_ctr++; |
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FPGA_SET_REG(fpga, ep.rx_tx_status, status); |
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if (silent) |
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return; |
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if (status & STATE_RX_PACKET_DROPPED) |
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printf("RX_PACKET_DROPPED, status %04x\n", status); |
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if (status & STATE_RX_DIST_ERR) |
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printf("RX_DIST_ERR\n"); |
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if (status & STATE_RX_LENGTH_ERR) |
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printf("RX_LENGTH_ERR\n"); |
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if (status & STATE_RX_FRAME_CTR_ERR) |
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printf("RX_FRAME_CTR_ERR\n"); |
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if (status & STATE_RX_FCS_ERR) |
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printf("RX_FCS_ERR\n"); |
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if (status & STATE_TX_ERR) |
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printf("TX_ERR\n"); |
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} |
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static void io_send(unsigned int fpga, unsigned int size) |
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{ |
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unsigned int k; |
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struct io_generic_packet packet = { |
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.source_address = 1, |
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.packet_type = 1, |
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.packet_length = size, |
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}; |
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u16 *p = (u16 *)&packet; |
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for (k = 0; k < sizeof(packet) / 2; ++k) |
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FPGA_SET_REG(fpga, ep.transmit_data, *p++); |
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for (k = 0; k < (size + 1) / 2; ++k) |
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FPGA_SET_REG(fpga, ep.transmit_data, k); |
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FPGA_SET_REG(fpga, ep.rx_tx_control, |
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CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER); |
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tx_ctr++; |
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} |
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static void io_receive(unsigned int fpga) |
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{ |
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unsigned int k = 0; |
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u16 rx_tx_status; |
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); |
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while (rx_tx_status & STATE_RX_DATA_AVAILABLE) { |
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u16 rx; |
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if (rx_tx_status & STATE_RX_DATA_LAST) |
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rx_ctr++; |
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FPGA_GET_REG(fpga, ep.receive_data, &rx); |
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); |
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++k; |
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} |
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} |
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static void io_reflect(unsigned int fpga) |
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{ |
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u16 buffer[128]; |
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unsigned int k = 0; |
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unsigned int n; |
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u16 rx_tx_status; |
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); |
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while (rx_tx_status & STATE_RX_DATA_AVAILABLE) { |
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FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]); |
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if (rx_tx_status & STATE_RX_DATA_LAST) |
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break; |
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); |
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} |
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if (!k) |
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return; |
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for (n = 0; n < k; ++n) |
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FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]); |
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FPGA_SET_REG(fpga, ep.rx_tx_control, |
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CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER); |
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tx_ctr++; |
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} |
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/*
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* FPGA io-endpoint reflector |
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* |
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* Syntax: |
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* ioreflect {fpga} {reportrate} |
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*/ |
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int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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unsigned int fpga; |
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unsigned int rate = 0; |
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unsigned long long last_seen = 0; |
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if (argc < 2) |
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return CMD_RET_USAGE; |
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fpga = simple_strtoul(argv[1], NULL, 10); |
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/*
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* If another parameter, it is the report rate in packets. |
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*/ |
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if (argc > 2) |
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rate = simple_strtoul(argv[2], NULL, 10); |
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/* enable receive path */ |
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FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); |
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/* set device address to dummy 1*/ |
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FPGA_SET_REG(fpga, ep.device_address, 1); |
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rx_ctr = 0; tx_ctr = 0; err_ctr = 0; |
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while (1) { |
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u16 top_int; |
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u16 rx_tx_status; |
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FPGA_GET_REG(fpga, top_interrupt, &top_int); |
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); |
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io_check_status(fpga, rx_tx_status, true); |
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if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) && |
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(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)) |
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io_reflect(fpga); |
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if (rate) { |
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if (!(tx_ctr % rate) && (tx_ctr != last_seen)) |
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printf("refl %llu, err %llu\n", tx_ctr, |
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err_ctr); |
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last_seen = tx_ctr; |
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} |
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if (ctrlc()) |
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break; |
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} |
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return 0; |
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} |
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/*
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* FPGA io-endpoint looptest |
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* |
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* Syntax: |
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* ioloop {fpga} {size} {rate} |
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*/ |
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#define DISP_LINE_LEN 16 |
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int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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unsigned int fpga; |
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unsigned int size; |
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unsigned int rate = 0; |
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if (argc < 3) |
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return CMD_RET_USAGE; |
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/*
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* FPGA is specified since argc > 2 |
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*/ |
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fpga = simple_strtoul(argv[1], NULL, 10); |
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/*
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* packet size is specified since argc > 2 |
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*/ |
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size = simple_strtoul(argv[2], NULL, 10); |
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/*
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* If another parameter, it is the test rate in packets per second. |
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*/ |
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if (argc > 3) |
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rate = simple_strtoul(argv[3], NULL, 10); |
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/* enable receive path */ |
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FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); |
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/* set device address to dummy 1*/ |
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FPGA_SET_REG(fpga, ep.device_address, 1); |
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rx_ctr = 0; tx_ctr = 0; err_ctr = 0; |
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while (1) { |
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u16 top_int; |
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u16 rx_tx_status; |
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FPGA_GET_REG(fpga, top_interrupt, &top_int); |
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FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); |
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io_check_status(fpga, rx_tx_status, false); |
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if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS) |
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io_send(fpga, size); |
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if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) |
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io_receive(fpga); |
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if (rate) { |
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if (ctrlc()) |
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break; |
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udelay(1000000 / rate); |
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if (!(tx_ctr % rate)) |
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printf("d %lld, tx %llu, rx %llu, err %llu\n", |
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tx_ctr - rx_ctr, tx_ctr, rx_ctr, |
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err_ctr); |
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} |
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} |
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return 0; |
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} |
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U_BOOT_CMD( |
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ioloop, 4, 0, do_ioloop, |
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"fpga io-endpoint looptest", |
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"fpga packetsize [packets/sec]" |
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); |
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U_BOOT_CMD( |
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ioreflect, 3, 0, do_ioreflect, |
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"fpga io-endpoint reflector", |
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"fpga reportrate" |
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); |
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@ -0,0 +1,88 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <gdsys_fpga.h> |
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#include <miiphy.h> |
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#include "ihs_mdio.h" |
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static int ihs_mdio_idle(struct mii_dev *bus) |
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{ |
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struct ihs_mdio_info *info = bus->priv; |
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u16 val; |
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unsigned int ctr = 0; |
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do { |
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FPGA_GET_REG(info->fpga, mdio.control, &val); |
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udelay(100); |
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if (ctr++ > 10) |
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return -1; |
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} while (!(val & (1 << 12))); |
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return 0; |
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} |
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static int ihs_mdio_reset(struct mii_dev *bus) |
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{ |
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ihs_mdio_idle(bus); |
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return 0; |
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} |
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static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr, |
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int regnum) |
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{ |
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struct ihs_mdio_info *info = bus->priv; |
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u16 val; |
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ihs_mdio_idle(bus); |
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FPGA_SET_REG(info->fpga, mdio.control, |
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((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10)); |
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/* wait for rx data available */ |
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udelay(100); |
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FPGA_GET_REG(info->fpga, mdio.rx_data, &val); |
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return val; |
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} |
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static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr, |
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int regnum, u16 value) |
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{ |
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struct ihs_mdio_info *info = bus->priv; |
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ihs_mdio_idle(bus); |
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FPGA_SET_REG(info->fpga, mdio.address_data, value); |
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FPGA_SET_REG(info->fpga, mdio.control, |
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((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10)); |
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return 0; |
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} |
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int ihs_mdio_init(struct ihs_mdio_info *info) |
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{ |
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struct mii_dev *bus = mdio_alloc(); |
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if (!bus) { |
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printf("Failed to allocate FSL MDIO bus\n"); |
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return -1; |
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} |
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bus->read = ihs_mdio_read; |
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bus->write = ihs_mdio_write; |
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bus->reset = ihs_mdio_reset; |
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sprintf(bus->name, info->name); |
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bus->priv = info; |
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return mdio_register(bus); |
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} |
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@ -0,0 +1,18 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _IHS_MDIO_H_ |
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#define _IHS_MDIO_H_ |
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struct ihs_mdio_info { |
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u32 fpga; |
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char *name; |
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}; |
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int ihs_mdio_init(struct ihs_mdio_info *info); |
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#endif |
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@ -0,0 +1,280 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <miiphy.h> |
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enum { |
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MIICMD_SET, |
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MIICMD_MODIFY, |
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MIICMD_VERIFY_VALUE, |
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MIICMD_WAIT_FOR_VALUE, |
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}; |
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struct mii_setupcmd { |
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u8 token; |
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u8 reg; |
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u16 data; |
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u16 mask; |
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u32 timeout; |
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}; |
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/*
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* verify we are talking to a 88e1518 |
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*/ |
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struct mii_setupcmd verify_88e1518[] = { |
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{ MIICMD_SET, 22, 0x0000 }, |
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{ MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff }, |
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{ MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 }, |
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}; |
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/*
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* workaround for erratum mentioned in 88E1518 release notes |
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*/ |
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struct mii_setupcmd fixup_88e1518[] = { |
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{ MIICMD_SET, 22, 0x00ff }, |
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{ MIICMD_SET, 17, 0x214b }, |
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{ MIICMD_SET, 16, 0x2144 }, |
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{ MIICMD_SET, 17, 0x0c28 }, |
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{ MIICMD_SET, 16, 0x2146 }, |
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{ MIICMD_SET, 17, 0xb233 }, |
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{ MIICMD_SET, 16, 0x214d }, |
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{ MIICMD_SET, 17, 0xcc0c }, |
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{ MIICMD_SET, 16, 0x2159 }, |
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{ MIICMD_SET, 22, 0x00fb }, |
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{ MIICMD_SET, 7, 0xc00d }, |
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{ MIICMD_SET, 22, 0x0000 }, |
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}; |
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/*
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* default initialization: |
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* - set RGMII receive timing to "receive clock transition when data stable" |
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* - set RGMII transmit timing to "transmit clock internally delayed" |
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* - set RGMII output impedance target to 78,8 Ohm |
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* - run output impedance calibration |
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* - set autonegotiation advertise to 1000FD only |
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*/ |
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struct mii_setupcmd default_88e1518[] = { |
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{ MIICMD_SET, 22, 0x0002 }, |
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{ MIICMD_MODIFY, 21, 0x0030, 0x0030 }, |
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{ MIICMD_MODIFY, 25, 0x0000, 0x0003 }, |
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{ MIICMD_MODIFY, 24, 0x8000, 0x8000 }, |
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{ MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 }, |
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{ MIICMD_SET, 22, 0x0000 }, |
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{ MIICMD_MODIFY, 4, 0x0000, 0x01e0 }, |
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{ MIICMD_MODIFY, 9, 0x0200, 0x0300 }, |
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}; |
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/*
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* turn off CLK125 for PHY daughterboard |
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*/ |
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struct mii_setupcmd ch1fix_88e1518[] = { |
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{ MIICMD_SET, 22, 0x0002 }, |
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{ MIICMD_MODIFY, 16, 0x0006, 0x0006 }, |
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{ MIICMD_SET, 22, 0x0000 }, |
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}; |
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/*
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* perform copper software reset |
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*/ |
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struct mii_setupcmd swreset_88e1518[] = { |
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{ MIICMD_SET, 22, 0x0000 }, |
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{ MIICMD_MODIFY, 0, 0x8000, 0x8000 }, |
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{ MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 }, |
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}; |
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/*
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* special one for 88E1514: |
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* Force SGMII to Copper mode |
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*/ |
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struct mii_setupcmd mii_to_copper_88e1514[] = { |
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{ MIICMD_SET, 22, 0x0012 }, |
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{ MIICMD_MODIFY, 20, 0x0001, 0x0007 }, |
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{ MIICMD_MODIFY, 20, 0x8000, 0x8000 }, |
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{ MIICMD_SET, 22, 0x0000 }, |
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}; |
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/*
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* turn off SGMII auto-negotiation |
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*/ |
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struct mii_setupcmd sgmii_autoneg_off_88e1518[] = { |
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{ MIICMD_SET, 22, 0x0001 }, |
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{ MIICMD_MODIFY, 0, 0x0000, 0x1000 }, |
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{ MIICMD_MODIFY, 0, 0x8000, 0x8000 }, |
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{ MIICMD_SET, 22, 0x0000 }, |
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}; |
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/*
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* invert LED2 polarity |
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*/ |
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struct mii_setupcmd invert_led2_88e1514[] = { |
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{ MIICMD_SET, 22, 0x0003 }, |
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{ MIICMD_MODIFY, 17, 0x0030, 0x0010 }, |
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{ MIICMD_SET, 22, 0x0000 }, |
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}; |
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static int process_setupcmd(const char *bus, unsigned char addr, |
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struct mii_setupcmd *setupcmd) |
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{ |
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int res; |
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u8 reg = setupcmd->reg; |
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u16 data = setupcmd->data; |
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u16 mask = setupcmd->mask; |
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u32 timeout = setupcmd->timeout; |
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u16 orig_data; |
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unsigned long start; |
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|
||||
debug("mii %s:%u reg %2u ", bus, addr, reg); |
||||
|
||||
switch (setupcmd->token) { |
||||
case MIICMD_MODIFY: |
||||
res = miiphy_read(bus, addr, reg, &orig_data); |
||||
if (res) |
||||
break; |
||||
debug("is %04x. (value %04x mask %04x) ", orig_data, data, |
||||
mask); |
||||
data = (orig_data & ~mask) | (data & mask); |
||||
/* fallthrough */ |
||||
case MIICMD_SET: |
||||
debug("=> %04x\n", data); |
||||
res = miiphy_write(bus, addr, reg, data); |
||||
break; |
||||
case MIICMD_VERIFY_VALUE: |
||||
res = miiphy_read(bus, addr, reg, &orig_data); |
||||
if (res) |
||||
break; |
||||
if ((orig_data & mask) != (data & mask)) |
||||
res = -1; |
||||
debug("(value %04x mask %04x) == %04x? %s\n", data, mask, |
||||
orig_data, res ? "FAIL" : "PASS"); |
||||
break; |
||||
case MIICMD_WAIT_FOR_VALUE: |
||||
res = -1; |
||||
start = get_timer(0); |
||||
while ((res != 0) && (get_timer(start) < timeout)) { |
||||
res = miiphy_read(bus, addr, reg, &orig_data); |
||||
if (res) |
||||
continue; |
||||
if ((orig_data & mask) != (data & mask)) |
||||
res = -1; |
||||
} |
||||
debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data, |
||||
mask, orig_data, res ? "FAIL" : "PASS", |
||||
get_timer(start)); |
||||
break; |
||||
default: |
||||
res = -1; |
||||
break; |
||||
} |
||||
|
||||
return res; |
||||
} |
||||
|
||||
static int process_setup(const char *bus, unsigned char addr, |
||||
struct mii_setupcmd *setupcmd, unsigned int count) |
||||
{ |
||||
int res = 0; |
||||
unsigned int k; |
||||
|
||||
for (k = 0; k < count; ++k) { |
||||
res = process_setupcmd(bus, addr, &setupcmd[k]); |
||||
if (res) { |
||||
printf("mii cmd %u on bus %s addr %u failed, aborting setup\n", |
||||
setupcmd[k].token, bus, addr); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
return res; |
||||
} |
||||
|
||||
int setup_88e1518(const char *bus, unsigned char addr) |
||||
{ |
||||
int res; |
||||
|
||||
res = process_setup(bus, addr, |
||||
verify_88e1518, ARRAY_SIZE(verify_88e1518)); |
||||
if (res) |
||||
return res; |
||||
|
||||
res = process_setup(bus, addr, |
||||
fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); |
||||
if (res) |
||||
return res; |
||||
|
||||
res = process_setup(bus, addr, |
||||
default_88e1518, ARRAY_SIZE(default_88e1518)); |
||||
if (res) |
||||
return res; |
||||
|
||||
if (addr) { |
||||
res = process_setup(bus, addr, |
||||
ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); |
||||
if (res) |
||||
return res; |
||||
} |
||||
|
||||
res = process_setup(bus, addr, |
||||
swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); |
||||
if (res) |
||||
return res; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int setup_88e1514(const char *bus, unsigned char addr) |
||||
{ |
||||
int res; |
||||
|
||||
res = process_setup(bus, addr, |
||||
verify_88e1518, ARRAY_SIZE(verify_88e1518)); |
||||
if (res) |
||||
return res; |
||||
|
||||
res = process_setup(bus, addr, |
||||
fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); |
||||
if (res) |
||||
return res; |
||||
|
||||
res = process_setup(bus, addr, |
||||
mii_to_copper_88e1514, |
||||
ARRAY_SIZE(mii_to_copper_88e1514)); |
||||
if (res) |
||||
return res; |
||||
|
||||
res = process_setup(bus, addr, |
||||
sgmii_autoneg_off_88e1518, |
||||
ARRAY_SIZE(sgmii_autoneg_off_88e1518)); |
||||
if (res) |
||||
return res; |
||||
|
||||
res = process_setup(bus, addr, |
||||
invert_led2_88e1514, |
||||
ARRAY_SIZE(invert_led2_88e1514)); |
||||
if (res) |
||||
return res; |
||||
|
||||
res = process_setup(bus, addr, |
||||
default_88e1518, ARRAY_SIZE(default_88e1518)); |
||||
if (res) |
||||
return res; |
||||
|
||||
if (addr) { |
||||
res = process_setup(bus, addr, |
||||
ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); |
||||
if (res) |
||||
return res; |
||||
} |
||||
|
||||
res = process_setup(bus, addr, |
||||
swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); |
||||
if (res) |
||||
return res; |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,14 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _PHY_H_ |
||||
#define _PHY_H_ |
||||
|
||||
int setup_88e1514(const char *bus, unsigned char addr); |
||||
int setup_88e1518(const char *bus, unsigned char addr); |
||||
|
||||
#endif |
||||
@ -0,0 +1,12 @@ |
||||
if TARGET_HRCON |
||||
|
||||
config SYS_BOARD |
||||
default "mpc8308" |
||||
|
||||
config SYS_VENDOR |
||||
default "gdsys" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "hrcon" |
||||
|
||||
endif |
||||
@ -0,0 +1,6 @@ |
||||
MPC8308 BOARD |
||||
M: Dirk Eibach <eibach@gdsys.de> |
||||
S: Maintained |
||||
F: board/gdsys/mpc8308/ |
||||
F: include/configs/hrcon.h |
||||
F: configs/hrcon_defconfig |
||||
@ -0,0 +1,9 @@ |
||||
#
|
||||
# (C) Copyright 2014
|
||||
# Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mpc8308.o sdram.o
|
||||
obj-$(CONFIG_HRCON) += hrcon.o
|
||||
@ -0,0 +1,675 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <hwconfig.h> |
||||
#include <i2c.h> |
||||
#include <spi.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <pci.h> |
||||
#include <mpc83xx.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <asm/io.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_mpc83xx_serdes.h> |
||||
|
||||
#include "mpc8308.h" |
||||
|
||||
#include <gdsys_fpga.h> |
||||
|
||||
#include "../common/osd.h" |
||||
#include "../common/mclink.h" |
||||
#include "../common/phy.h" |
||||
|
||||
#include <pca953x.h> |
||||
#include <pca9698.h> |
||||
|
||||
#include <miiphy.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define MAX_MUX_CHANNELS 2 |
||||
|
||||
enum { |
||||
UNITTYPE_MAIN_SERVER = 0, |
||||
UNITTYPE_MAIN_USER = 1, |
||||
UNITTYPE_VIDEO_SERVER = 2, |
||||
UNITTYPE_VIDEO_USER = 3, |
||||
}; |
||||
|
||||
enum { |
||||
UNITTYPEPCB_DVI = 0, |
||||
UNITTYPEPCB_DP_165 = 1, |
||||
UNITTYPEPCB_DP_300 = 2, |
||||
UNITTYPEPCB_HDMI = 3, |
||||
}; |
||||
|
||||
enum { |
||||
HWVER_100 = 0, |
||||
HWVER_110 = 1, |
||||
}; |
||||
|
||||
enum { |
||||
FPGA_HWVER_200 = 0, |
||||
FPGA_HWVER_210 = 1, |
||||
}; |
||||
|
||||
enum { |
||||
COMPRESSION_NONE = 0, |
||||
COMPRESSION_TYPE1_DELTA = 1, |
||||
COMPRESSION_TYPE1_TYPE2_DELTA = 3, |
||||
}; |
||||
|
||||
enum { |
||||
AUDIO_NONE = 0, |
||||
AUDIO_TX = 1, |
||||
AUDIO_RX = 2, |
||||
AUDIO_RXTX = 3, |
||||
}; |
||||
|
||||
enum { |
||||
SYSCLK_147456 = 0, |
||||
}; |
||||
|
||||
enum { |
||||
RAM_DDR2_32 = 0, |
||||
RAM_DDR3_32 = 1, |
||||
}; |
||||
|
||||
enum { |
||||
CARRIER_SPEED_1G = 0, |
||||
CARRIER_SPEED_2_5G = 1, |
||||
}; |
||||
|
||||
enum { |
||||
MCFPGA_DONE = 1 << 0, |
||||
MCFPGA_INIT_N = 1 << 1, |
||||
MCFPGA_PROGRAM_N = 1 << 2, |
||||
MCFPGA_UPDATE_ENABLE_N = 1 << 3, |
||||
MCFPGA_RESET_N = 1 << 4, |
||||
}; |
||||
|
||||
enum { |
||||
GPIO_MDC = 1 << 14, |
||||
GPIO_MDIO = 1 << 15, |
||||
}; |
||||
|
||||
unsigned int mclink_fpgacount; |
||||
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; |
||||
|
||||
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) |
||||
{ |
||||
int res; |
||||
|
||||
switch (fpga) { |
||||
case 0: |
||||
out_le16(reg, data); |
||||
break; |
||||
default: |
||||
res = mclink_send(fpga - 1, regoff, data); |
||||
if (res < 0) { |
||||
printf("mclink_send reg %02lx data %04x returned %d\n", |
||||
regoff, data, res); |
||||
return res; |
||||
} |
||||
break; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) |
||||
{ |
||||
int res; |
||||
|
||||
switch (fpga) { |
||||
case 0: |
||||
*data = in_le16(reg); |
||||
break; |
||||
default: |
||||
if (fpga > mclink_fpgacount) |
||||
return -EINVAL; |
||||
res = mclink_receive(fpga - 1, regoff, data); |
||||
if (res < 0) { |
||||
printf("mclink_receive reg %02lx returned %d\n", |
||||
regoff, res); |
||||
return res; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
char *s = getenv("serial#"); |
||||
bool hw_type_cat = pca9698_get_value(0x20, 20); |
||||
|
||||
puts("Board: "); |
||||
|
||||
printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); |
||||
|
||||
if (s != NULL) { |
||||
puts(", serial# "); |
||||
puts(s); |
||||
} |
||||
|
||||
puts("\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void print_fpga_info(unsigned int fpga, bool rgmii2_present) |
||||
{ |
||||
u16 versions; |
||||
u16 fpga_version; |
||||
u16 fpga_features; |
||||
unsigned unit_type; |
||||
unsigned unit_type_pcb_video; |
||||
unsigned hardware_version; |
||||
unsigned feature_compression; |
||||
unsigned feature_osd; |
||||
unsigned feature_audio; |
||||
unsigned feature_sysclock; |
||||
unsigned feature_ramconfig; |
||||
unsigned feature_carrier_speed; |
||||
unsigned feature_carriers; |
||||
unsigned feature_video_channels; |
||||
|
||||
FPGA_GET_REG(fpga, versions, &versions); |
||||
FPGA_GET_REG(fpga, fpga_version, &fpga_version); |
||||
FPGA_GET_REG(fpga, fpga_features, &fpga_features); |
||||
|
||||
unit_type = (versions & 0xf000) >> 12; |
||||
unit_type_pcb_video = (versions & 0x01c0) >> 6; |
||||
feature_compression = (fpga_features & 0xe000) >> 13; |
||||
feature_osd = fpga_features & (1<<11); |
||||
feature_audio = (fpga_features & 0x0600) >> 9; |
||||
feature_sysclock = (fpga_features & 0x0180) >> 7; |
||||
feature_ramconfig = (fpga_features & 0x0060) >> 5; |
||||
feature_carrier_speed = fpga_features & (1<<4); |
||||
feature_carriers = (fpga_features & 0x000c) >> 2; |
||||
feature_video_channels = fpga_features & 0x0003; |
||||
|
||||
switch (unit_type) { |
||||
case UNITTYPE_MAIN_USER: |
||||
printf("Mainchannel"); |
||||
break; |
||||
|
||||
case UNITTYPE_VIDEO_USER: |
||||
printf("Videochannel"); |
||||
break; |
||||
|
||||
default: |
||||
printf("UnitType %d(not supported)", unit_type); |
||||
break; |
||||
} |
||||
|
||||
if (unit_type == UNITTYPE_MAIN_USER) { |
||||
hardware_version = |
||||
(!!pca9698_get_value(0x20, 24) << 0) |
||||
| (!!pca9698_get_value(0x20, 25) << 1) |
||||
| (!!pca9698_get_value(0x20, 26) << 2) |
||||
| (!!pca9698_get_value(0x20, 27) << 3) |
||||
| (!!pca9698_get_value(0x20, 28) << 4); |
||||
switch (hardware_version) { |
||||
case HWVER_100: |
||||
printf(" HW-Ver 1.00,"); |
||||
break; |
||||
|
||||
case HWVER_110: |
||||
printf(" HW-Ver 1.10,"); |
||||
break; |
||||
|
||||
default: |
||||
printf(" HW-Ver %d(not supported),", |
||||
hardware_version); |
||||
break; |
||||
} |
||||
if (rgmii2_present) |
||||
printf(" RGMII2,"); |
||||
} |
||||
|
||||
if (unit_type == UNITTYPE_VIDEO_USER) { |
||||
hardware_version = versions & 0x000f; |
||||
switch (hardware_version) { |
||||
case FPGA_HWVER_200: |
||||
printf(" HW-Ver 2.00,"); |
||||
break; |
||||
|
||||
case FPGA_HWVER_210: |
||||
printf(" HW-Ver 2.10,"); |
||||
break; |
||||
|
||||
default: |
||||
printf(" HW-Ver %d(not supported),", |
||||
hardware_version); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
switch (unit_type_pcb_video) { |
||||
case UNITTYPEPCB_DVI: |
||||
printf(" DVI,"); |
||||
break; |
||||
|
||||
case UNITTYPEPCB_DP_165: |
||||
printf(" DP 165MPix/s,"); |
||||
break; |
||||
|
||||
case UNITTYPEPCB_DP_300: |
||||
printf(" DP 300MPix/s,"); |
||||
break; |
||||
|
||||
case UNITTYPEPCB_HDMI: |
||||
printf(" HDMI,"); |
||||
break; |
||||
} |
||||
|
||||
printf(" FPGA V %d.%02d\n features:", |
||||
fpga_version / 100, fpga_version % 100); |
||||
|
||||
|
||||
switch (feature_compression) { |
||||
case COMPRESSION_NONE: |
||||
printf(" no compression"); |
||||
break; |
||||
|
||||
case COMPRESSION_TYPE1_DELTA: |
||||
printf(" type1-deltacompression"); |
||||
break; |
||||
|
||||
case COMPRESSION_TYPE1_TYPE2_DELTA: |
||||
printf(" type1-deltacompression, type2-inlinecompression"); |
||||
break; |
||||
|
||||
default: |
||||
printf(" compression %d(not supported)", feature_compression); |
||||
break; |
||||
} |
||||
|
||||
printf(", %sosd", feature_osd ? "" : "no "); |
||||
|
||||
switch (feature_audio) { |
||||
case AUDIO_NONE: |
||||
printf(", no audio"); |
||||
break; |
||||
|
||||
case AUDIO_TX: |
||||
printf(", audio tx"); |
||||
break; |
||||
|
||||
case AUDIO_RX: |
||||
printf(", audio rx"); |
||||
break; |
||||
|
||||
case AUDIO_RXTX: |
||||
printf(", audio rx+tx"); |
||||
break; |
||||
|
||||
default: |
||||
printf(", audio %d(not supported)", feature_audio); |
||||
break; |
||||
} |
||||
|
||||
puts(",\n "); |
||||
|
||||
switch (feature_sysclock) { |
||||
case SYSCLK_147456: |
||||
printf("clock 147.456 MHz"); |
||||
break; |
||||
|
||||
default: |
||||
printf("clock %d(not supported)", feature_sysclock); |
||||
break; |
||||
} |
||||
|
||||
switch (feature_ramconfig) { |
||||
case RAM_DDR2_32: |
||||
printf(", RAM 32 bit DDR2"); |
||||
break; |
||||
|
||||
case RAM_DDR3_32: |
||||
printf(", RAM 32 bit DDR3"); |
||||
break; |
||||
|
||||
default: |
||||
printf(", RAM %d(not supported)", feature_ramconfig); |
||||
break; |
||||
} |
||||
|
||||
printf(", %d carrier(s) %s", feature_carriers, |
||||
feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); |
||||
|
||||
printf(", %d video channel(s)\n", feature_video_channels); |
||||
} |
||||
|
||||
int last_stage_init(void) |
||||
{ |
||||
int slaves; |
||||
unsigned int k; |
||||
unsigned int mux_ch; |
||||
unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; |
||||
u16 fpga_features; |
||||
bool hw_type_cat = pca9698_get_value(0x20, 20); |
||||
bool ch0_rgmii2_present = false; |
||||
|
||||
FPGA_GET_REG(0, fpga_features, &fpga_features); |
||||
|
||||
/* Turn on Parade DP501 */ |
||||
pca9698_direction_output(0x20, 10, 1); |
||||
|
||||
ch0_rgmii2_present = !pca9698_get_value(0x20, 30); |
||||
|
||||
/* wait for FPGA done */ |
||||
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { |
||||
unsigned int ctr = 0; |
||||
|
||||
if (i2c_probe(mclink_controllers[k])) |
||||
continue; |
||||
|
||||
while (!(pca953x_get_val(mclink_controllers[k]) |
||||
& MCFPGA_DONE)) { |
||||
udelay(100000); |
||||
if (ctr++ > 5) { |
||||
printf("no done for mclink_controller %d\n", k); |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
if (hw_type_cat) { |
||||
miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, |
||||
bb_miiphy_write); |
||||
for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { |
||||
if ((mux_ch == 1) && !ch0_rgmii2_present) |
||||
continue; |
||||
|
||||
setup_88e1514(bb_miiphy_buses[0].name, mux_ch); |
||||
} |
||||
} |
||||
|
||||
/* give slave-PLLs and Parade DP501 some time to be up and running */ |
||||
udelay(500000); |
||||
|
||||
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; |
||||
slaves = mclink_probe(); |
||||
mclink_fpgacount = 0; |
||||
|
||||
print_fpga_info(0, ch0_rgmii2_present); |
||||
osd_probe(0); |
||||
|
||||
if (slaves <= 0) |
||||
return 0; |
||||
|
||||
mclink_fpgacount = slaves; |
||||
|
||||
for (k = 1; k <= slaves; ++k) { |
||||
FPGA_GET_REG(k, fpga_features, &fpga_features); |
||||
|
||||
print_fpga_info(k, false); |
||||
osd_probe(k); |
||||
if (hw_type_cat) { |
||||
miiphy_register(bb_miiphy_buses[k].name, |
||||
bb_miiphy_read, bb_miiphy_write); |
||||
setup_88e1514(bb_miiphy_buses[k].name, 0); |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* provide access to fpga gpios (for I2C bitbang) |
||||
* (these may look all too simple but make iocon.h much more readable) |
||||
*/ |
||||
void fpga_gpio_set(unsigned int bus, int pin) |
||||
{ |
||||
FPGA_SET_REG(bus, gpio.set, pin); |
||||
} |
||||
|
||||
void fpga_gpio_clear(unsigned int bus, int pin) |
||||
{ |
||||
FPGA_SET_REG(bus, gpio.clear, pin); |
||||
} |
||||
|
||||
int fpga_gpio_get(unsigned int bus, int pin) |
||||
{ |
||||
u16 val; |
||||
|
||||
FPGA_GET_REG(bus, gpio.read, &val); |
||||
|
||||
return val & pin; |
||||
} |
||||
|
||||
void mpc8308_init(void) |
||||
{ |
||||
pca9698_direction_output(0x20, 4, 1); |
||||
} |
||||
|
||||
void mpc8308_set_fpga_reset(unsigned state) |
||||
{ |
||||
pca9698_set_value(0x20, 4, state ? 0 : 1); |
||||
} |
||||
|
||||
void mpc8308_setup_hw(void) |
||||
{ |
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
||||
|
||||
/*
|
||||
* set "startup-finished"-gpios |
||||
*/ |
||||
setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); |
||||
setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); |
||||
} |
||||
|
||||
int mpc8308_get_fpga_done(unsigned fpga) |
||||
{ |
||||
return pca9698_get_value(0x20, 19); |
||||
} |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
int board_mmc_init(bd_t *bd) |
||||
{ |
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
||||
sysconf83xx_t *sysconf = &immr->sysconf; |
||||
|
||||
/* Enable cache snooping in eSDHC system configuration register */ |
||||
out_be32(&sysconf->sdhccr, 0x02000000); |
||||
|
||||
return fsl_esdhc_mmc_init(bd); |
||||
} |
||||
#endif |
||||
|
||||
static struct pci_region pcie_regions_0[] = { |
||||
{ |
||||
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE, |
||||
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
.size = CONFIG_SYS_PCIE1_MEM_SIZE, |
||||
.flags = PCI_REGION_MEM, |
||||
}, |
||||
{ |
||||
.bus_start = CONFIG_SYS_PCIE1_IO_BASE, |
||||
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS, |
||||
.size = CONFIG_SYS_PCIE1_IO_SIZE, |
||||
.flags = PCI_REGION_IO, |
||||
}, |
||||
}; |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
||||
sysconf83xx_t *sysconf = &immr->sysconf; |
||||
law83xx_t *pcie_law = sysconf->pcielaw; |
||||
struct pci_region *pcie_reg[] = { pcie_regions_0 }; |
||||
|
||||
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, |
||||
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); |
||||
|
||||
/* Deassert the resets in the control register */ |
||||
out_be32(&sysconf->pecr1, 0xE0008000); |
||||
udelay(2000); |
||||
|
||||
/* Configure PCI Express Local Access Windows */ |
||||
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); |
||||
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); |
||||
|
||||
mpc83xx_pcie_init(1, pcie_reg); |
||||
} |
||||
|
||||
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) |
||||
{ |
||||
info->portwidth = FLASH_CFI_16BIT; |
||||
info->chipwidth = FLASH_CFI_BY16; |
||||
info->interface = FLASH_CFI_X16; |
||||
return 1; |
||||
} |
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) |
||||
void ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
ft_cpu_setup(blob, bd); |
||||
fdt_fixup_dr_usb(blob, bd); |
||||
fdt_fixup_esdhc(blob, bd); |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* FPGA MII bitbang implementation |
||||
*/ |
||||
|
||||
struct fpga_mii { |
||||
unsigned fpga; |
||||
int mdio; |
||||
} fpga_mii[] = { |
||||
{ 0, 1}, |
||||
{ 1, 1}, |
||||
{ 2, 1}, |
||||
{ 3, 1}, |
||||
}; |
||||
|
||||
static int mii_dummy_init(struct bb_miiphy_bus *bus) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
static int mii_mdio_active(struct bb_miiphy_bus *bus) |
||||
{ |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
if (fpga_mii->mdio) |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); |
||||
else |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_mdio_tristate(struct bb_miiphy_bus *bus) |
||||
{ |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) |
||||
{ |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
if (v) |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); |
||||
else |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); |
||||
|
||||
fpga_mii->mdio = v; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) |
||||
{ |
||||
u16 gpio; |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); |
||||
|
||||
*v = ((gpio & GPIO_MDIO) != 0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) |
||||
{ |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
if (v) |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); |
||||
else |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_delay(struct bb_miiphy_bus *bus) |
||||
{ |
||||
udelay(1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
struct bb_miiphy_bus bb_miiphy_buses[] = { |
||||
{ |
||||
.name = "board0", |
||||
.init = mii_dummy_init, |
||||
.mdio_active = mii_mdio_active, |
||||
.mdio_tristate = mii_mdio_tristate, |
||||
.set_mdio = mii_set_mdio, |
||||
.get_mdio = mii_get_mdio, |
||||
.set_mdc = mii_set_mdc, |
||||
.delay = mii_delay, |
||||
.priv = &fpga_mii[0], |
||||
}, |
||||
{ |
||||
.name = "board1", |
||||
.init = mii_dummy_init, |
||||
.mdio_active = mii_mdio_active, |
||||
.mdio_tristate = mii_mdio_tristate, |
||||
.set_mdio = mii_set_mdio, |
||||
.get_mdio = mii_get_mdio, |
||||
.set_mdc = mii_set_mdc, |
||||
.delay = mii_delay, |
||||
.priv = &fpga_mii[1], |
||||
}, |
||||
{ |
||||
.name = "board2", |
||||
.init = mii_dummy_init, |
||||
.mdio_active = mii_mdio_active, |
||||
.mdio_tristate = mii_mdio_tristate, |
||||
.set_mdio = mii_set_mdio, |
||||
.get_mdio = mii_get_mdio, |
||||
.set_mdc = mii_set_mdc, |
||||
.delay = mii_delay, |
||||
.priv = &fpga_mii[2], |
||||
}, |
||||
{ |
||||
.name = "board3", |
||||
.init = mii_dummy_init, |
||||
.mdio_active = mii_mdio_active, |
||||
.mdio_tristate = mii_mdio_tristate, |
||||
.set_mdio = mii_set_mdio, |
||||
.get_mdio = mii_get_mdio, |
||||
.set_mdc = mii_set_mdc, |
||||
.delay = mii_delay, |
||||
.priv = &fpga_mii[3], |
||||
}, |
||||
}; |
||||
|
||||
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / |
||||
sizeof(bb_miiphy_buses[0]); |
||||
@ -0,0 +1,109 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include <asm/ppc4xx-gpio.h> |
||||
#include <asm/global_data.h> |
||||
|
||||
#include "mpc8308.h" |
||||
#include <gdsys_fpga.h> |
||||
|
||||
#define REFLECTION_TESTPATTERN 0xdede |
||||
#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) |
||||
|
||||
#ifdef CONFIG_SYS_FPGA_NO_RFL_HI |
||||
#define REFLECTION_TESTREG reflection_low |
||||
#else |
||||
#define REFLECTION_TESTREG reflection_high |
||||
#endif |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int get_fpga_state(unsigned dev) |
||||
{ |
||||
return gd->arch.fpga_state[dev]; |
||||
} |
||||
|
||||
void print_fpga_state(unsigned dev) |
||||
{ |
||||
if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) |
||||
puts(" Waiting for FPGA-DONE timed out.\n"); |
||||
if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) |
||||
puts(" FPGA reflection test failed.\n"); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
unsigned k; |
||||
|
||||
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) |
||||
gd->arch.fpga_state[k] = 0; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
unsigned k; |
||||
unsigned ctr; |
||||
|
||||
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) |
||||
gd->arch.fpga_state[k] = 0; |
||||
|
||||
/*
|
||||
* reset FPGA |
||||
*/ |
||||
mpc8308_init(); |
||||
|
||||
mpc8308_set_fpga_reset(1); |
||||
|
||||
mpc8308_setup_hw(); |
||||
|
||||
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { |
||||
ctr = 0; |
||||
while (!mpc8308_get_fpga_done(k)) { |
||||
udelay(100000); |
||||
if (ctr++ > 5) { |
||||
gd->arch.fpga_state[k] |= |
||||
FPGA_STATE_DONE_FAILED; |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
udelay(10); |
||||
|
||||
mpc8308_set_fpga_reset(0); |
||||
|
||||
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { |
||||
/*
|
||||
* wait for fpga out of reset |
||||
*/ |
||||
ctr = 0; |
||||
while (1) { |
||||
u16 val; |
||||
|
||||
FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); |
||||
|
||||
FPGA_GET_REG(k, REFLECTION_TESTREG, &val); |
||||
if (val == REFLECTION_TESTPATTERN_INV) |
||||
break; |
||||
|
||||
udelay(100000); |
||||
if (ctr++ > 5) { |
||||
gd->arch.fpga_state[k] |= |
||||
FPGA_STATE_REFLECTION_FAILED; |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,10 @@ |
||||
#ifndef __MPC8308_H_ |
||||
#define __MPC8308_H_ |
||||
|
||||
/* functions to be provided by board implementation */ |
||||
void mpc8308_init(void); |
||||
void mpc8308_set_fpga_reset(unsigned state); |
||||
void mpc8308_setup_hw(void); |
||||
int mpc8308_get_fpga_done(unsigned fpga); |
||||
|
||||
#endif /* __MPC8308_H_ */ |
||||
@ -0,0 +1,82 @@ |
||||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc. |
||||
* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com |
||||
* |
||||
* Authors: Nick.Spence@freescale.com |
||||
* Wilson.Lo@freescale.com |
||||
* scottwood@freescale.com |
||||
* |
||||
* This files is mostly identical to the original from |
||||
* board\freescale\mpc8315erdb\sdram.c |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc83xx.h> |
||||
#include <spd_sdram.h> |
||||
|
||||
#include <asm/bitops.h> |
||||
#include <asm/io.h> |
||||
|
||||
#include <asm/processor.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* Fixed sdram init -- doesn't use serial presence detect.
|
||||
* |
||||
* This is useful for faster booting in configs where the RAM is unlikely |
||||
* to be changed, or for things like NAND booting where space is tight. |
||||
*/ |
||||
static long fixed_sdram(void) |
||||
{ |
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
||||
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; |
||||
u32 msize_log2 = __ilog2(msize); |
||||
|
||||
out_be32(&im->sysconf.ddrlaw[0].bar, |
||||
CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); |
||||
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); |
||||
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); |
||||
|
||||
out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); |
||||
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); |
||||
|
||||
/* Currently we use only one CS, so disable the other bank. */ |
||||
out_be32(&im->ddr.cs_config[1], 0); |
||||
|
||||
out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); |
||||
out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); |
||||
out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); |
||||
out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); |
||||
out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); |
||||
|
||||
out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); |
||||
out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); |
||||
out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); |
||||
out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); |
||||
|
||||
out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); |
||||
sync(); |
||||
|
||||
/* enable DDR controller */ |
||||
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); |
||||
sync(); |
||||
|
||||
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
||||
u32 msize; |
||||
|
||||
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) |
||||
return -1; |
||||
|
||||
/* DDR SDRAM */ |
||||
msize = fixed_sdram(); |
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */ |
||||
return msize; |
||||
} |
||||
@ -0,0 +1,3 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_HRCON=y |
||||
@ -0,0 +1,614 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 family */ |
||||
#define CONFIG_MPC83xx 1 /* MPC83xx family */ |
||||
#define CONFIG_MPC830x 1 /* MPC830x family */ |
||||
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ |
||||
#define CONFIG_HRCON 1 /* HRCON board specific */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000 |
||||
|
||||
#define CONFIG_IDENT_STRING " hrcon 0.01" |
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_EARLY_INIT_R |
||||
#define CONFIG_LAST_STAGE_INIT |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT 1 |
||||
#define CONFIG_FIT_VERBOSE 1 |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
||||
|
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_EXT2 |
||||
|
||||
#define CONFIG_CMD_FPGAD |
||||
#define CONFIG_CMD_IOLOOP |
||||
|
||||
/*
|
||||
* System Clock Setup |
||||
*/ |
||||
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN |
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word |
||||
* if CLKIN is 66.66MHz, then |
||||
* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz |
||||
* We choose the A type silicon as default, so the core is 400Mhz. |
||||
*/ |
||||
#define CONFIG_SYS_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_2X1 |\
|
||||
HRCWL_SVCOD_DIV_2 |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 |\
|
||||
HRCWL_CORE_TO_CSB_3X1) |
||||
/*
|
||||
* There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits |
||||
* in 8308's HRCWH according to the manual, but original Freescale's |
||||
* code has them and I've expirienced some problems using the board |
||||
* with BDI3000 attached when I've tried to set these bits to zero |
||||
* (UART doesn't work after the 'reset run' command). |
||||
*/ |
||||
#define CONFIG_SYS_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_RGMII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN) |
||||
|
||||
/*
|
||||
* System IO Config |
||||
*/ |
||||
#define CONFIG_SYS_SICRH (\ |
||||
SICRH_ESDHC_A_SD |\
|
||||
SICRH_ESDHC_B_SD |\
|
||||
SICRH_ESDHC_C_SD |\
|
||||
SICRH_GPIO_A_GPIO |\
|
||||
SICRH_GPIO_B_GPIO |\
|
||||
SICRH_IEEE1588_A_GPIO |\
|
||||
SICRH_USB |\
|
||||
SICRH_GTM_GPIO |\
|
||||
SICRH_IEEE1588_B_GPIO |\
|
||||
SICRH_ETSEC2_GPIO |\
|
||||
SICRH_GPIOSEL_1 |\
|
||||
SICRH_TMROBI_V3P3 |\
|
||||
SICRH_TSOBI1_V2P5 |\
|
||||
SICRH_TSOBI2_V2P5) /* 0x0037f103 */ |
||||
#define CONFIG_SYS_SICRL (\ |
||||
SICRL_SPI_PF0 |\
|
||||
SICRL_UART_PF0 |\
|
||||
SICRL_IRQ_PF0 |\
|
||||
SICRL_I2C2_PF0 |\
|
||||
SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ |
||||
|
||||
/*
|
||||
* IMMR new address |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xE0000000 |
||||
|
||||
/*
|
||||
* SERDES |
||||
*/ |
||||
#define CONFIG_FSL_SERDES |
||||
#define CONFIG_FSL_SERDES1 0xe3000 |
||||
|
||||
/*
|
||||
* Arbiter Setup |
||||
*/ |
||||
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
||||
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
||||
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
||||
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
||||
| DDRCDR_PZ_LOZ \
|
||||
| DDRCDR_NZ_LOZ \
|
||||
| DDRCDR_ODT \
|
||||
| DDRCDR_Q_DRN) |
||||
/* 0x7b880001 */ |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
* consist of one chip NT5TU64M16HG from NANYA |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 |
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
||||
| CSCONFIG_ODT_RD_NEVER \
|
||||
| CSCONFIG_ODT_WR_ONLY_CURRENT \
|
||||
| CSCONFIG_BANK_BIT_3 \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
||||
/* 0x80010102 */ |
||||
#define CONFIG_SYS_DDR_TIMING_3 0 |
||||
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
||||
| (0 << TIMING_CFG0_WRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_RRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WWT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
|
||||
| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
|
||||
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_MRS_CYC_SHIFT)) |
||||
/* 0x00260802 */ |
||||
#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
||||
| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
|
||||
| (7 << TIMING_CFG1_CASLAT_SHIFT) \
|
||||
| (9 << TIMING_CFG1_REFREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRTORD_SHIFT)) |
||||
/* 0x26279222 */ |
||||
#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
||||
| (4 << TIMING_CFG2_CPO_SHIFT) \
|
||||
| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
|
||||
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
|
||||
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
|
||||
| (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) |
||||
/* 0x021848c5 */ |
||||
#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
||||
| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) |
||||
/* 0x08240100 */ |
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_DBW_16) |
||||
/* 0x43100000 */ |
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ |
||||
#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ |
||||
| (0x0242 << SDRAM_MODE_SD_SHIFT)) |
||||
/* ODT 150ohm CL=4, AL=0 on SDRAM */ |
||||
#define CONFIG_SYS_DDR_MODE2 0x00000000 |
||||
|
||||
/*
|
||||
* Memory test |
||||
*/ |
||||
#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x07f00000 |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 |
||||
#define CONFIG_SYS_LBC_LBCR 0x00040000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#if 1 |
||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
#define CONFIG_FLASH_CFI_LEGACY |
||||
#define CONFIG_SYS_FLASH_LEGACY_512Kx16 |
||||
#else |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
||||
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
||||
|
||||
/* Window base at flash base */ |
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ |
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET) |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 135 |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
/*
|
||||
* FPGA |
||||
*/ |
||||
#define CONFIG_SYS_FPGA0_BASE 0xE0600000 |
||||
#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ |
||||
|
||||
/* Window base at FPGA base */ |
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE |
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) |
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ |
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ |
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET) |
||||
|
||||
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE |
||||
#define CONFIG_SYS_FPGA_DONE(k) 0x0010 |
||||
|
||||
#define CONFIG_SYS_FPGA_COUNT 1 |
||||
|
||||
#define CONFIG_SYS_MCLINK_MAX 3 |
||||
|
||||
#define CONFIG_SYS_FPGA_PTR \ |
||||
{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 2 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
/* Pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_FSL |
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 |
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
||||
|
||||
#define CONFIG_PCA953X /* NXP PCA9554 */ |
||||
#define CONFIG_PCA9698 /* NXP PCA9698 */ |
||||
|
||||
#define CONFIG_SYS_I2C_IHS |
||||
#define CONFIG_SYS_I2C_IHS_CH0 |
||||
#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 |
||||
#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F |
||||
#define CONFIG_SYS_I2C_IHS_CH1 |
||||
#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 |
||||
#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F |
||||
#define CONFIG_SYS_I2C_IHS_CH2 |
||||
#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 |
||||
#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F |
||||
#define CONFIG_SYS_I2C_IHS_CH3 |
||||
#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 |
||||
#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F |
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define CONFIG_SYS_I2C_SOFT |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F |
||||
#define I2C_SOFT_DECLARATIONS2 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F |
||||
#define I2C_SOFT_DECLARATIONS3 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F |
||||
#define I2C_SOFT_DECLARATIONS4 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F |
||||
|
||||
#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} |
||||
#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} |
||||
#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
void fpga_gpio_set(unsigned int bus, int pin); |
||||
void fpga_gpio_clear(unsigned int bus, int pin); |
||||
int fpga_gpio_get(unsigned int bus, int pin); |
||||
#endif |
||||
|
||||
#define I2C_ACTIVE { } |
||||
#define I2C_TRISTATE { } |
||||
#define I2C_READ \ |
||||
(fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0) |
||||
#define I2C_SDA(bit) \ |
||||
do { \
|
||||
if (bit) \
|
||||
fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
|
||||
else \
|
||||
fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
|
||||
} while (0) |
||||
#define I2C_SCL(bit) \ |
||||
do { \
|
||||
if (bit) \
|
||||
fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
|
||||
else \
|
||||
fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
|
||||
} while (0) |
||||
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ |
||||
|
||||
/*
|
||||
* Software (bit-bang) MII driver configuration |
||||
*/ |
||||
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
||||
#define CONFIG_BITBANGMII_MULTI |
||||
|
||||
/*
|
||||
* OSD Setup |
||||
*/ |
||||
#define CONFIG_SYS_OSD_SCREENS 1 |
||||
#define CONFIG_SYS_DP501_DIFFERENTIAL |
||||
#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 |
||||
#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 |
||||
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 |
||||
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 |
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 |
||||
|
||||
/* enable PCIE clock */ |
||||
#define CONFIG_SYS_SCCR_PCIEXP1CM 1 |
||||
|
||||
#define CONFIG_PCI |
||||
#define CONFIG_PCI_INDIRECT_BRIDGE |
||||
#define CONFIG_PCIE |
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 |
||||
|
||||
/*
|
||||
* TSEC |
||||
*/ |
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
||||
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
||||
|
||||
/*
|
||||
* TSEC ethernet configuration |
||||
*/ |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_TSEC1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC0" |
||||
#define TSEC1_PHY_ADDR 1 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC1_FLAGS TSEC_GIGABIT |
||||
|
||||
/* Options are: eTSEC[0-1] */ |
||||
#define CONFIG_ETHPRIME "eTSEC0" |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#if 1 |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
||||
CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
#else |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_PING |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ |
||||
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
||||
#define CONFIG_AUTOBOOT_STOP_STR " " |
||||
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 256 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CONFIG_SYS_HID0_INIT 0x000000000 |
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
||||
HID0_ENABLE_INSTRUCTION_CACHE | \
|
||||
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
||||
#define CONFIG_SYS_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
/* DDR: cache cacheable */ |
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ |
||||
BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
||||
|
||||
/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ |
||||
BATU_VP) |
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ |
||||
BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ |
||||
BATL_CACHEINHIBIT | \
|
||||
BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_HAS_ETH0 |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
||||
|
||||
#define CONFIG_HOSTNAME hrcon |
||||
#define CONFIG_ROOTPATH "/opt/nfsroot" |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS1\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"kernel_addr=1000000\0" \
|
||||
"fdt_addr=C00000\0" \
|
||||
"fdtfile=hrcon.dtb\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
|
||||
" +${filesize};cp.b ${fileaddr} " \
|
||||
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
|
||||
"upd=run load update\0" \
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp ${kernel_addr} $bootfile;" \
|
||||
"tftp ${fdt_addr} $fdtfile;" \
|
||||
"bootm ${kernel_addr} - ${fdt_addr}" |
||||
|
||||
#define CONFIG_MMCBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
|
||||
"ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
|
||||
"bootm ${kernel_addr} - ${fdt_addr}" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue