Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile include/configs/trats.h include/configs/trats2.h include/mmc.hmaster
commit
519fdde9e6
@ -1,71 +0,0 @@ |
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/*
|
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* This program is used to generate definitions needed by |
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* assembly language modules. |
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* |
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* We use the technique used in the OSF Mach kernel code: |
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* generate asm statements containing #defines, |
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* compile this file to assembler, and then extract the |
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* #defines from the assembly-language output. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/imx-regs.h> |
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|
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#include <linux/kbuild.h> |
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int main(void) |
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{ |
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/* Round up to make sure size gives nice stack alignment */ |
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DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); |
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DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); |
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DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); |
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DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); |
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DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); |
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DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); |
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DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); |
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DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); |
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DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); |
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DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); |
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DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); |
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DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); |
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DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); |
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DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); |
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DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); |
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|
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/* Multi-Layer AHB Crossbar Switch */ |
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DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); |
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DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); |
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DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); |
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DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); |
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DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); |
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DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); |
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DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); |
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DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); |
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DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); |
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DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); |
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DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); |
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DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); |
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DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); |
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DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); |
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DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); |
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DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); |
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/* AHB <-> IP-Bus Interface */ |
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DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); |
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DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); |
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DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); |
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DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); |
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DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); |
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DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); |
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DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); |
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DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); |
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DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); |
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DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); |
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DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); |
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return 0; |
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} |
@ -1,62 +0,0 @@ |
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* This program is used to generate definitions needed by |
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* assembly language modules. |
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* |
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* We use the technique used in the OSF Mach kernel code: |
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* generate asm statements containing #defines, |
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* compile this file to assembler, and then extract the |
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* #defines from the assembly-language output. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/mb86r0x.h> |
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#include <linux/kbuild.h> |
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int main(void) |
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{ |
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/* ddr2 controller */ |
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DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); |
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DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); |
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DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); |
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DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); |
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DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); |
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DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); |
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DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); |
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DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); |
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DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); |
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DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); |
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DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); |
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DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); |
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DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); |
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DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); |
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DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); |
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|
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/* clock reset generator */ |
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DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); |
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DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); |
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DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); |
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DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); |
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DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); |
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DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); |
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/* chip control module */ |
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DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); |
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/* external bus interface */ |
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DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); |
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DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); |
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DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); |
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DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); |
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DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); |
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DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); |
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DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); |
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DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); |
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DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); |
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return 0; |
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} |
@ -1,57 +0,0 @@ |
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* This program is used to generate definitions needed by |
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* assembly language modules. |
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* |
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* We use the technique used in the OSF Mach kernel code: |
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* generate asm statements containing #defines, |
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* compile this file to assembler, and then extract the |
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* #defines from the assembly-language output. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/imx-regs.h> |
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#include <linux/kbuild.h> |
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int main(void) |
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{ |
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/* Clock Control Module */ |
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DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); |
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DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); |
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DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); |
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DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); |
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DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); |
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DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); |
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/* Enhanced SDRAM Controller */ |
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DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); |
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DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); |
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DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); |
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/* Multi-Layer AHB Crossbar Switch */ |
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DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); |
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DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); |
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DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); |
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DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); |
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DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); |
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DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); |
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DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); |
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DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); |
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DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); |
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DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); |
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DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); |
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DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); |
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DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); |
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DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); |
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DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); |
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/* AHB <-> IP-Bus Interface */ |
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DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); |
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DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); |
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return 0; |
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} |
@ -1,47 +0,0 @@ |
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* This program is used to generate definitions needed by |
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* assembly language modules. |
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* |
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* We use the technique used in the OSF Mach kernel code: |
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* generate asm statements containing #defines, |
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* compile this file to assembler, and then extract the |
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* #defines from the assembly-language output. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/imx-regs.h> |
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#include <linux/kbuild.h> |
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int main(void) |
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{ |
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DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); |
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DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); |
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DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); |
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DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); |
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DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); |
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DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); |
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DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); |
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DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); |
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DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); |
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DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); |
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DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); |
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DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); |
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DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); |
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DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); |
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DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); |
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DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); |
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DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + |
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offsetof(struct system_control_regs, gpcr)); |
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DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + |
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offsetof(struct system_control_regs, fmcr)); |
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return 0; |
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} |
@ -1,73 +0,0 @@ |
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* This program is used to generate definitions needed by |
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* assembly language modules. |
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* |
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* We use the technique used in the OSF Mach kernel code: |
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* generate asm statements containing #defines, |
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* compile this file to assembler, and then extract the |
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* #defines from the assembly-language output. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/imx-regs.h> |
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|
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#include <linux/kbuild.h> |
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|
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int main(void) |
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{ |
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|
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/* Round up to make sure size gives nice stack alignment */ |
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DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); |
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DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); |
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DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); |
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DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); |
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DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); |
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DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); |
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DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); |
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DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); |
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DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); |
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DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); |
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DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); |
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DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); |
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DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); |
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DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); |
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DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); |
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DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); |
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DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); |
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DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); |
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DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); |
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DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); |
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DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); |
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DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); |
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DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); |
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DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); |
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DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); |
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DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); |
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DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); |
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DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); |
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DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); |
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DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); |
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DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); |
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DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); |
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DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); |
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DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); |
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#if defined(CONFIG_MX53) |
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DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); |
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#endif |
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|
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/* DPLL */ |
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DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); |
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DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); |
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DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); |
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DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); |
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DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); |
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DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); |
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DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); |
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DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); |
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|
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return 0; |
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} |
@ -0,0 +1,248 @@ |
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/*
|
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* This program is used to generate definitions needed by |
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* assembly language modules. |
||||
* |
||||
* We use the technique used in the OSF Mach kernel code: |
||||
* generate asm statements containing #defines, |
||||
* compile this file to assembler, and then extract the |
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* #defines from the assembly-language output. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <linux/kbuild.h> |
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|
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#if defined(CONFIG_MB86R0x) |
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#include <asm/arch/mb86r0x.h> |
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#endif |
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#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ |
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|| defined(CONFIG_MX51) || defined(CONFIG_MX53) |
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#include <asm/arch/imx-regs.h> |
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#endif |
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|
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int main(void) |
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{ |
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/*
|
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* TODO : Check if each entry in this file is really necessary. |
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* - struct mb86r0x_ddr2 |
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* - struct mb86r0x_memc |
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* - struct esdramc_regs |
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* - struct max_regs |
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* - struct aips_regs |
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* - struct aipi_regs |
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* - struct clkctl |
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* - struct dpll |
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* are used only for generating asm-offsets.h. |
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* It means their offset addresses are referenced only from assembly |
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* code. Is it better to define the macros directly in headers? |
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*/ |
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|
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#if defined(CONFIG_MB86R0x) |
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/* ddr2 controller */ |
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DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); |
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DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); |
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DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); |
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DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); |
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DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); |
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DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); |
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DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); |
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DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); |
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DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); |
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DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); |
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DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); |
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DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); |
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DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); |
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DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); |
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DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); |
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|
||||
/* clock reset generator */ |
||||
DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); |
||||
DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); |
||||
DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); |
||||
DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); |
||||
DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); |
||||
DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); |
||||
|
||||
/* chip control module */ |
||||
DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); |
||||
|
||||
/* external bus interface */ |
||||
DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); |
||||
DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); |
||||
DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); |
||||
DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); |
||||
DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); |
||||
DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); |
||||
DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); |
||||
DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); |
||||
DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MX25) |
||||
/* Clock Control Module */ |
||||
DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); |
||||
DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); |
||||
DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); |
||||
DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); |
||||
DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); |
||||
DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); |
||||
|
||||
/* Enhanced SDRAM Controller */ |
||||
DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); |
||||
DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); |
||||
DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); |
||||
|
||||
/* Multi-Layer AHB Crossbar Switch */ |
||||
DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); |
||||
DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); |
||||
DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); |
||||
DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); |
||||
DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); |
||||
DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); |
||||
DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); |
||||
DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); |
||||
DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); |
||||
DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); |
||||
DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); |
||||
DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); |
||||
DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); |
||||
DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); |
||||
DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); |
||||
|
||||
/* AHB <-> IP-Bus Interface */ |
||||
DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); |
||||
DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MX27) |
||||
DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); |
||||
DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); |
||||
DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); |
||||
DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); |
||||
|
||||
DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); |
||||
DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); |
||||
DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); |
||||
DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); |
||||
DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); |
||||
DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); |
||||
DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); |
||||
|
||||
DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); |
||||
DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); |
||||
DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); |
||||
DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); |
||||
DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); |
||||
|
||||
DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + |
||||
offsetof(struct system_control_regs, gpcr)); |
||||
DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + |
||||
offsetof(struct system_control_regs, fmcr)); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MX35) |
||||
/* Round up to make sure size gives nice stack alignment */ |
||||
DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); |
||||
DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); |
||||
DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); |
||||
DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); |
||||
DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); |
||||
DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); |
||||
DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); |
||||
DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); |
||||
DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); |
||||
DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); |
||||
DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); |
||||
DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); |
||||
DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); |
||||
DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); |
||||
DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); |
||||
|
||||
/* Multi-Layer AHB Crossbar Switch */ |
||||
DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); |
||||
DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); |
||||
DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); |
||||
DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); |
||||
DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); |
||||
DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); |
||||
DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); |
||||
DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); |
||||
DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); |
||||
DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); |
||||
DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); |
||||
DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); |
||||
DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); |
||||
DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); |
||||
DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); |
||||
DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); |
||||
|
||||
/* AHB <-> IP-Bus Interface */ |
||||
DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); |
||||
DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); |
||||
DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); |
||||
DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); |
||||
DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); |
||||
DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); |
||||
DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); |
||||
DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); |
||||
DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); |
||||
DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); |
||||
DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MX51) || defined(CONFIG_MX53) |
||||
/* Round up to make sure size gives nice stack alignment */ |
||||
DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); |
||||
DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); |
||||
DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); |
||||
DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); |
||||
DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); |
||||
DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); |
||||
DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); |
||||
DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); |
||||
DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); |
||||
DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); |
||||
DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); |
||||
DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); |
||||
DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); |
||||
DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); |
||||
DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); |
||||
DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); |
||||
DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); |
||||
DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); |
||||
DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); |
||||
DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); |
||||
DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); |
||||
DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); |
||||
DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); |
||||
DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); |
||||
DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); |
||||
DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); |
||||
DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); |
||||
DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); |
||||
DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); |
||||
DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); |
||||
DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); |
||||
DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); |
||||
DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); |
||||
DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); |
||||
#if defined(CONFIG_MX53) |
||||
DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); |
||||
#endif |
||||
|
||||
/* DPLL */ |
||||
DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); |
||||
DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); |
||||
DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); |
||||
DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); |
||||
DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); |
||||
DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); |
||||
DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); |
||||
DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
@ -1,44 +0,0 @@ |
||||
/*
|
||||
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
||||
* |
||||
* Generate definitions needed by assembly language modules. |
||||
* This code generates raw asm output which is post-processed to extract |
||||
* and format the required data. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
#include <common.h> |
||||
|
||||
#include <linux/kbuild.h> |
||||
|
||||
int main(void) |
||||
{ |
||||
#ifdef CONFIG_FTSMC020 |
||||
OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); |
||||
OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); |
||||
#endif |
||||
BLANK(); |
||||
#ifdef CONFIG_FTAHBC020S |
||||
OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]); |
||||
OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); |
||||
OFFSET(FTAHBC020S_CR, ftahbc02s, cr); |
||||
#endif |
||||
BLANK(); |
||||
#ifdef CONFIG_FTPMU010 |
||||
OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0); |
||||
#endif |
||||
BLANK(); |
||||
#ifdef CONFIG_FTSDMC021 |
||||
OFFSET(FTSDMC021_TP1, ftsdmc021, tp1); |
||||
OFFSET(FTSDMC021_TP2, ftsdmc021, tp2); |
||||
OFFSET(FTSDMC021_CR1, ftsdmc021, cr1); |
||||
OFFSET(FTSDMC021_CR2, ftsdmc021, cr2); |
||||
OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr); |
||||
OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr); |
||||
OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr); |
||||
OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr); |
||||
#endif |
||||
return 0; |
||||
} |
@ -0,0 +1,52 @@ |
||||
/*
|
||||
* (C) Copyright 2013 Patrice Bouchand <pbfwdlist_gmail_com> |
||||
* lzma uncompress command in Uboot |
||||
* |
||||
* made from existing cmd_unzip.c file of Uboot |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/io.h> |
||||
|
||||
#include <lzma/LzmaTools.h> |
||||
|
||||
static int do_lzmadec(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) |
||||
{ |
||||
unsigned long src, dst; |
||||
unsigned long src_len = ~0UL, dst_len = ~0UL; |
||||
int ret; |
||||
|
||||
switch (argc) { |
||||
case 4: |
||||
dst_len = simple_strtoul(argv[3], NULL, 16); |
||||
/* fall through */ |
||||
case 3: |
||||
src = simple_strtoul(argv[1], NULL, 16); |
||||
dst = simple_strtoul(argv[2], NULL, 16); |
||||
break; |
||||
default: |
||||
return CMD_RET_USAGE; |
||||
} |
||||
|
||||
ret = lzmaBuffToBuffDecompress(map_sysmem(dst, dst_len), &src_len, |
||||
map_sysmem(src, 0), dst_len); |
||||
|
||||
if (ret != SZ_OK) |
||||
return 1; |
||||
printf("Uncompressed size: %ld = 0x%lX\n", src_len, src_len); |
||||
setenv_hex("filesize", src_len); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
lzmadec, 4, 1, do_lzmadec, |
||||
"lzma uncompress a memory region", |
||||
"srcaddr dstaddr [dstsize]" |
||||
); |
@ -1,387 +0,0 @@ |
||||
/*
|
||||
* i2c.c - driver for ADI TWI/I2C |
||||
* |
||||
* Copyright (c) 2006-2013 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
|
||||
#include <asm/clock.h> |
||||
#include <asm/twi.h> |
||||
#include <asm/io.h> |
||||
|
||||
/* Every register is 32bit aligned, but only 16bits in size */ |
||||
#define ureg(name) u16 name; u16 __pad_##name; |
||||
struct twi_regs { |
||||
ureg(clkdiv); |
||||
ureg(control); |
||||
ureg(slave_ctl); |
||||
ureg(slave_stat); |
||||
ureg(slave_addr); |
||||
ureg(master_ctl); |
||||
ureg(master_stat); |
||||
ureg(master_addr); |
||||
ureg(int_stat); |
||||
ureg(int_mask); |
||||
ureg(fifo_ctl); |
||||
ureg(fifo_stat); |
||||
char __pad[0x50]; |
||||
ureg(xmt_data8); |
||||
ureg(xmt_data16); |
||||
ureg(rcv_data8); |
||||
ureg(rcv_data16); |
||||
}; |
||||
#undef ureg |
||||
|
||||
/* U-Boot I2C framework allows only one active device at a time. */ |
||||
#ifdef TWI_CLKDIV |
||||
#define TWI0_CLKDIV TWI_CLKDIV |
||||
#endif |
||||
static struct twi_regs *twi = (void *)TWI0_CLKDIV; |
||||
|
||||
#ifdef DEBUG |
||||
# define dmemset(s, c, n) memset(s, c, n) |
||||
#else |
||||
# define dmemset(s, c, n) |
||||
#endif |
||||
#define debugi(fmt, args...) \ |
||||
debug( \
|
||||
"MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
|
||||
twi->master_stat, twi->fifo_stat, twi->int_stat, \
|
||||
__func__, __LINE__, ## args) |
||||
|
||||
#ifdef CONFIG_TWICLK_KHZ |
||||
# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED |
||||
#endif |
||||
|
||||
/*
|
||||
* The way speed is changed into duty often results in integer truncation |
||||
* with 50% duty, so we'll force rounding up to the next duty by adding 1 |
||||
* to the max. In practice this will get us a speed of something like |
||||
* 385 KHz. The other limit is easy to handle as it is only 8 bits. |
||||
*/ |
||||
#define I2C_SPEED_MAX 400000 |
||||
#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) |
||||
#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) |
||||
#define I2C_DUTY_MIN 0xff /* 8 bit limited */ |
||||
#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) |
||||
/* Note: duty is inverse of speed, so the comparisons below are correct */ |
||||
#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN |
||||
# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz" |
||||
#endif |
||||
|
||||
/* All transfers are described by this data structure */ |
||||
struct i2c_msg { |
||||
u8 flags; |
||||
#define I2C_M_COMBO 0x4 |
||||
#define I2C_M_STOP 0x2 |
||||
#define I2C_M_READ 0x1 |
||||
int len; /* msg length */ |
||||
u8 *buf; /* pointer to msg data */ |
||||
int alen; /* addr length */ |
||||
u8 *abuf; /* addr buffer */ |
||||
}; |
||||
|
||||
/* Allow msec timeout per ~byte transfer */ |
||||
#define I2C_TIMEOUT 10 |
||||
|
||||
/**
|
||||
* wait_for_completion - manage the actual i2c transfer |
||||
* @msg: the i2c msg |
||||
*/ |
||||
static int wait_for_completion(struct i2c_msg *msg) |
||||
{ |
||||
u16 int_stat, ctl; |
||||
ulong timebase = get_timer(0); |
||||
|
||||
do { |
||||
int_stat = readw(&twi->int_stat); |
||||
|
||||
if (int_stat & XMTSERV) { |
||||
debugi("processing XMTSERV"); |
||||
writew(XMTSERV, &twi->int_stat); |
||||
if (msg->alen) { |
||||
writew(*(msg->abuf++), &twi->xmt_data8); |
||||
--msg->alen; |
||||
} else if (!(msg->flags & I2C_M_COMBO) && msg->len) { |
||||
writew(*(msg->buf++), &twi->xmt_data8); |
||||
--msg->len; |
||||
} else { |
||||
ctl = readw(&twi->master_ctl); |
||||
if (msg->flags & I2C_M_COMBO) |
||||
writew(ctl | RSTART | MDIR, |
||||
&twi->master_ctl); |
||||
else |
||||
writew(ctl | STOP, &twi->master_ctl); |
||||
} |
||||
} |
||||
if (int_stat & RCVSERV) { |
||||
debugi("processing RCVSERV"); |
||||
writew(RCVSERV, &twi->int_stat); |
||||
if (msg->len) { |
||||
*(msg->buf++) = readw(&twi->rcv_data8); |
||||
--msg->len; |
||||
} else if (msg->flags & I2C_M_STOP) { |
||||
ctl = readw(&twi->master_ctl); |
||||
writew(ctl | STOP, &twi->master_ctl); |
||||
} |
||||
} |
||||
if (int_stat & MERR) { |
||||
debugi("processing MERR"); |
||||
writew(MERR, &twi->int_stat); |
||||
return msg->len; |
||||
} |
||||
if (int_stat & MCOMP) { |
||||
debugi("processing MCOMP"); |
||||
writew(MCOMP, &twi->int_stat); |
||||
if (msg->flags & I2C_M_COMBO && msg->len) { |
||||
ctl = readw(&twi->master_ctl); |
||||
ctl = (ctl & ~RSTART) | |
||||
(min(msg->len, 0xff) << 6) | MEN | MDIR; |
||||
writew(ctl, &twi->master_ctl); |
||||
} else |
||||
break; |
||||
} |
||||
|
||||
/* If we were able to do something, reset timeout */ |
||||
if (int_stat) |
||||
timebase = get_timer(0); |
||||
|
||||
} while (get_timer(timebase) < I2C_TIMEOUT); |
||||
|
||||
return msg->len; |
||||
} |
||||
|
||||
/**
|
||||
* i2c_transfer - setup an i2c transfer |
||||
* @return: 0 if things worked, non-0 if things failed |
||||
* |
||||
* Here we just get the i2c stuff all prepped and ready, and then tail off |
||||
* into wait_for_completion() for all the bits to go. |
||||
*/ |
||||
static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, |
||||
int len, u8 flags) |
||||
{ |
||||
int ret; |
||||
u16 ctl; |
||||
uchar addr_buffer[] = { |
||||
(addr >> 0), |
||||
(addr >> 8), |
||||
(addr >> 16), |
||||
}; |
||||
struct i2c_msg msg = { |
||||
.flags = flags | (len >= 0xff ? I2C_M_STOP : 0), |
||||
.buf = buffer, |
||||
.len = len, |
||||
.abuf = addr_buffer, |
||||
.alen = alen, |
||||
}; |
||||
|
||||
dmemset(buffer, 0xff, len); |
||||
debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i ", |
||||
chip, addr, alen, buffer[0], len); |
||||
debugi("flags=0x%02x[%s] ", flags, |
||||
(flags & I2C_M_READ ? "rd" : "wr")); |
||||
|
||||
/* wait for things to settle */ |
||||
while (readw(&twi->master_stat) & BUSBUSY) |
||||
if (ctrlc()) |
||||
return 1; |
||||
|
||||
/* Set Transmit device address */ |
||||
writew(chip, &twi->master_addr); |
||||
|
||||
/* Clear the FIFO before starting things */ |
||||
writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl); |
||||
writew(0, &twi->fifo_ctl); |
||||
|
||||
/* prime the pump */ |
||||
if (msg.alen) { |
||||
len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; |
||||
debugi("first byte=0x%02x", *msg.abuf); |
||||
writew(*(msg.abuf++), &twi->xmt_data8); |
||||
--msg.alen; |
||||
} else if (!(msg.flags & I2C_M_READ) && msg.len) { |
||||
debugi("first byte=0x%02x", *msg.buf); |
||||
writew(*(msg.buf++), &twi->xmt_data8); |
||||
--msg.len; |
||||
} |
||||
|
||||
/* clear int stat */ |
||||
writew(-1, &twi->master_stat); |
||||
writew(-1, &twi->int_stat); |
||||
writew(0, &twi->int_mask); |
||||
|
||||
/* Master enable */ |
||||
ctl = readw(&twi->master_ctl); |
||||
ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN | |
||||
((msg.flags & I2C_M_READ) ? MDIR : 0); |
||||
writew(ctl, &twi->master_ctl); |
||||
|
||||
/* process the rest */ |
||||
ret = wait_for_completion(&msg); |
||||
debugi("ret=%d", ret); |
||||
|
||||
if (ret) { |
||||
ctl = readw(&twi->master_ctl) & ~MEN; |
||||
writew(ctl, &twi->master_ctl); |
||||
ctl = readw(&twi->control) & ~TWI_ENA; |
||||
writew(ctl, &twi->control); |
||||
ctl = readw(&twi->control) | TWI_ENA; |
||||
writew(ctl, &twi->control); |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
/**
|
||||
* i2c_set_bus_speed - set i2c bus speed |
||||
* @speed: bus speed (in HZ) |
||||
*/ |
||||
int i2c_set_bus_speed(unsigned int speed) |
||||
{ |
||||
u16 clkdiv = I2C_SPEED_TO_DUTY(speed); |
||||
|
||||
/* Set TWI interface clock */ |
||||
if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) |
||||
return -1; |
||||
clkdiv = (clkdiv << 8) | (clkdiv & 0xff); |
||||
writew(clkdiv, &twi->clkdiv); |
||||
|
||||
/* Don't turn it on */ |
||||
writew(speed > 100000 ? FAST : 0, &twi->master_ctl); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/**
|
||||
* i2c_get_bus_speed - get i2c bus speed |
||||
* @speed: bus speed (in HZ) |
||||
*/ |
||||
unsigned int i2c_get_bus_speed(void) |
||||
{ |
||||
u16 clkdiv = readw(&twi->clkdiv) & 0xff; |
||||
/* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ |
||||
return 5000000 / clkdiv; |
||||
} |
||||
|
||||
/**
|
||||
* i2c_init - initialize the i2c bus |
||||
* @speed: bus speed (in HZ) |
||||
* @slaveaddr: address of device in slave mode (0 - not slave) |
||||
* |
||||
* Slave mode isn't actually implemented. It'll stay that way until |
||||
* we get a real request for it. |
||||
*/ |
||||
void i2c_init(int speed, int slaveaddr) |
||||
{ |
||||
u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; |
||||
|
||||
/* Set TWI internal clock as 10MHz */ |
||||
writew(prescale, &twi->control); |
||||
|
||||
/* Set TWI interface clock as specified */ |
||||
i2c_set_bus_speed(speed); |
||||
|
||||
/* Enable it */ |
||||
writew(TWI_ENA | prescale, &twi->control); |
||||
|
||||
debugi("CONTROL:0x%04x CLKDIV:0x%04x", readw(&twi->control), |
||||
readw(&twi->clkdiv)); |
||||
|
||||
#if CONFIG_SYS_I2C_SLAVE |
||||
# error I2C slave support not tested/supported |
||||
#endif |
||||
} |
||||
|
||||
/**
|
||||
* i2c_probe - test if a chip exists at a given i2c address |
||||
* @chip: i2c chip addr to search for |
||||
* @return: 0 if found, non-0 if not found |
||||
*/ |
||||
int i2c_probe(uchar chip) |
||||
{ |
||||
u8 byte; |
||||
return i2c_read(chip, 0, 0, &byte, 1); |
||||
} |
||||
|
||||
/**
|
||||
* i2c_read - read data from an i2c device |
||||
* @chip: i2c chip addr |
||||
* @addr: memory (register) address in the chip |
||||
* @alen: byte size of address |
||||
* @buffer: buffer to store data read from chip |
||||
* @len: how many bytes to read |
||||
* @return: 0 on success, non-0 on failure |
||||
*/ |
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
return i2c_transfer(chip, addr, alen, buffer, |
||||
len, (alen ? I2C_M_COMBO : I2C_M_READ)); |
||||
} |
||||
|
||||
/**
|
||||
* i2c_write - write data to an i2c device |
||||
* @chip: i2c chip addr |
||||
* @addr: memory (register) address in the chip |
||||
* @alen: byte size of address |
||||
* @buffer: buffer holding data to write to chip |
||||
* @len: how many bytes to write |
||||
* @return: 0 on success, non-0 on failure |
||||
*/ |
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
return i2c_transfer(chip, addr, alen, buffer, len, 0); |
||||
} |
||||
|
||||
/**
|
||||
* i2c_set_bus_num - change active I2C bus |
||||
* @bus: bus index, zero based |
||||
* @returns: 0 on success, non-0 on failure |
||||
*/ |
||||
int i2c_set_bus_num(unsigned int bus) |
||||
{ |
||||
switch (bus) { |
||||
#if CONFIG_SYS_MAX_I2C_BUS > 0 |
||||
case 0: |
||||
twi = (void *)TWI0_CLKDIV; |
||||
return 0; |
||||
#endif |
||||
#if CONFIG_SYS_MAX_I2C_BUS > 1 |
||||
case 1: |
||||
twi = (void *)TWI1_CLKDIV; |
||||
return 0; |
||||
#endif |
||||
#if CONFIG_SYS_MAX_I2C_BUS > 2 |
||||
case 2: |
||||
twi = (void *)TWI2_CLKDIV; |
||||
return 0; |
||||
#endif |
||||
default: return -1; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* i2c_get_bus_num - returns index of active I2C bus |
||||
*/ |
||||
unsigned int i2c_get_bus_num(void) |
||||
{ |
||||
switch ((unsigned long)twi) { |
||||
#if CONFIG_SYS_MAX_I2C_BUS > 0 |
||||
case TWI0_CLKDIV: |
||||
return 0; |
||||
#endif |
||||
#if CONFIG_SYS_MAX_I2C_BUS > 1 |
||||
case TWI1_CLKDIV: |
||||
return 1; |
||||
#endif |
||||
#if CONFIG_SYS_MAX_I2C_BUS > 2 |
||||
case TWI2_CLKDIV: |
||||
return 2; |
||||
#endif |
||||
default: return -1; |
||||
} |
||||
} |
@ -0,0 +1,41 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Samsung Electronics |
||||
* Przemyslaw Marczak <p.marczak@samsung.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __UUID_H__ |
||||
#define __UUID_H__ |
||||
|
||||
/* This is structure is in big-endian */ |
||||
struct uuid { |
||||
unsigned int time_low; |
||||
unsigned short time_mid; |
||||
unsigned short time_hi_and_version; |
||||
unsigned char clock_seq_hi_and_reserved; |
||||
unsigned char clock_seq_low; |
||||
unsigned char node[6]; |
||||
} __packed; |
||||
|
||||
enum { |
||||
UUID_STR_FORMAT_STD, |
||||
UUID_STR_FORMAT_GUID |
||||
}; |
||||
|
||||
#define UUID_STR_LEN 36 |
||||
#define UUID_BIN_LEN sizeof(struct uuid) |
||||
|
||||
#define UUID_VERSION_MASK 0xf000 |
||||
#define UUID_VERSION_SHIFT 12 |
||||
#define UUID_VERSION 0x4 |
||||
|
||||
#define UUID_VARIANT_MASK 0xc0 |
||||
#define UUID_VARIANT_SHIFT 7 |
||||
#define UUID_VARIANT 0x1 |
||||
|
||||
int uuid_str_valid(const char *uuid); |
||||
int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format); |
||||
void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format); |
||||
void gen_rand_uuid(unsigned char *uuid_bin); |
||||
void gen_rand_uuid_str(char *uuid_str, int str_format); |
||||
#endif |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in new issue