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@ -55,8 +55,8 @@ |
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#define RCC_CFGR_PPRE1_SHIFT 10 |
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#define RCC_CFGR_PPRE2_SHIFT 13 |
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#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6) |
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#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) |
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#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6) |
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#define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16) |
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#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 |
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#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 |
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#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) |
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@ -247,9 +247,9 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, |
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if (pllsai) { |
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/* PLL48CLK is selected from PLLSAI, get PLLSAI value */ |
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pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); |
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pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK) |
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pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK) |
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>> RCC_PLLSAICFGR_PLLSAIN_SHIFT); |
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pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK) |
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pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIP_MASK) |
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>> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); |
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return ((priv->hse_rate / pllm) * pllsain) / pllsaip; |
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} |
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