am335x:Handle worst case scenario for Errata 1.0.24

In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.

Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Adapt to current framework]
Signed-off-by: Tom Rini <trini@ti.com>

arch/arm/cpu/armv7/am33xx/board.c

@@ -144,6 +144,8 @@ int arch_misc_init(void)
  */
 __weak void am33xx_spl_board_init(void)
 {
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 
 static void rtc32k_enable(void)

arch/arm/cpu/armv7/am33xx/clock_am33xx.c

@@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = {
 	.cm_div_m2_dpll		= CM_WKUP + 0xA0,
 };
 
-const struct dpll_params dpll_mpu = {
+struct dpll_params dpll_mpu_opp100 = {
 		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
+const struct dpll_params dpll_core_opp100 = {
 		1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_mpu = {
+		MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+		50, OSC-1, -1, -1, 1, 1, 1};
 const struct dpll_params dpll_per = {
 		960, OSC-1, 5, -1, -1, -1, -1};
 

arch/arm/include/asm/arch-am33xx/clocks_am33xx.h

@@ -29,5 +29,7 @@
 #define UART_SMART_IDLE_EN	(0x1 << 0x3)
 
 extern void enable_dmm_clocks(void);
+extern const struct dpll_params dpll_core_opp100;
+extern struct dpll_params dpll_mpu_opp100;
 
 #endif	/* endif _CLOCKS_AM33XX_H_ */

board/ti/am335x/board.c

@@ -249,14 +249,13 @@ const struct dpll_params dpll_ddr_bone_black = {
 void am33xx_spl_board_init(void)
 {
 	struct am335x_baseboard_id header;
-	struct dpll_params dpll_mpu = {0, OSC-1, 1, -1, -1, -1, -1};
 	int mpu_vdd;
 
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 
 	/* Get the frequency */
-	dpll_mpu.m = am335x_get_efuse_mpu_max_freq(cdev);
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 
 	if (board_is_bone(&header) || board_is_bone_lt(&header)) {
 		/* BeagleBone PMIC Code */
@@ -293,13 +292,13 @@ void am33xx_spl_board_init(void)
 		 * a Beaglebone Black it supports 1GHz.
 		 */
 		if (board_is_bone_lt(&header))
-			dpll_mpu.m = MPUPLL_M_1000;
+			dpll_mpu_opp100.m = MPUPLL_M_1000;
 
 		/*
 		 * Increase USB current limit to 1300mA or 1800mA and set
 		 * the MPU voltage controller as needed.
 		 */
-		if (dpll_mpu.m == MPUPLL_M_1000) {
+		if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 		} else {
@@ -313,6 +312,15 @@ void am33xx_spl_board_init(void)
 				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 			puts("tps65217_reg_write failure\n");
 
+		/* Set DCDC3 (CORE) voltage to 1.125V */
+		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+			puts("tps65217_voltage_update failure\n");
+			return;
+		}
+
+		/* Set CORE Frequencies to OPP100 */
+		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 
 		/* Set DCDC2 (MPU) voltage */
 		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
@@ -360,7 +368,8 @@ void am33xx_spl_board_init(void)
 		 * VDD to drive at that speed.
 		 */
 		sil_rev = readl(&cdev->deviceid) >> 28;
-		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, dpll_mpu.m);
+		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
+						      dpll_mpu_opp100.m);
 
 		/* Tell the TPS65910 to use i2c */
 		tps65910_set_i2c_control();
@@ -372,10 +381,13 @@ void am33xx_spl_board_init(void)
 		/* Second, update the CORE voltage. */
 		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 			return;
+
+		/* Set CORE Frequencies to OPP100 */
+		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 	}
 
 	/* Set MPU Frequency to what we detected now that voltages are set */
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 
 const struct dpll_params *get_dpll_ddr_params(void)

include/configs/pcm051.h

@@ -201,6 +201,7 @@
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 /*
  * Place the image at the start of the ROM defined image space.
  * We limit our size to the ROM-defined downloaded image area, and use the

include/power/tps65217.h

@@ -65,6 +65,7 @@ enum {
 #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA	0x02
 #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA	0x03
 
+#define TPS65217_DCDC_VOLT_SEL_1125MV		0x09
 #define TPS65217_DCDC_VOLT_SEL_1275MV		0x0F
 #define TPS65217_DCDC_VOLT_SEL_1325MV		0x11