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@ -104,6 +104,43 @@ static void remove_cpu_resets(void) |
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writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); |
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} |
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static void tegra124_ram_repair(void) |
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{ |
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; |
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u32 ram_repair_timeout; /*usec*/ |
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u32 val; |
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/*
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* Request the Flow Controller perform RAM repair whenever it turns on |
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* a power rail that requires RAM repair. |
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*/ |
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clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN); |
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/* Request SW trigerred RAM repair by setting req bit */ |
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/* cluster 0 */ |
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setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); |
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/* Wait for completion (status == 0) */ |
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ram_repair_timeout = 500; |
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do { |
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udelay(1); |
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val = readl(&flow->ram_repair); |
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} while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--); |
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if (!ram_repair_timeout) |
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debug("Ram Repair cluster0 failed\n"); |
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/* cluster 1 */ |
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setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); |
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/* Wait for completion (status == 0) */ |
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ram_repair_timeout = 500; |
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do { |
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udelay(1); |
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val = readl(&flow->ram_repair_cluster1); |
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} while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--); |
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if (!ram_repair_timeout) |
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debug("Ram Repair cluster1 failed\n"); |
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} |
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/**
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* Tegra124 requires some special clock initialization, including setting up |
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* the DVC I2C, turning on MSELECT and selecting the G CPU cluster |
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@ -254,10 +291,11 @@ void start_cpu(u32 reset_vector) |
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&pmc->pmc_pwrgate_timer_mult); |
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enable_cpu_power_rail(); |
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powerup_cpus(); |
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tegra124_ram_repair(); |
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enable_cpu_clocks(); |
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clock_enable_coresight(1); |
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remove_cpu_resets(); |
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writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); |
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powerup_cpus(); |
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remove_cpu_resets(); |
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debug("%s exit, should continue @ reset_vector\n", __func__); |
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} |
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