Modified the mpc5xxx and the ppc4xx cpu to use the generic OHCI driver

and adapted board configs TQM5200 and yosemite accordingly. This commit
also makes the maximum number of root hub ports configurable 
(CFG_USB_OHCI_MAX_ROOT_PORTS).

cpu/mpc5xxx/Makefile

@@ -28,7 +28,7 @@ LIB	= lib$(CPU).a
 START	= start.o
 ASOBJS	= io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
 OBJS	= i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \
-	  loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o
+	  loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
 
 all:	.depend $(START) $(ASOBJS) $(LIB)
 

cpu/ppc4xx/Makefile

@@ -31,7 +31,8 @@ COBJS	= 405gp_pci.o 4xx_enet.o \
 	  bedbug_405.o commproc.o \
 	  cpu.o cpu_init.o i2c.o interrupts.o \
 	  miiphy.o sdram.o serial.o \
-	  spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o
+	  spd_sdram.o speed.o traps.o \
+	  usb_ohci.o usbdev.o usb.o
 
 OBJS	= $(AOBJS) $(COBJS)
 

drivers/usb_ohci.c

@@ -45,6 +45,7 @@
 
 #ifdef CONFIG_USB_OHCI
 
+/* mk: are these really required? */
 #if defined(CONFIG_S3C2400)
 # include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
@@ -53,6 +54,8 @@
 # include <asm/arch/hardware.h>
 #elif defined(CONFIG_CPU_MONAHANS)
 # include <asm/arch/pxa-regs.h>
+#elif defined(CONFIG_MPC5200)
+# include <mpc5xxx.h>
 #endif
 
 #include <malloc.h>
@@ -557,8 +560,10 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
  * the link from the ed still points to another operational ed or 0
  * so the HC can eventually finish the processing of the unlinked ed */
 
-static int ep_unlink (ohci_t *ohci, ed_t *ed)
+static int ep_unlink (ohci_t *ohci, ed_t *edi)
 {
+	volatile ed_t *ed = edi;
+
 	ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
 
 	switch (ed->type) {
@@ -825,6 +830,9 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
 				} else
 					td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
 			}
+#ifdef CONFIG_MPC5200
+			td_list->hwNextTD = 0;
+#endif
 		}
 
 		td_list->next_dl_td = td_rev;
@@ -1448,7 +1456,8 @@ static int hc_reset (ohci_t *ohci)
 		readl(&ohci->regs->control));
 
 	/* Reset USB (needed by some controllers) */
-	writel (0, &ohci->regs->control);
+	ohci->hc_control = 0;
+	writel (ohci->hc_control, &ohci->regs->control);
 
 	/* HC Reset requires max 10 us delay */
 	writel (OHCI_HCR,  &ohci->regs->cmdstatus);

drivers/usb_ohci.h

@@ -113,7 +113,9 @@ struct td {
 	__u32 hwNextTD;		/* Next TD Pointer */
 	__u32 hwBE;		/* Memory Buffer End Pointer */
 
+/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */
 	__u16 hwPSW[MAXPSW];
+/* #endif */
 	__u8 unused;
 	__u8 index;
 	struct ed *ed;
@@ -137,8 +139,13 @@ typedef struct td td_t;
 #define NUM_INTS 32	/* part of the OHCI standard */
 struct ohci_hcca {
 	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
+#if defined(CONFIG_MPC5200)
+	__u16	pad1;			/* set to 0 on each frame_no change */
+	__u16	frame_no;		/* current frame number */
+#else
 	__u16	frame_no;		/* current frame number */
 	__u16	pad1;			/* set to 0 on each frame_no change */
+#endif
 	__u32	done_head;		/* info returned for an interrupt */
 	u8		reserved_for_hc[116];
 } __attribute((aligned(256)));
@@ -147,7 +154,9 @@ struct ohci_hcca {
 /*
  * Maximum number of root hub ports.
  */
-#define MAX_ROOT_PORTS	3	/* maximum OHCI root hub ports */
+#ifndef CFG_USB_OHCI_MAX_ROOT_PORTS
+# error "CFG_USB_OHCI_MAX_ROOT_PORTS undefined!"
+#endif
 
 /*
  * This is the structure of the OHCI controller's memory mapped I/O
@@ -181,7 +190,7 @@ struct ohci_regs {
 		__u32	a;
 		__u32	b;
 		__u32	status;
-		__u32	portstatus[MAX_ROOT_PORTS];
+		__u32	portstatus[CFG_USB_OHCI_MAX_ROOT_PORTS];
 	} roothub;
 } __attribute((aligned(32)));
 

include/configs/TQM5200.h

@@ -128,6 +128,13 @@
 #define CONFIG_USB_OHCI
 #define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
 #define CONFIG_USB_STORAGE
+
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT
+#define CFG_USB_OHCI_REGS_BASE	MPC5XXX_USB
+#define CFG_USB_OHCI_SLOT_NAME	"mpc5200"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+
 #else
 #define ADD_USB_CMD		0
 #endif

include/configs/delta.h

@@ -111,6 +111,7 @@
 #define CFG_USB_OHCI_CPU_INIT	1
 #define CFG_USB_OHCI_REGS_BASE	OHCI_REGS_BASE
 #define CFG_USB_OHCI_SLOT_NAME	"delta"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	3
 
 #define LITTLEENDIAN            1       /* used by usb_ohci.c  */
 

include/configs/mp2usb.h

@@ -111,6 +111,7 @@
 #define CFG_USB_OHCI_CPU_INIT		1
 #define CFG_USB_OHCI_REGS_BASE		AT91_USB_HOST_BASE
 #define CFG_USB_OHCI_SLOT_NAME		"at91rm9200"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
 
 #undef CONFIG_HARD_I2C
 

include/configs/trab.h

@@ -88,6 +88,7 @@
 #define CFG_USB_OHCI_CPU_INIT	1
 #define CFG_USB_OHCI_REGS_BASE	S3C24X0_USB_HOST_BASE
 #define CFG_USB_OHCI_SLOT_NAME	"s3c2400"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
 
 /*
  * Size of malloc() pool

include/configs/yosemite.h

@@ -216,6 +216,12 @@
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
 
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT	1
+#define CFG_USB_OHCI_REGS_BASE	(CFG_PERIPHERAL_BASE | 0x1000)
+#define CFG_USB_OHCI_SLOT_NAME	"ppc440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
+
 /*Comment this out to enable USB 1.1 device*/
 #define USB_2_0_DEVICE
 #endif /*CONFIG_440EP*/