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@ -7,33 +7,51 @@ |
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#ifndef __CONFIG_ZYNQ_H |
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#define __CONFIG_ZYNQ_H |
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#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ |
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/* High Level configuration Options */ |
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#define CONFIG_ARMV7 |
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#define CONFIG_ZYNQ |
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/* CPU clock */ |
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#define CONFIG_CPU_FREQ_HZ 800000000 |
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#ifndef CONFIG_CPU_FREQ_HZ |
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# define CONFIG_CPU_FREQ_HZ 800000000 |
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#endif |
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/* Serial drivers */ |
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#define CONFIG_BAUDRATE 115200 |
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/* The following table includes the supported baudrates */ |
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#define CONFIG_SYS_BAUDRATE_TABLE \ |
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
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#define CONFIG_BAUDRATE 115200 |
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/* XPSS Serial driver */ |
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/* Zynq Serial driver */ |
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#define CONFIG_ZYNQ_SERIAL |
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#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 |
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#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE |
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#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 |
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/* DCC driver */ |
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#if defined(CONFIG_ZYNQ_DCC) |
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# define CONFIG_ARM_DCC |
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# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ |
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#endif |
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/* Ethernet driver */ |
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#define CONFIG_NET_MULTI |
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#define CONFIG_ZYNQ_GEM |
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#define CONFIG_ZYNQ_GEM0 |
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#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 |
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#define CONFIG_ZYNQ_SDHCI |
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#define CONFIG_ZYNQ_SDHCI0 |
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#define CONFIG_ZYNQ_SPI |
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/* SPI */ |
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#ifdef CONFIG_ZYNQ_SPI |
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# define CONFIG_SPI_FLASH |
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# define CONFIG_SPI_FLASH_SST |
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# define CONFIG_CMD_SF |
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#endif |
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/* NOR */ |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_ZYNQ_SDHCI0 |
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/* MMC */ |
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#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) |
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# define CONFIG_MMC |
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@ -48,7 +66,6 @@ |
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#endif |
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#define CONFIG_ZYNQ_I2C0 |
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/* I2C */ |
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#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) |
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# define CONFIG_CMD_I2C |
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@ -58,26 +75,6 @@ |
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# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 |
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#endif |
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#if defined(CONFIG_ZYNQ_DCC) |
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# define CONFIG_ARM_DCC |
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# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ |
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#endif |
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#define CONFIG_ZYNQ_SPI |
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/* SPI */ |
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#ifdef CONFIG_ZYNQ_SPI |
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# define CONFIG_SPI_FLASH |
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# define CONFIG_SPI_FLASH_SST |
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# define CONFIG_CMD_SF |
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#endif |
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/* Enable the PL to be downloaded */ |
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#define CONFIG_FPGA |
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#define CONFIG_FPGA_XILINX |
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#define CONFIG_FPGA_ZYNQPL |
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#define CONFIG_CMD_FPGA |
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#define CONFIG_BOOTP_SERVERIP |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_GATEWAY |
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@ -91,12 +88,9 @@ |
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#define CONFIG_PHY_MARVELL |
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/* Environment */ |
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#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ |
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#define CONFIG_ENV_IS_NOWHERE |
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#define CONFIG_ENV_SIZE 0x10000 |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_SYS_MALLOC_LEN 0x400000 |
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#define CONFIG_SYS_LOAD_ADDR 0 |
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/* Miscellaneous configurable options */ |
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#define CONFIG_SYS_PROMPT "zynq-uboot> " |
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@ -110,8 +104,6 @@ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
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sizeof(CONFIG_SYS_PROMPT) + 16) |
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#define CONFIG_SYS_LOAD_ADDR 0 |
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/* Physical Memory map */ |
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#define CONFIG_SYS_TEXT_BASE 0 |
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@ -122,15 +114,25 @@ |
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) |
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#define CONFIG_SYS_MALLOC_LEN 0x400000 |
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE |
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE) |
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/* OF */ |
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/* Enable the PL to be downloaded */ |
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#define CONFIG_FPGA |
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#define CONFIG_FPGA_XILINX |
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#define CONFIG_FPGA_ZYNQPL |
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#define CONFIG_CMD_FPGA |
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/* Open Firmware flat tree */ |
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#define CONFIG_OF_LIBFDT |
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/* FIT support */ |
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#define CONFIG_FIT |
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#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ |
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#define CONFIG_OF_LIBFDT |
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/* Boot FreeBSD/vxWorks from an ELF image */ |
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#if defined(CONFIG_ZYNQ_BOOT_FREEBSD) |
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