Tom Rini
8 years ago
commit
541c9be880
@ -0,0 +1,202 @@ |
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/* |
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* Clock specification for Xilinx ZynqMP |
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* |
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* (C) Copyright 2015, Xilinx, Inc. |
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* |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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&amba { |
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clk100: clk100 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <100000000>; |
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}; |
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clk125: clk125 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <125000000>; |
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}; |
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clk200: clk200 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <200000000>; |
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}; |
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clk250: clk250 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <250000000>; |
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}; |
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clk300: clk300 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <300000000>; |
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}; |
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clk600: clk600 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <600000000>; |
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}; |
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dp_aclk: clock0 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <100000000>; |
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clock-accuracy = <100>; |
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}; |
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dp_aud_clk: clock1 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <24576000>; |
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clock-accuracy = <100>; |
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}; |
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dpdma_clk: dpdma_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0x0>; |
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clock-frequency = <533000000>; |
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}; |
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|
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drm_clock: drm_clock { |
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compatible = "fixed-clock"; |
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#clock-cells = <0x0>; |
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clock-frequency = <262750000>; |
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clock-accuracy = <0x64>; |
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}; |
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}; |
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&can0 { |
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clocks = <&clk100 &clk100>; |
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}; |
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&can1 { |
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clocks = <&clk100 &clk100>; |
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}; |
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&fpd_dma_chan1 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan2 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan3 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan4 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan5 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan6 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan7 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan8 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&nand0 { |
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clocks = <&clk100 &clk100>; |
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}; |
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&gem0 { |
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clocks = <&clk125>, <&clk125>, <&clk125>; |
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}; |
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&gem1 { |
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clocks = <&clk125>, <&clk125>, <&clk125>; |
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}; |
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&gem2 { |
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clocks = <&clk125>, <&clk125>, <&clk125>; |
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}; |
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&gem3 { |
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clocks = <&clk125>, <&clk125>, <&clk125>; |
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}; |
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&gpio { |
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clocks = <&clk100>; |
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}; |
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&i2c0 { |
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clocks = <&clk100>; |
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}; |
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&i2c1 { |
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clocks = <&clk100>; |
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}; |
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&qspi { |
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clocks = <&clk300 &clk300>; |
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}; |
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&sata { |
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clocks = <&clk250>; |
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}; |
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&sdhci0 { |
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clocks = <&clk200 &clk200>; |
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}; |
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&sdhci1 { |
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clocks = <&clk200 &clk200>; |
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}; |
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&spi0 { |
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clocks = <&clk200 &clk200>; |
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}; |
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&spi1 { |
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clocks = <&clk200 &clk200>; |
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}; |
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&uart0 { |
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clocks = <&clk100 &clk100>; |
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}; |
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&uart1 { |
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clocks = <&clk100 &clk100>; |
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}; |
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&usb0 { |
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clocks = <&clk250>, <&clk250>; |
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}; |
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&usb1 { |
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clocks = <&clk250>, <&clk250>; |
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}; |
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&xilinx_drm { |
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clocks = <&drm_clock>; |
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}; |
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&xlnx_dp { |
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clocks = <&dp_aclk>, <&dp_aud_clk>; |
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}; |
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&xlnx_dpdma { |
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clocks = <&dpdma_clk>; |
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}; |
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&xlnx_dp_snd_codec0 { |
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clocks = <&dp_aud_clk>; |
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}; |
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@ -0,0 +1,211 @@ |
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/* |
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* dts file for Xilinx ZynqMP zc1751-xm015-dc1 |
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* |
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* (C) Copyright 2015, Xilinx, Inc. |
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* |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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#include "zynqmp.dtsi" |
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#include "zynqmp-clk.dtsi" |
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/ { |
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model = "ZynqMP zc1751-xm015-dc1 RevA"; |
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; |
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aliases { |
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ethernet0 = &gem3; |
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gpio0 = &gpio; |
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i2c0 = &i2c1; |
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mmc0 = &sdhci0; |
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mmc1 = &sdhci1; |
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rtc0 = &rtc; |
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serial0 = &uart0; |
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spi0 = &qspi; |
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usb0 = &usb0; |
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}; |
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chosen { |
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bootargs = "earlycon"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
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}; |
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}; |
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/* fpd_dma clk 667MHz, lpd_dma 500MHz */ |
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&fpd_dma_chan1 { |
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status = "okay"; |
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xlnx,include-sg; /* for testing purpose */ |
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xlnx,overfetch; /* for testing purpose */ |
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xlnx,ratectrl = <0>; /* for testing purpose */ |
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xlnx,src-issue = <31>; |
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}; |
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&fpd_dma_chan2 { |
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status = "okay"; |
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xlnx,ratectrl = <100>; /* for testing purpose */ |
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xlnx,src-issue = <4>; /* for testing purpose */ |
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}; |
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&fpd_dma_chan3 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan4 { |
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status = "okay"; |
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xlnx,include-sg; /* for testing purpose */ |
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}; |
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&fpd_dma_chan5 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan6 { |
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status = "okay"; |
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xlnx,include-sg; /* for testing purpose */ |
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}; |
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&fpd_dma_chan7 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan8 { |
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status = "okay"; |
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xlnx,include-sg; /* for testing purpose */ |
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}; |
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&gem3 { |
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status = "okay"; |
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local-mac-address = [00 0a 35 00 02 90]; |
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phy-handle = <&phy0>; |
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phy-mode = "rgmii-id"; |
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phy0: phy@0 { |
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reg = <0>; |
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}; |
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}; |
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&gpio { |
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status = "okay"; |
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}; |
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&gpu { |
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status = "okay"; |
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}; |
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&i2c1 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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eeprom@55 { |
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compatible = "at,24c64"; /* 24AA64 */ |
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reg = <0x55>; |
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}; |
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}; |
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&qspi { |
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status = "okay"; |
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flash@0 { |
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compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */ |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x0>; |
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spi-tx-bus-width = <1>; |
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spi-rx-bus-width = <4>; |
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spi-max-frequency = <108000000>; /* Based on DC1 spec */ |
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partition@qspi-fsbl-uboot { /* for testing purpose */ |
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label = "qspi-fsbl-uboot"; |
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reg = <0x0 0x100000>; |
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}; |
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partition@qspi-linux { /* for testing purpose */ |
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label = "qspi-linux"; |
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reg = <0x100000 0x500000>; |
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}; |
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partition@qspi-device-tree { /* for testing purpose */ |
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label = "qspi-device-tree"; |
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reg = <0x600000 0x20000>; |
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}; |
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partition@qspi-rootfs { /* for testing purpose */ |
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label = "qspi-rootfs"; |
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reg = <0x620000 0x5E0000>; |
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}; |
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}; |
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}; |
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&rtc { |
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status = "okay"; |
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}; |
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&sata { |
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status = "okay"; |
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/* SATA phy OOB timing settings */ |
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ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; |
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ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; |
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ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
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ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
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ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; |
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; |
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
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}; |
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/* eMMC */ |
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&sdhci0 { |
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status = "okay"; |
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bus-width = <8>; |
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}; |
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/* SD1 with level shifter */ |
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&sdhci1 { |
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status = "okay"; |
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no-1-8-v; /* for 1.0 silicon */ |
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}; |
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&uart0 { |
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status = "okay"; |
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}; |
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/* ULPI SMSC USB3320 */ |
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&usb0 { |
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status = "okay"; |
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dr_mode = "host"; |
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}; |
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&xilinx_drm { |
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status = "okay"; |
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}; |
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&xlnx_dp { |
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status = "okay"; |
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}; |
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&xlnx_dp_sub { |
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status = "okay"; |
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xlnx,vid-clk-pl; |
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}; |
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&xlnx_dp_snd_pcm0 { |
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status = "okay"; |
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}; |
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&xlnx_dp_snd_pcm1 { |
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status = "okay"; |
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}; |
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&xlnx_dp_snd_card { |
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status = "okay"; |
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}; |
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&xlnx_dp_snd_codec0 { |
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status = "okay"; |
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}; |
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&xlnx_dpdma { |
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status = "okay"; |
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}; |
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@ -0,0 +1,236 @@ |
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/* |
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* dts file for Xilinx ZynqMP zc1751-xm016-dc2 |
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* |
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* (C) Copyright 2015, Xilinx, Inc. |
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* |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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#include "zynqmp.dtsi" |
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#include "zynqmp-clk.dtsi" |
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/ { |
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model = "ZynqMP zc1751-xm016-dc2 RevA"; |
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; |
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aliases { |
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can0 = &can0; |
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can1 = &can1; |
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ethernet0 = &gem2; |
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gpio0 = &gpio; |
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i2c0 = &i2c0; |
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rtc0 = &rtc; |
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serial0 = &uart0; |
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serial1 = &uart1; |
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spi0 = &spi0; |
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spi1 = &spi1; |
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usb0 = &usb1; |
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}; |
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chosen { |
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bootargs = "earlycon"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
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}; |
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}; |
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&can0 { |
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status = "okay"; |
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}; |
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&can1 { |
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status = "okay"; |
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}; |
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/* fpd_dma clk 667MHz, lpd_dma 500MHz */ |
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&fpd_dma_chan1 { |
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status = "okay"; |
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xlnx,include-sg; /* for testing purpose */ |
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xlnx,overfetch; /* for testing purpose */ |
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xlnx,ratectrl = <0>; /* for testing purpose */ |
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xlnx,src-issue = <31>; |
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}; |
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&fpd_dma_chan2 { |
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status = "okay"; |
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xlnx,ratectrl = <100>; /* for testing purpose */ |
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xlnx,src-issue = <4>; /* for testing purpose */ |
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}; |
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&fpd_dma_chan3 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan4 { |
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status = "okay"; |
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xlnx,include-sg; /* for testing purpose */ |
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}; |
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&fpd_dma_chan5 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan6 { |
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status = "okay"; |
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xlnx,include-sg; /* for testing purpose */ |
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}; |
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&fpd_dma_chan7 { |
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status = "okay"; |
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}; |
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|
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&fpd_dma_chan8 { |
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status = "okay"; |
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xlnx,include-sg; /* for testing purpose */ |
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}; |
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|
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&gem2 { |
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status = "okay"; |
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local-mac-address = [00 0a 35 00 02 90]; |
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phy-handle = <&phy0>; |
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phy-mode = "rgmii-id"; |
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phy0: phy@5 { |
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reg = <5>; |
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ti,rx-internal-delay = <0x8>; |
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ti,tx-internal-delay = <0xa>; |
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ti,fifo-depth = <0x1>; |
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}; |
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}; |
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|
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&gpio { |
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status = "okay"; |
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}; |
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|
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&i2c0 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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|
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tca6416_u26: gpio@20 { |
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compatible = "ti,tca6416"; |
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reg = <0x20>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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/* IRQ not connected */ |
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}; |
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|
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rtc@68 { |
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compatible = "dallas,ds1339"; |
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reg = <0x68>; |
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}; |
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}; |
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|
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&nand0 { |
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status = "okay"; |
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arasan,has-mdma; |
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num-cs = <2>; |
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|
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partition@0 { /* for testing purpose */ |
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label = "nand-fsbl-uboot"; |
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reg = <0x0 0x0 0x400000>; |
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}; |
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partition@1 { /* for testing purpose */ |
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label = "nand-linux"; |
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reg = <0x0 0x400000 0x1400000>; |
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}; |
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partition@2 { /* for testing purpose */ |
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label = "nand-device-tree"; |
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reg = <0x0 0x1800000 0x400000>; |
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}; |
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partition@3 { /* for testing purpose */ |
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label = "nand-rootfs"; |
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reg = <0x0 0x1C00000 0x1400000>; |
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}; |
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partition@4 { /* for testing purpose */ |
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label = "nand-bitstream"; |
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reg = <0x0 0x3000000 0x400000>; |
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}; |
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partition@5 { /* for testing purpose */ |
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label = "nand-misc"; |
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reg = <0x0 0x3400000 0xFCC00000>; |
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}; |
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|
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partition@6 { /* for testing purpose */ |
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label = "nand1-fsbl-uboot"; |
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reg = <0x1 0x0 0x400000>; |
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}; |
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partition@7 { /* for testing purpose */ |
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label = "nand1-linux"; |
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reg = <0x1 0x400000 0x1400000>; |
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}; |
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partition@8 { /* for testing purpose */ |
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label = "nand1-device-tree"; |
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reg = <0x1 0x1800000 0x400000>; |
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}; |
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partition@9 { /* for testing purpose */ |
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label = "nand1-rootfs"; |
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reg = <0x1 0x1C00000 0x1400000>; |
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}; |
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partition@10 { /* for testing purpose */ |
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label = "nand1-bitstream"; |
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reg = <0x1 0x3000000 0x400000>; |
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}; |
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partition@11 { /* for testing purpose */ |
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label = "nand1-misc"; |
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reg = <0x1 0x3400000 0xFCC00000>; |
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}; |
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}; |
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|
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&rtc { |
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status = "okay"; |
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}; |
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|
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&spi0 { |
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status = "okay"; |
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num-cs = <1>; |
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spi0_flash0: spi0_flash0@0 { |
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compatible = "m25p80"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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spi-max-frequency = <50000000>; |
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reg = <0>; |
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|
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spi0_flash0@00000000 { |
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label = "spi0_flash0"; |
||||
reg = <0x0 0x100000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&spi1 { |
||||
status = "okay"; |
||||
num-cs = <1>; |
||||
spi1_flash0: spi1_flash0@0 { |
||||
compatible = "mtd_dataflash"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
spi-max-frequency = <20000000>; |
||||
reg = <0>; |
||||
|
||||
spi1_flash0@00000000 { |
||||
label = "spi1_flash0"; |
||||
reg = <0x0 0x84000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
/* ULPI SMSC USB3320 */ |
||||
&usb1 { |
||||
status = "okay"; |
||||
dr_mode = "host"; |
||||
}; |
||||
|
||||
&uart0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart1 { |
||||
status = "okay"; |
||||
}; |
||||
@ -0,0 +1,121 @@ |
||||
/* |
||||
* dts file for Xilinx ZynqMP zc1751-xm019-dc5 |
||||
* |
||||
* (C) Copyright 2015, Xilinx, Inc. |
||||
* |
||||
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include "zynqmp.dtsi" |
||||
#include "zynqmp-clk.dtsi" |
||||
/ { |
||||
model = "ZynqMP zc1751-xm019-dc5 RevA"; |
||||
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; |
||||
|
||||
aliases { |
||||
ethernet0 = &gem1; |
||||
gpio0 = &gpio; |
||||
i2c0 = &i2c0; |
||||
i2c1 = &i2c1; |
||||
mmc0 = &sdhci0; |
||||
serial0 = &uart0; |
||||
serial1 = &uart1; |
||||
}; |
||||
|
||||
chosen { |
||||
bootargs = "earlycon=cdns,mmio,0xff000000,115200n8"; |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
memory { |
||||
device_type = "memory"; |
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
||||
}; |
||||
}; |
||||
|
||||
/* fpd_dma clk 667MHz, lpd_dma 500MHz */ |
||||
&fpd_dma_chan1 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
xlnx,overfetch; /* for testing purpose */ |
||||
xlnx,ratectrl = <0>; /* for testing purpose */ |
||||
xlnx,src-issue = <31>; |
||||
}; |
||||
|
||||
&fpd_dma_chan2 { |
||||
status = "okay"; |
||||
xlnx,ratectrl = <100>; /* for testing purpose */ |
||||
xlnx,src-issue = <4>; /* for testing purpose */ |
||||
}; |
||||
|
||||
&fpd_dma_chan3 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fpd_dma_chan4 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
}; |
||||
|
||||
&fpd_dma_chan5 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fpd_dma_chan6 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
}; |
||||
|
||||
&fpd_dma_chan7 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fpd_dma_chan8 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
}; |
||||
|
||||
&gem1 { |
||||
status = "okay"; |
||||
local-mac-address = [00 0a 35 00 02 90]; |
||||
phy-handle = <&phy0>; |
||||
phy-mode = "rgmii-id"; |
||||
phy0: phy@0 { |
||||
reg = <0>; |
||||
}; |
||||
}; |
||||
|
||||
&gpio { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
/* FIXME: Add device */ |
||||
&i2c0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
/* FIXME: Add device */ |
||||
&i2c1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhci0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&watchdog0 { |
||||
status = "okay"; |
||||
}; |
||||
@ -0,0 +1,42 @@ |
||||
/* |
||||
* dts file for Xilinx ZynqMP ZCU102 RevB |
||||
* |
||||
* (C) Copyright 2016, Xilinx, Inc. |
||||
* |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "zynqmp-zcu102.dts" |
||||
|
||||
/ { |
||||
model = "ZynqMP ZCU102 RevB"; |
||||
}; |
||||
|
||||
&gem3 { |
||||
phy-handle = <&phyc>; |
||||
phyc: phy@c { |
||||
reg = <0xc>; |
||||
ti,rx-internal-delay = <0x8>; |
||||
ti,tx-internal-delay = <0xa>; |
||||
ti,fifo-depth = <0x1>; |
||||
}; |
||||
/* Cleanup from RevA */ |
||||
/delete-node/ phy@21; |
||||
}; |
||||
|
||||
/* Different qspi 512Mbit version */ |
||||
|
||||
/* Fix collision with u61 */ |
||||
&i2c0 { |
||||
i2cswitch@75 { |
||||
i2c@2 { |
||||
max15303@1b { /* u8 */ |
||||
compatible = "max15303"; |
||||
reg = <0x1b>; |
||||
}; |
||||
/delete-node/ max15303@20; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,631 @@ |
||||
/* |
||||
* dts file for Xilinx ZynqMP ZCU102 |
||||
* |
||||
* (C) Copyright 2015, Xilinx, Inc. |
||||
* |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include "zynqmp.dtsi" |
||||
#include "zynqmp-clk.dtsi" |
||||
|
||||
/ { |
||||
model = "ZynqMP ZCU102 RevA"; |
||||
compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; |
||||
|
||||
aliases { |
||||
ethernet0 = &gem3; |
||||
gpio0 = &gpio; |
||||
i2c0 = &i2c0; |
||||
i2c1 = &i2c1; |
||||
mmc0 = &sdhci1; |
||||
rtc0 = &rtc; |
||||
serial0 = &uart0; |
||||
serial1 = &uart1; |
||||
spi0 = &qspi; |
||||
usb0 = &usb0; |
||||
}; |
||||
|
||||
chosen { |
||||
bootargs = "earlycon"; |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
memory { |
||||
device_type = "memory"; |
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
||||
}; |
||||
}; |
||||
|
||||
&can1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
/* fpd_dma clk 667MHz, lpd_dma 500MHz */ |
||||
&fpd_dma_chan1 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
xlnx,overfetch; /* for testing purpose */ |
||||
xlnx,ratectrl = <0>; /* for testing purpose */ |
||||
xlnx,src-issue = <31>; |
||||
}; |
||||
|
||||
&fpd_dma_chan2 { |
||||
status = "okay"; |
||||
xlnx,ratectrl = <100>; /* for testing purpose */ |
||||
xlnx,src-issue = <4>; /* for testing purpose */ |
||||
}; |
||||
|
||||
&fpd_dma_chan3 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fpd_dma_chan4 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
}; |
||||
|
||||
&fpd_dma_chan5 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fpd_dma_chan6 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
}; |
||||
|
||||
&fpd_dma_chan7 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fpd_dma_chan8 { |
||||
status = "okay"; |
||||
xlnx,include-sg; /* for testing purpose */ |
||||
}; |
||||
|
||||
&gem3 { |
||||
status = "okay"; |
||||
local-mac-address = [00 0a 35 00 02 90]; |
||||
phy-handle = <&phy0>; |
||||
phy-mode = "rgmii-id"; |
||||
phy0: phy@21 { |
||||
reg = <21>; |
||||
ti,rx-internal-delay = <0x8>; |
||||
ti,tx-internal-delay = <0xa>; |
||||
ti,fifo-depth = <0x1>; |
||||
}; |
||||
}; |
||||
|
||||
&gpio { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gpu { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&i2c0 { |
||||
status = "okay"; |
||||
clock-frequency = <400000>; |
||||
|
||||
tca6416_u97: gpio@20 { |
||||
/* |
||||
* Enable all GTs to out from U-Boot |
||||
* i2c mw 20 6 0 - setup IO to output |
||||
* i2c mw 20 2 ef - setup output values on pins 0-7 |
||||
* i2c mw 20 3 ff - setup output values on pins 10-17 |
||||
*/ |
||||
compatible = "ti,tca6416"; |
||||
reg = <0x20>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
/* |
||||
* IRQ not connected |
||||
* Lines: |
||||
* 0 - PS_GTR_LAN_SEL0 |
||||
* 1 - PS_GTR_LAN_SEL1 |
||||
* 2 - PS_GTR_LAN_SEL2 |
||||
* 3 - PS_GTR_LAN_SEL3 |
||||
* 4 - PCI_CLK_DIR_SEL |
||||
* 5 - IIC_MUX_RESET_B |
||||
* 6 - GEM3_EXP_RESET_B |
||||
* 7, 10 - 17 - not connected |
||||
*/ |
||||
|
||||
gtr_sel0 { |
||||
gpio-hog; |
||||
gpios = <0 0>; |
||||
output-high; /* PCIE = 0, DP = 1 */ |
||||
line-name = "sel0"; |
||||
}; |
||||
gtr_sel1 { |
||||
gpio-hog; |
||||
gpios = <1 0>; |
||||
output-high; /* PCIE = 0, DP = 1 */ |
||||
line-name = "sel1"; |
||||
}; |
||||
gtr_sel2 { |
||||
gpio-hog; |
||||
gpios = <2 0>; |
||||
output-high; /* PCIE = 0, USB0 = 1 */ |
||||
line-name = "sel2"; |
||||
}; |
||||
gtr_sel3 { |
||||
gpio-hog; |
||||
gpios = <3 0>; |
||||
output-high; /* PCIE = 0, SATA = 1 */ |
||||
line-name = "sel3"; |
||||
}; |
||||
}; |
||||
|
||||
tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ |
||||
compatible = "ti,tca6416"; |
||||
reg = <0x21>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
/* |
||||
* IRQ not connected |
||||
* Lines: |
||||
* 0 - VCCPSPLL_EN |
||||
* 1 - MGTRAVCC_EN |
||||
* 2 - MGTRAVTT_EN |
||||
* 3 - VCCPSDDRPLL_EN |
||||
* 4 - MIO26_PMU_INPUT_LS |
||||
* 5 - PL_PMBUS_ALERT |
||||
* 6 - PS_PMBUS_ALERT |
||||
* 7 - MAXIM_PMBUS_ALERT |
||||
* 10 - PL_DDR4_VTERM_EN |
||||
* 11 - PL_DDR4_VPP_2V5_EN |
||||
* 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON |
||||
* 13 - PS_DIMM_SUSPEND_EN |
||||
* 14 - PS_DDR4_VTERM_EN |
||||
* 15 - PS_DDR4_VPP_2V5_EN |
||||
* 16 - 17 - not connected |
||||
*/ |
||||
}; |
||||
|
||||
i2cswitch@75 { /* u60 */ |
||||
compatible = "nxp,pca9544"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0x75>; |
||||
i2c@0 { /* i2c mw 75 0 1 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0>; |
||||
/* PS_PMBUS */ |
||||
ina226@40 { /* u76 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x40>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@41 { /* u77 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x41>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@42 { /* u78 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x42>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@43 { /* u87 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x43>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@44 { /* u85 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x44>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@45 { /* u86 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x45>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@46 { /* u93 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x46>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@47 { /* u88 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x47>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@4a { /* u15 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x4a>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@4b { /* u92 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x4b>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
}; |
||||
i2c@1 { /* i2c mw 75 0 1 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <1>; |
||||
/* PL_PMBUS */ |
||||
ina226@40 { /* u79 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x40>; |
||||
shunt-resistor = <2000>; |
||||
}; |
||||
ina226@41 { /* u81 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x41>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@42 { /* u80 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x42>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@43 { /* u84 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x43>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@44 { /* u16 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x44>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@45 { /* u65 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x45>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@46 { /* u74 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x46>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
ina226@47 { /* u75 */ |
||||
compatible = "ti,ina226"; |
||||
reg = <0x47>; |
||||
shunt-resistor = <5000>; |
||||
}; |
||||
}; |
||||
i2c@2 { /* i2c mw 75 0 1 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <2>; |
||||
/* MAXIM_PMBUS - 00 */ |
||||
max15301@a { /* u46 */ |
||||
compatible = "max15301"; |
||||
reg = <0xa>; |
||||
}; |
||||
max15303@b { /* u4 */ |
||||
compatible = "max15303"; |
||||
reg = <0xb>; |
||||
}; |
||||
max15303@10 { /* u13 */ |
||||
compatible = "max15303"; |
||||
reg = <0x10>; |
||||
}; |
||||
max15301@13 { /* u47 */ |
||||
compatible = "max15301"; |
||||
reg = <0x13>; |
||||
}; |
||||
max15303@14 { /* u7 */ |
||||
compatible = "max15303"; |
||||
reg = <0x14>; |
||||
}; |
||||
max15303@15 { /* u6 */ |
||||
compatible = "max15303"; |
||||
reg = <0x15>; |
||||
}; |
||||
max15303@16 { /* u10 */ |
||||
compatible = "max15303"; |
||||
reg = <0x16>; |
||||
}; |
||||
max15303@17 { /* u9 */ |
||||
compatible = "max15303"; |
||||
reg = <0x17>; |
||||
}; |
||||
max15301@18 { /* u63 */ |
||||
compatible = "max15301"; |
||||
reg = <0x18>; |
||||
}; |
||||
max15303@1a { /* u49 */ |
||||
compatible = "max15303"; |
||||
reg = <0x1a>; |
||||
}; |
||||
max15303@1d { /* u18 */ |
||||
compatible = "max15303"; |
||||
reg = <0x1d>; |
||||
}; |
||||
max15303@20 { /* u8 */ |
||||
compatible = "max15303"; |
||||
status = "disabled"; /* unreachable */ |
||||
reg = <0x20>; |
||||
}; |
||||
|
||||
/* drivers/hwmon/pmbus/Kconfig:86: be called max20751. |
||||
drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o |
||||
*/ |
||||
max20751@72 { /* u95 FIXME - not detected */ |
||||
compatible = "max20751"; |
||||
reg = <0x72>; |
||||
}; |
||||
max20751@73 { /* u96 FIXME - not detected */ |
||||
compatible = "max20751"; |
||||
reg = <0x73>; |
||||
}; |
||||
}; |
||||
/* Bus 3 is not connected */ |
||||
}; |
||||
|
||||
/* FIXME PL connection - u55 , PMOD - j160 */ |
||||
/* FIXME MSP430F - u41 - not detected */ |
||||
}; |
||||
|
||||
&i2c1 { |
||||
status = "okay"; |
||||
clock-frequency = <400000>; |
||||
/* FIXME PL i2c via PCA9306 - u45 */ |
||||
/* FIXME MSP430 - u41 - not detected */ |
||||
i2cswitch@74 { /* u34 */ |
||||
compatible = "nxp,pca9548"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0x74>; |
||||
i2c@0 { /* i2c mw 74 0 1 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0>; |
||||
/* |
||||
* IIC_EEPROM 1kB memory which uses 256B blocks |
||||
* where every block has different address. |
||||
* 0 - 256B address 0x54 |
||||
* 256B - 512B address 0x55 |
||||
* 512B - 768B address 0x56 |
||||
* 768B - 1024B address 0x57 |
||||
*/ |
||||
eeprom@54 { /* u23 */ |
||||
compatible = "at,24c08"; |
||||
reg = <0x54>; |
||||
}; |
||||
}; |
||||
i2c@1 { /* i2c mw 74 0 2 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <1>; |
||||
si5341: clock-generator1@36 { /* SI5341 - u69 */ |
||||
compatible = "si5341"; |
||||
reg = <0x36>; |
||||
}; |
||||
|
||||
}; |
||||
i2c@2 { /* i2c mw 74 0 4 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <2>; |
||||
si570_1: clock-generator2@5d { /* USER SI570 - u42 */ |
||||
#clock-cells = <0>; |
||||
compatible = "silabs,si570"; |
||||
reg = <0x5d>; |
||||
temperature-stability = <50>; |
||||
factory-fout = <300000000>; |
||||
clock-frequency = <300000000>; |
||||
}; |
||||
}; |
||||
i2c@3 { /* i2c mw 74 0 8 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <3>; |
||||
si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ |
||||
#clock-cells = <0>; |
||||
compatible = "silabs,si570"; |
||||
reg = <0x5d>; |
||||
temperature-stability = <50>; /* copy from zc702 */ |
||||
factory-fout = <156250000>; |
||||
clock-frequency = <148500000>; |
||||
}; |
||||
}; |
||||
i2c@4 { /* i2c mw 74 0 10 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <4>; |
||||
si5328: clock-generator4@69 {/* SI5328 - u20 */ |
||||
compatible = "silabs,si5328"; |
||||
reg = <0x69>; |
||||
}; |
||||
}; |
||||
/* 5 - 7 unconnected */ |
||||
}; |
||||
|
||||
i2cswitch@75 { |
||||
compatible = "nxp,pca9548"; /* u135 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0x75>; |
||||
|
||||
i2c@0 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0>; |
||||
/* HPC0_IIC */ |
||||
}; |
||||
i2c@1 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <1>; |
||||
/* HPC1_IIC */ |
||||
}; |
||||
i2c@2 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <2>; |
||||
/* SYSMON */ |
||||
}; |
||||
i2c@3 { /* i2c mw 75 0 8 */ |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <3>; |
||||
/* DDR4 SODIMM */ |
||||
dev@19 { /* u-boot detection */ |
||||
compatible = "xxx"; |
||||
reg = <0x19>; |
||||
}; |
||||
dev@30 { /* u-boot detection */ |
||||
compatible = "xxx"; |
||||
reg = <0x30>; |
||||
}; |
||||
dev@35 { /* u-boot detection */ |
||||
compatible = "xxx"; |
||||
reg = <0x35>; |
||||
}; |
||||
dev@36 { /* u-boot detection */ |
||||
compatible = "xxx"; |
||||
reg = <0x36>; |
||||
}; |
||||
dev@51 { /* u-boot detection - maybe SPD */ |
||||
compatible = "xxx"; |
||||
reg = <0x51>; |
||||
}; |
||||
}; |
||||
i2c@4 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <4>; |
||||
/* SEP 3 */ |
||||
}; |
||||
i2c@5 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <5>; |
||||
/* SEP 2 */ |
||||
}; |
||||
i2c@6 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <6>; |
||||
/* SEP 1 */ |
||||
}; |
||||
i2c@7 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <7>; |
||||
/* SEP 0 */ |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&pcie { |
||||
/* status = "okay"; */ |
||||
}; |
||||
|
||||
&qspi { |
||||
status = "okay"; |
||||
is-dual = <1>; |
||||
flash@0 { |
||||
compatible = "m25p80"; /* 32MB */ |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
reg = <0x0>; |
||||
spi-tx-bus-width = <1>; |
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ |
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */ |
||||
partition@qspi-fsbl-uboot { /* for testing purpose */ |
||||
label = "qspi-fsbl-uboot"; |
||||
reg = <0x0 0x100000>; |
||||
}; |
||||
partition@qspi-linux { /* for testing purpose */ |
||||
label = "qspi-linux"; |
||||
reg = <0x100000 0x500000>; |
||||
}; |
||||
partition@qspi-device-tree { /* for testing purpose */ |
||||
label = "qspi-device-tree"; |
||||
reg = <0x600000 0x20000>; |
||||
}; |
||||
partition@qspi-rootfs { /* for testing purpose */ |
||||
label = "qspi-rootfs"; |
||||
reg = <0x620000 0x5E0000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&rtc { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sata { |
||||
status = "okay"; |
||||
/* SATA OOB timing settings */ |
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; |
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; |
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; |
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; |
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
||||
}; |
||||
|
||||
/* SD1 with level shifter */ |
||||
&sdhci1 { |
||||
status = "okay"; |
||||
no-1-8-v; /* for 1.0 silicon */ |
||||
}; |
||||
|
||||
&uart0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
/* ULPI SMSC USB3320 */ |
||||
&usb0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&dwc3_0 { |
||||
status = "okay"; |
||||
dr_mode = "host"; |
||||
}; |
||||
|
||||
&xilinx_drm { |
||||
status = "okay"; |
||||
clocks = <&si570_1>; |
||||
}; |
||||
|
||||
&xlnx_dp { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&xlnx_dp_sub { |
||||
status = "okay"; |
||||
xlnx,vid-clk-pl; |
||||
}; |
||||
|
||||
&xlnx_dp_snd_pcm0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&xlnx_dp_snd_pcm1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&xlnx_dp_snd_card { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&xlnx_dp_snd_codec0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&xlnx_dpdma { |
||||
status = "okay"; |
||||
}; |
||||
@ -0,0 +1,37 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1" |
||||
CONFIG_ARCH_ZYNQMP=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_ZYNQMP_USB=y |
||||
CONFIG_SYS_TEXT_BASE=0x8000000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_PROMPT="ZynqMP> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_TIMER=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_SYS_I2C_CADENCE=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_ZYNQ_SDHCI=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_BAR=y |
||||
CONFIG_SPI_FLASH_SPANSION=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_SPI_FLASH_WINBOND=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ZYNQ_GEM=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_ULPI_VIEWPORT=y |
||||
CONFIG_USB_ULPI=y |
||||
CONFIG_USB_GADGET=y |
||||
@ -0,0 +1,35 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2" |
||||
CONFIG_ARCH_ZYNQMP=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_ZYNQMP_USB=y |
||||
CONFIG_SYS_TEXT_BASE=0x8000000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_PROMPT="ZynqMP> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_TIMER=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_SYS_I2C_CADENCE=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_NAND_ARASAN=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_BAR=y |
||||
CONFIG_SPI_FLASH_SST=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ZYNQ_GEM=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_ULPI_VIEWPORT=y |
||||
CONFIG_USB_ULPI=y |
||||
CONFIG_USB_GADGET=y |
||||
@ -0,0 +1,24 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5" |
||||
CONFIG_ARCH_ZYNQMP=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_SYS_TEXT_BASE=0x8000000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_PROMPT="ZynqMP> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_TIMER=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_SYS_I2C_CADENCE=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_ZYNQ_SDHCI=y |
||||
CONFIG_DM_ETH=y |
||||
@ -0,0 +1,34 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" |
||||
CONFIG_ARCH_ZYNQMP=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_ZYNQMP_USB=y |
||||
CONFIG_SYS_TEXT_BASE=0x8000000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_PROMPT="ZynqMP> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_TIMER=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_ZYNQ_SDHCI=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_BAR=y |
||||
CONFIG_SPI_FLASH_SPANSION=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_SPI_FLASH_WINBOND=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ZYNQ_GEM=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_ULPI_VIEWPORT=y |
||||
CONFIG_USB_ULPI=y |
||||
CONFIG_USB_GADGET=y |
||||
@ -0,0 +1,34 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" |
||||
CONFIG_ARCH_ZYNQMP=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_ZYNQMP_USB=y |
||||
CONFIG_SYS_TEXT_BASE=0x8000000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_PROMPT="ZynqMP> " |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_TIMER=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_ZYNQ_SDHCI=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_BAR=y |
||||
CONFIG_SPI_FLASH_SPANSION=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_SPI_FLASH_WINBOND=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ZYNQ_GEM=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_ULPI_VIEWPORT=y |
||||
CONFIG_USB_ULPI=y |
||||
CONFIG_USB_GADGET=y |
||||
@ -0,0 +1,20 @@ |
||||
Cadence I2C controller Device Tree Bindings |
||||
------------------------------------------- |
||||
|
||||
Required properties: |
||||
- compatible : Should be "cdns,i2c-r1p10" or "xlnx,zynq-spi-r1p10". |
||||
- reg : Physical base address and size of I2C registers map. |
||||
- interrupts : Property with a value describing the interrupt |
||||
number. |
||||
- interrupt-parent : Must be core interrupt controller |
||||
- clocks : Clock phandles (see clock bindings for details). |
||||
|
||||
Example: |
||||
i2c0: i2c@e0004000 { |
||||
compatible = "cdns,i2c-r1p10"; |
||||
reg = <0xe0004000 0x1000>; |
||||
clocks = <&clkc 38>; |
||||
interrupts = <0 25 4>; |
||||
interrupt-parent = <&intc>; |
||||
status = "disabled"; |
||||
}; |
||||
@ -0,0 +1,335 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com> |
||||
* IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) |
||||
* |
||||
* This file is based on: drivers/i2c/zynq_i2c.c, |
||||
* with added driver-model support and code cleanup. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/types.h> |
||||
#include <linux/io.h> |
||||
#include <asm/errno.h> |
||||
#include <dm/device.h> |
||||
#include <dm/root.h> |
||||
#include <i2c.h> |
||||
#include <fdtdec.h> |
||||
#include <mapmem.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* i2c register set */ |
||||
struct cdns_i2c_regs { |
||||
u32 control; |
||||
u32 status; |
||||
u32 address; |
||||
u32 data; |
||||
u32 interrupt_status; |
||||
u32 transfer_size; |
||||
u32 slave_mon_pause; |
||||
u32 time_out; |
||||
u32 interrupt_mask; |
||||
u32 interrupt_enable; |
||||
u32 interrupt_disable; |
||||
}; |
||||
|
||||
/* Control register fields */ |
||||
#define CDNS_I2C_CONTROL_RW 0x00000001 |
||||
#define CDNS_I2C_CONTROL_MS 0x00000002 |
||||
#define CDNS_I2C_CONTROL_NEA 0x00000004 |
||||
#define CDNS_I2C_CONTROL_ACKEN 0x00000008 |
||||
#define CDNS_I2C_CONTROL_HOLD 0x00000010 |
||||
#define CDNS_I2C_CONTROL_SLVMON 0x00000020 |
||||
#define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040 |
||||
#define CDNS_I2C_CONTROL_DIV_B_SHIFT 8 |
||||
#define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00 |
||||
#define CDNS_I2C_CONTROL_DIV_A_SHIFT 14 |
||||
#define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000 |
||||
|
||||
/* Status register values */ |
||||
#define CDNS_I2C_STATUS_RXDV 0x00000020 |
||||
#define CDNS_I2C_STATUS_TXDV 0x00000040 |
||||
#define CDNS_I2C_STATUS_RXOVF 0x00000080 |
||||
#define CDNS_I2C_STATUS_BA 0x00000100 |
||||
|
||||
/* Interrupt register fields */ |
||||
#define CDNS_I2C_INTERRUPT_COMP 0x00000001 |
||||
#define CDNS_I2C_INTERRUPT_DATA 0x00000002 |
||||
#define CDNS_I2C_INTERRUPT_NACK 0x00000004 |
||||
#define CDNS_I2C_INTERRUPT_TO 0x00000008 |
||||
#define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010 |
||||
#define CDNS_I2C_INTERRUPT_RXOVF 0x00000020 |
||||
#define CDNS_I2C_INTERRUPT_TXOVF 0x00000040 |
||||
#define CDNS_I2C_INTERRUPT_RXUNF 0x00000080 |
||||
#define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200 |
||||
|
||||
#define CDNS_I2C_FIFO_DEPTH 16 |
||||
#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ |
||||
|
||||
#ifdef DEBUG |
||||
static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) |
||||
{ |
||||
int int_status; |
||||
int status; |
||||
int_status = readl(&cdns_i2c->interrupt_status); |
||||
|
||||
status = readl(&cdns_i2c->status); |
||||
if (int_status || status) { |
||||
debug("Status: "); |
||||
if (int_status & CDNS_I2C_INTERRUPT_COMP) |
||||
debug("COMP "); |
||||
if (int_status & CDNS_I2C_INTERRUPT_DATA) |
||||
debug("DATA "); |
||||
if (int_status & CDNS_I2C_INTERRUPT_NACK) |
||||
debug("NACK "); |
||||
if (int_status & CDNS_I2C_INTERRUPT_TO) |
||||
debug("TO "); |
||||
if (int_status & CDNS_I2C_INTERRUPT_SLVRDY) |
||||
debug("SLVRDY "); |
||||
if (int_status & CDNS_I2C_INTERRUPT_RXOVF) |
||||
debug("RXOVF "); |
||||
if (int_status & CDNS_I2C_INTERRUPT_TXOVF) |
||||
debug("TXOVF "); |
||||
if (int_status & CDNS_I2C_INTERRUPT_RXUNF) |
||||
debug("RXUNF "); |
||||
if (int_status & CDNS_I2C_INTERRUPT_ARBLOST) |
||||
debug("ARBLOST "); |
||||
if (status & CDNS_I2C_STATUS_RXDV) |
||||
debug("RXDV "); |
||||
if (status & CDNS_I2C_STATUS_TXDV) |
||||
debug("TXDV "); |
||||
if (status & CDNS_I2C_STATUS_RXOVF) |
||||
debug("RXOVF "); |
||||
if (status & CDNS_I2C_STATUS_BA) |
||||
debug("BA "); |
||||
debug("TS%d ", readl(&cdns_i2c->transfer_size)); |
||||
debug("\n"); |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
struct i2c_cdns_bus { |
||||
int id; |
||||
struct cdns_i2c_regs __iomem *regs; /* register base */ |
||||
}; |
||||
|
||||
|
||||
/** cdns_i2c_probe() - Probe method
|
||||
* @dev: udevice pointer |
||||
* |
||||
* DM callback called when device is probed |
||||
*/ |
||||
static int cdns_i2c_probe(struct udevice *dev) |
||||
{ |
||||
struct i2c_cdns_bus *bus = dev_get_priv(dev); |
||||
|
||||
bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev); |
||||
if (!bus->regs) |
||||
return -ENOMEM; |
||||
|
||||
/* TODO: Calculate dividers based on CPU_CLK_1X */ |
||||
/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ |
||||
writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) | |
||||
(2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control); |
||||
|
||||
/* Enable master mode, ack, and 7-bit addressing */ |
||||
setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS | |
||||
CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA); |
||||
|
||||
debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int cdns_i2c_remove(struct udevice *dev) |
||||
{ |
||||
struct i2c_cdns_bus *bus = dev_get_priv(dev); |
||||
|
||||
debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); |
||||
|
||||
unmap_sysmem(bus->regs); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Wait for an interrupt */ |
||||
static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask) |
||||
{ |
||||
int timeout, int_status; |
||||
|
||||
for (timeout = 0; timeout < 100; timeout++) { |
||||
udelay(100); |
||||
int_status = readl(&cdns_i2c->interrupt_status); |
||||
if (int_status & mask) |
||||
break; |
||||
} |
||||
|
||||
/* Clear interrupt status flags */ |
||||
writel(int_status & mask, &cdns_i2c->interrupt_status); |
||||
|
||||
return int_status & mask; |
||||
} |
||||
|
||||
static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) |
||||
{ |
||||
if (speed != 100000) { |
||||
printf("%s, failed to set clock speed to %u\n", __func__, |
||||
speed); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Probe to see if a chip is present. */ |
||||
static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr, |
||||
uint chip_flags) |
||||
{ |
||||
struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus); |
||||
struct cdns_i2c_regs *regs = i2c_bus->regs; |
||||
|
||||
/* Attempt to read a byte */ |
||||
setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | |
||||
CDNS_I2C_CONTROL_RW); |
||||
clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); |
||||
writel(0xFF, ®s->interrupt_status); |
||||
writel(chip_addr, ®s->address); |
||||
writel(1, ®s->transfer_size); |
||||
|
||||
return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | |
||||
CDNS_I2C_INTERRUPT_NACK) & |
||||
CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; |
||||
} |
||||
|
||||
static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, |
||||
u32 len, bool next_is_read) |
||||
{ |
||||
u8 *cur_data = data; |
||||
|
||||
struct cdns_i2c_regs *regs = i2c_bus->regs; |
||||
|
||||
setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | |
||||
CDNS_I2C_CONTROL_HOLD); |
||||
|
||||
/* if next is a read, we need to clear HOLD, doesn't work */ |
||||
if (next_is_read) |
||||
clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); |
||||
|
||||
clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW); |
||||
|
||||
writel(0xFF, ®s->interrupt_status); |
||||
writel(addr, ®s->address); |
||||
|
||||
while (len--) { |
||||
writel(*(cur_data++), ®s->data); |
||||
if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) { |
||||
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) { |
||||
/* Release the bus */ |
||||
clrbits_le32(®s->control, |
||||
CDNS_I2C_CONTROL_HOLD); |
||||
return -ETIMEDOUT; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* All done... release the bus */ |
||||
clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); |
||||
/* Wait for the address and data to be sent */ |
||||
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) |
||||
return -ETIMEDOUT; |
||||
return 0; |
||||
} |
||||
|
||||
static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, |
||||
u32 len) |
||||
{ |
||||
u32 status; |
||||
u32 i = 0; |
||||
u8 *cur_data = data; |
||||
|
||||
/* TODO: Fix this */ |
||||
struct cdns_i2c_regs *regs = i2c_bus->regs; |
||||
|
||||
/* Check the hardware can handle the requested bytes */ |
||||
if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX)) |
||||
return -EINVAL; |
||||
|
||||
setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | |
||||
CDNS_I2C_CONTROL_RW); |
||||
|
||||
/* Start reading data */ |
||||
writel(addr, ®s->address); |
||||
writel(len, ®s->transfer_size); |
||||
|
||||
/* Wait for data */ |
||||
do { |
||||
status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | |
||||
CDNS_I2C_INTERRUPT_DATA); |
||||
if (!status) { |
||||
/* Release the bus */ |
||||
clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); |
||||
return -ETIMEDOUT; |
||||
} |
||||
debug("Read %d bytes\n", |
||||
len - readl(®s->transfer_size)); |
||||
for (; i < len - readl(®s->transfer_size); i++) |
||||
*(cur_data++) = readl(®s->data); |
||||
} while (readl(®s->transfer_size) != 0); |
||||
/* All done... release the bus */ |
||||
clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); |
||||
|
||||
#ifdef DEBUG |
||||
cdns_i2c_debug_status(regs); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, |
||||
int nmsgs) |
||||
{ |
||||
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); |
||||
int ret; |
||||
|
||||
debug("i2c_xfer: %d messages\n", nmsgs); |
||||
for (; nmsgs > 0; nmsgs--, msg++) { |
||||
bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); |
||||
|
||||
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); |
||||
if (msg->flags & I2C_M_RD) { |
||||
ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, |
||||
msg->len); |
||||
} else { |
||||
ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, |
||||
msg->len, next_is_read); |
||||
} |
||||
if (ret) { |
||||
debug("i2c_write: error sending\n"); |
||||
return -EREMOTEIO; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct dm_i2c_ops cdns_i2c_ops = { |
||||
.xfer = cdns_i2c_xfer, |
||||
.probe_chip = cdns_i2c_probe_chip, |
||||
.set_bus_speed = cdns_i2c_set_bus_speed, |
||||
}; |
||||
|
||||
static const struct udevice_id cdns_i2c_of_match[] = { |
||||
{ .compatible = "cdns,i2c-r1p10" }, |
||||
{ /* end of table */ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(cdns_i2c) = { |
||||
.name = "i2c-cdns", |
||||
.id = UCLASS_I2C, |
||||
.of_match = cdns_i2c_of_match, |
||||
.probe = cdns_i2c_probe, |
||||
.remove = cdns_i2c_remove, |
||||
.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus), |
||||
.ops = &cdns_i2c_ops, |
||||
}; |
||||
@ -0,0 +1,29 @@ |
||||
/*
|
||||
* Configuration for Xilinx ZynqMP zc1751 XM015 DC1 |
||||
* |
||||
* (C) Copyright 2015 Xilinx, Inc. |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H |
||||
#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H |
||||
|
||||
#define CONFIG_ZYNQ_SDHCI0 |
||||
#define CONFIG_ZYNQ_SDHCI1 |
||||
#define CONFIG_AHCI |
||||
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} |
||||
|
||||
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm015 dc1" |
||||
|
||||
#define CONFIG_KERNEL_FDT_OFST_SIZE \ |
||||
"kernel_offset=0x400000\0" \
|
||||
"fdt_offset=0x2400000\0" \
|
||||
"kernel_size=0x2000000\0" \
|
||||
"fdt_size=0x80000\0" \
|
||||
"board=zc1751-dc1\0" |
||||
|
||||
#include <configs/xilinx_zynqmp.h> |
||||
|
||||
#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */ |
||||
@ -0,0 +1,26 @@ |
||||
/*
|
||||
* Configuration for Xilinx ZynqMP zc1751 XM016 DC2 |
||||
* |
||||
* (C) Copyright 2015 Xilinx, Inc. |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H |
||||
#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H |
||||
|
||||
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR} |
||||
|
||||
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2" |
||||
|
||||
#define CONFIG_KERNEL_FDT_OFST_SIZE \ |
||||
"kernel_offset=0x400000\0" \
|
||||
"fdt_offset=0x2400000\0" \
|
||||
"kernel_size=0x2000000\0" \
|
||||
"fdt_size=0x80000\0" \
|
||||
"board=zc1751-dc2\0" |
||||
|
||||
#include <configs/xilinx_zynqmp.h> |
||||
|
||||
#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */ |
||||
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* Configuration for Xilinx ZynqMP zc1751 XM019 DC5 |
||||
* |
||||
* (C) Copyright 2015 Xilinx, Inc. |
||||
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H |
||||
#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H |
||||
|
||||
#define CONFIG_ZYNQ_SDHCI0 |
||||
|
||||
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5" |
||||
|
||||
#define CONFIG_KERNEL_FDT_OFST_SIZE \ |
||||
"kernel_offset=0x400000\0" \
|
||||
"fdt_offset=0x2400000\0" \
|
||||
"kernel_size=0x2000000\0" \
|
||||
"fdt_size=0x80000\0" \
|
||||
"board=zc1751-dc5\0" |
||||
|
||||
#include <configs/xilinx_zynqmp.h> |
||||
|
||||
#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */ |
||||
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* Configuration for Xilinx ZynqMP zcu102 |
||||
* |
||||
* (C) Copyright 2015 Xilinx, Inc. |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_ZYNQMP_ZCU102_H |
||||
#define __CONFIG_ZYNQMP_ZCU102_H |
||||
|
||||
#define CONFIG_ZYNQ_SDHCI1 |
||||
#define CONFIG_ZYNQ_I2C0 |
||||
#define CONFIG_ZYNQ_I2C1 |
||||
#define CONFIG_SYS_I2C_MAX_HOPS 1 |
||||
#define CONFIG_SYS_NUM_I2C_BUSES 18 |
||||
#define CONFIG_SYS_I2C_BUSES { \ |
||||
{0, {I2C_NULL_HOP} }, \
|
||||
{0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
|
||||
{0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
|
||||
{0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
|
||||
{1, {I2C_NULL_HOP} }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
|
||||
{1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
|
||||
} |
||||
|
||||
#define CONFIG_SYS_I2C_ZYNQ |
||||
#define CONFIG_PCA953X |
||||
#define CONFIG_CMD_PCA953X |
||||
#define CONFIG_CMD_PCA953X_INFO |
||||
|
||||
#define CONFIG_AHCI |
||||
#define CONFIG_SATA_CEVA |
||||
|
||||
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} |
||||
|
||||
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102" |
||||
|
||||
#define CONFIG_KERNEL_FDT_OFST_SIZE \ |
||||
"kernel_offset=0x180000\0" \
|
||||
"fdt_offset=0x100000\0" \
|
||||
"kernel_size=0x1e00000\0" \
|
||||
"fdt_size=0x80000\0" \
|
||||
"board=zcu102\0" |
||||
|
||||
#include <configs/xilinx_zynqmp.h> |
||||
|
||||
#endif /* __CONFIG_ZYNQMP_ZCU102_H */ |
||||
Loading…
Reference in new issue