add support for Zephyr Engineering ZPC.1900 board * Patch by Anders Larsen, 23 Sep 2003: add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only implemented for the x86 architecture)master
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o flash.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,31 @@ |
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# ZPC.1900 board
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#
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TEXT_BASE = 0xFFF00000
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#TEXT_BASE = 0x03000000
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@ -0,0 +1,818 @@ |
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/*
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* (C) Copyright 2002 |
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* Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com |
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* |
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* Copyright (C) 2003 Arabella Software Ltd. |
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* Yuli Barcohen <yuli@arabellasw.com> |
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* Modified to work with AMD flashes |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#undef DEBUG_FLASH |
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/*
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* This file implements a Common Flash Interface (CFI) driver for U-Boot. |
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* The width of the port and the width of the chips are determined at initialization. |
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* These widths are used to calculate the address for access CFI data structures. |
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* It has been tested on an Intel Strataflash implementation and AMD 29F016D. |
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* |
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* References |
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* JEDEC Standard JESD68 - Common Flash Interface (CFI) |
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* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes |
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* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets |
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* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet |
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* |
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* TODO |
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* |
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* Use Primary Extended Query table (PRI) and Alternate Algorithm Query |
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* Table (ALT) to determine if protection is available |
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* |
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* Add support for other command sets Use the PRI and ALT to determine command set |
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* Verify erase and program timeouts. |
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*/ |
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#define FLASH_CMD_CFI 0x98 |
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#define FLASH_CMD_READ_ID 0x90 |
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#define FLASH_CMD_RESET 0xff |
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#define FLASH_CMD_BLOCK_ERASE 0x20 |
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#define FLASH_CMD_ERASE_CONFIRM 0xD0 |
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#define FLASH_CMD_WRITE 0x40 |
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#define FLASH_CMD_PROTECT 0x60 |
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#define FLASH_CMD_PROTECT_SET 0x01 |
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#define FLASH_CMD_PROTECT_CLEAR 0xD0 |
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#define FLASH_CMD_CLEAR_STATUS 0x50 |
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#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 |
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#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 |
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#define FLASH_STATUS_DONE 0x80 |
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#define FLASH_STATUS_ESS 0x40 |
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#define FLASH_STATUS_ECLBS 0x20 |
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#define FLASH_STATUS_PSLBS 0x10 |
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#define FLASH_STATUS_VPENS 0x08 |
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#define FLASH_STATUS_PSS 0x04 |
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#define FLASH_STATUS_DPS 0x02 |
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#define FLASH_STATUS_R 0x01 |
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#define FLASH_STATUS_PROTECT 0x01 |
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#define AMD_CMD_RESET 0xF0 |
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#define AMD_CMD_WRITE 0xA0 |
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#define AMD_CMD_ERASE_START 0x80 |
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#define AMD_CMD_ERASE_SECTOR 0x30 |
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#define AMD_STATUS_TOGGLE 0x40 |
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#define AMD_STATUS_ERROR 0x20 |
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#define FLASH_OFFSET_CFI 0x55 |
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#define FLASH_OFFSET_CFI_RESP 0x10 |
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#define FLASH_OFFSET_WTOUT 0x1F |
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#define FLASH_OFFSET_WBTOUT 0x20 |
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#define FLASH_OFFSET_ETOUT 0x21 |
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#define FLASH_OFFSET_CETOUT 0x22 |
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#define FLASH_OFFSET_WMAX_TOUT 0x23 |
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#define FLASH_OFFSET_WBMAX_TOUT 0x24 |
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#define FLASH_OFFSET_EMAX_TOUT 0x25 |
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#define FLASH_OFFSET_CEMAX_TOUT 0x26 |
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#define FLASH_OFFSET_SIZE 0x27 |
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#define FLASH_OFFSET_INTERFACE 0x28 |
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#define FLASH_OFFSET_BUFFER_SIZE 0x2A |
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#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C |
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#define FLASH_OFFSET_ERASE_REGIONS 0x2D |
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#define FLASH_OFFSET_PROTECT 0x02 |
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#define FLASH_OFFSET_USER_PROTECTION 0x85 |
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#define FLASH_OFFSET_INTEL_PROTECTION 0x81 |
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#define FLASH_MAN_CFI 0x01000000 |
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typedef union { |
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unsigned char c; |
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unsigned short w; |
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unsigned long l; |
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} cfiword_t; |
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typedef union { |
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volatile unsigned char *cp; |
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volatile unsigned short *wp; |
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volatile unsigned long *lp; |
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} cfiptr_t; |
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#define NUM_ERASE_REGIONS 4 |
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static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); |
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static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); |
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static void flash_write_cmd(flash_info_t * info, int sect, uint offset, uchar cmd); |
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static void flash_unlock_seq(flash_info_t *info); |
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static int flash_isequal(flash_info_t * info, int sect, uint offset, uchar cmd); |
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static int flash_isset(flash_info_t * info, int sect, uint offset, uchar cmd); |
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static int flash_toggle(flash_info_t * info, int sect, uint offset, uchar cmd); |
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static int flash_detect_cfi(flash_info_t * info); |
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static ulong flash_get_size (ulong base, int banknum); |
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static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); |
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static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); |
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#ifdef CFG_FLASH_USE_BUFFER_WRITE |
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static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); |
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#endif |
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/*-----------------------------------------------------------------------
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* create an address based on the offset and the port width |
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*/ |
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inline uchar * flash_make_addr(flash_info_t * info, int sect, uint offset) |
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{ |
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return ((uchar *)(info->start[sect] + (offset * info->portwidth))); |
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} |
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/*-----------------------------------------------------------------------
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* read a character at a port width address |
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*/ |
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inline uchar flash_read_uchar(flash_info_t * info, uint offset) |
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{ |
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uchar *cp; |
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cp = flash_make_addr(info, 0, offset); |
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return (cp[info->portwidth - 1]); |
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} |
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/*-----------------------------------------------------------------------
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* read a short word by swapping for ppc format. |
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*/ |
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ushort flash_read_ushort(flash_info_t * info, int sect, uint offset) |
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{ |
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uchar * addr; |
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addr = flash_make_addr(info, sect, offset); |
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return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); |
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} |
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/*-----------------------------------------------------------------------
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* read a long word by picking the least significant byte of each maiximum |
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* port size word. Swap for ppc format. |
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*/ |
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ulong flash_read_long(flash_info_t * info, int sect, uint offset) |
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{ |
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uchar * addr; |
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addr = flash_make_addr(info, sect, offset); |
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return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | |
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(addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size = 0; |
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int i; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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size += flash_info[i].size = flash_get_size(bank_base[i], i); |
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if (flash_info[i].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", |
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i, flash_info[i].size, flash_info[i].size << 20); |
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} |
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} |
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/* Monitor protection ON by default */ |
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#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_MONITOR_BASE, |
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CFG_MONITOR_BASE + monitor_flash_len - 1, |
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&flash_info[0]); |
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#endif |
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return (size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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int rcode = 0; |
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int prot; |
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int sect; |
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if( info->flash_id != FLASH_MAN_CFI) { |
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printf ("Can't erase unknown flash type - aborted\n"); |
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return 1; |
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} |
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if ((s_first < 0) || (s_first > s_last)) { |
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printf ("- no sectors to erase\n"); |
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return 1; |
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} |
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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for (sect = s_first; sect<=s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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#ifdef INTEL_COMMANDS |
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flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); |
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flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); |
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flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); |
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#else |
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flash_unlock_seq(info); |
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flash_write_cmd(info, sect, 0x555, AMD_CMD_ERASE_START); |
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flash_unlock_seq(info); |
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flash_write_cmd(info, sect, 0, AMD_CMD_ERASE_SECTOR); |
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#endif |
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if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { |
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rcode = 1; |
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} else |
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printf("."); |
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} |
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} |
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printf (" done\n"); |
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return rcode; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id != FLASH_MAN_CFI) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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printf("CFI conformant FLASH (%d x %d)", |
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(info->portwidth << 3 ), (info->chipwidth << 3 )); |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", |
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info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n"); |
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printf (" %08lX%5s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " " |
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); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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ulong wp; |
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ulong cp; |
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int aln; |
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cfiword_t cword; |
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int i, rc; |
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/* get lower aligned address */ |
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wp = (addr & ~(info->portwidth - 1)); |
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/* handle unaligned start */ |
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if((aln = addr - wp) != 0) { |
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cword.l = 0; |
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cp = wp; |
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for(i=0;i<aln; ++i, ++cp) |
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flash_add_byte(info, &cword, (*(uchar *)cp)); |
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for(; (i< info->portwidth) && (cnt > 0) ; i++) { |
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flash_add_byte(info, &cword, *src++); |
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cnt--; |
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cp++; |
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} |
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for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) |
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flash_add_byte(info, &cword, (*(uchar *)cp)); |
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if((rc = flash_write_cfiword(info, wp, cword)) != 0) |
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return rc; |
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wp = cp; |
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} |
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#ifdef CFG_FLASH_USE_BUFFER_WRITE |
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while(cnt >= info->portwidth) { |
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i = info->buffer_size > cnt? cnt: info->buffer_size; |
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if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) |
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return rc; |
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wp += i; |
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src += i; |
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cnt -=i; |
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} |
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#else |
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/* handle the aligned part */ |
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while(cnt >= info->portwidth) { |
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cword.l = 0; |
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for(i = 0; i < info->portwidth; i++) { |
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flash_add_byte(info, &cword, *src++); |
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} |
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if((rc = flash_write_cfiword(info, wp, cword)) != 0) |
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return rc; |
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wp += info->portwidth; |
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cnt -= info->portwidth; |
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} |
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#endif /* CFG_FLASH_USE_BUFFER_WRITE */ |
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if (cnt == 0) { |
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return (0); |
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} |
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/*
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* handle unaligned tail bytes |
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*/ |
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cword.l = 0; |
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for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { |
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flash_add_byte(info, &cword, *src++); |
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--cnt; |
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} |
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for (; i<info->portwidth; ++i, ++cp) { |
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flash_add_byte(info, & cword, (*(uchar *)cp)); |
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} |
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return flash_write_cfiword(info, wp, cword); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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#ifdef CFG_FLASH_PROTECTION |
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int flash_real_protect(flash_info_t *info, long sector, int prot) |
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{ |
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int retcode = 0; |
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flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
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flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); |
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if(prot) |
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flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); |
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else |
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flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); |
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if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, |
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prot?"protect":"unprotect")) == 0) { |
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info->protect[sector] = prot; |
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/* Intel's unprotect unprotects all locking */ |
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if(prot == 0) { |
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int i; |
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for(i = 0 ; i<info->sector_count; i++) { |
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if(info->protect[i]) |
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flash_real_protect(info, i, 1); |
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} |
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} |
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} |
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return retcode; |
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} |
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#endif /* CFG_FLASH_PROTECTION */ |
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/*-----------------------------------------------------------------------
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* wait for XSR.7 to be set. Time out with an error if it does not. |
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* This routine does not set the flash to read-array mode. |
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*/ |
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static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) |
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{ |
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ulong start; |
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/* Wait for command completion */ |
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start = get_timer (0); |
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while ( |
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#ifdef INTEL_COMMANDS |
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!flash_isset(info, sector, 0, FLASH_STATUS_DONE) |
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#else |
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flash_toggle(info, sector, 0, AMD_STATUS_TOGGLE) |
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#endif |
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) { |
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if (get_timer(start) > info->erase_blk_tout) { |
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printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); |
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#ifdef INTEL_COMMANDS |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); |
||||
#else |
||||
flash_write_cmd(info, sector, 0, AMD_CMD_RESET); |
||||
#endif |
||||
return ERR_TIMOUT; |
||||
} |
||||
} |
||||
return ERR_OK; |
||||
} |
||||
/*-----------------------------------------------------------------------
|
||||
* Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. |
||||
* This routine sets the flash to read-array mode. |
||||
*/ |
||||
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) |
||||
{ |
||||
int retcode; |
||||
retcode = flash_status_check(info, sector, tout, prompt); |
||||
#ifdef INTEL_COMMANDS |
||||
if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { |
||||
retcode = ERR_INVAL; |
||||
printf("Flash %s error at address %lx\n", prompt,info->start[sector]); |
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ |
||||
printf("Command Sequence Error.\n"); |
||||
} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ |
||||
printf("Block Erase Error.\n"); |
||||
retcode = ERR_NOT_ERASED; |
||||
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { |
||||
printf("Locking Error\n"); |
||||
} |
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ |
||||
printf("Block locked.\n"); |
||||
retcode = ERR_PROTECTED; |
||||
} |
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) |
||||
printf("Vpp Low Error.\n"); |
||||
} |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); |
||||
#endif |
||||
return retcode; |
||||
} |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) |
||||
{ |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
cword->c = c; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
cword->w = (cword->w << 8) | c; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
cword->l = (cword->l << 8) | c; |
||||
} |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* make a proper sized command based on the port and chip widths |
||||
*/ |
||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) |
||||
{ |
||||
int i; |
||||
uchar *cp = (uchar *)cmdbuf; |
||||
for(i=0; i< info->portwidth; i++) |
||||
*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; |
||||
} |
||||
|
||||
/*
|
||||
* Write a proper sized command to the correct address |
||||
*/ |
||||
static void flash_write_cmd(flash_info_t * info, int sect, uint offset, uchar cmd) |
||||
{ |
||||
|
||||
volatile cfiptr_t addr; |
||||
cfiword_t cword; |
||||
addr.cp = flash_make_addr(info, sect, offset); |
||||
flash_make_cmd(info, cmd, &cword); |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
*addr.cp = cword.c; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
*addr.wp = cword.w; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
*addr.lp = cword.l; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static void flash_unlock_seq(flash_info_t *info) |
||||
{ |
||||
flash_write_cmd(info, 0, 0x555, 0xAA); |
||||
flash_write_cmd(info, 0, 0x2AA, 0x55); |
||||
} |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static int flash_isequal(flash_info_t * info, int sect, uint offset, uchar cmd) |
||||
{ |
||||
cfiptr_t cptr; |
||||
cfiword_t cword; |
||||
int retval; |
||||
cptr.cp = flash_make_addr(info, sect, offset); |
||||
flash_make_cmd(info, cmd, &cword); |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
retval = (cptr.cp[0] == cword.c); |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
retval = (cptr.wp[0] == cword.w); |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
retval = (cptr.lp[0] == cword.l); |
||||
break; |
||||
default: |
||||
retval = 0; |
||||
break; |
||||
} |
||||
return retval; |
||||
} |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static int flash_isset(flash_info_t * info, int sect, uint offset, uchar cmd) |
||||
{ |
||||
cfiptr_t cptr; |
||||
cfiword_t cword; |
||||
int retval; |
||||
cptr.cp = flash_make_addr(info, sect, offset); |
||||
flash_make_cmd(info, cmd, &cword); |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
retval = ((cptr.cp[0] & cword.c) == cword.c); |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
retval = ((cptr.wp[0] & cword.w) == cword.w); |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
retval = ((cptr.lp[0] & cword.l) == cword.l); |
||||
break; |
||||
default: |
||||
retval = 0; |
||||
break; |
||||
} |
||||
return retval; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static int flash_toggle(flash_info_t * info, int sect, uint offset, uchar cmd) |
||||
{ |
||||
cfiptr_t cptr; |
||||
cfiword_t cword; |
||||
int retval; |
||||
cptr.cp = flash_make_addr(info, sect, offset); |
||||
flash_make_cmd(info, cmd, &cword); |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c)); |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w)); |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l)); |
||||
break; |
||||
default: |
||||
retval = 0; |
||||
break; |
||||
} |
||||
return retval; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* detect if flash is compatible with the Common Flash Interface (CFI) |
||||
* http://www.jedec.org/download/search/jesd68.pdf
|
||||
* |
||||
*/ |
||||
static int flash_detect_cfi(flash_info_t * info) |
||||
{ |
||||
|
||||
for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; |
||||
info->portwidth <<= 1) { |
||||
for(info->chipwidth =FLASH_CFI_BY8; |
||||
info->chipwidth <= info->portwidth; |
||||
info->chipwidth <<= 1) { |
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); |
||||
flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); |
||||
if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && |
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && |
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
* |
||||
*/ |
||||
static ulong flash_get_size (ulong base, int banknum) |
||||
{ |
||||
flash_info_t * info = &flash_info[banknum]; |
||||
int i, j; |
||||
int sect_cnt; |
||||
unsigned long sector; |
||||
unsigned long tmp; |
||||
int size_ratio; |
||||
uchar num_erase_regions; |
||||
int erase_region_size; |
||||
int erase_region_count; |
||||
|
||||
info->start[0] = base; |
||||
|
||||
if(flash_detect_cfi(info)){ |
||||
size_ratio = info->portwidth / info->chipwidth; |
||||
num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); |
||||
#ifdef DEBUG_FLASH |
||||
printf("found %d erase regions\n", num_erase_regions); |
||||
#endif |
||||
sect_cnt = 0; |
||||
sector = base; |
||||
for(i = 0 ; i < num_erase_regions; i++) { |
||||
if(i > NUM_ERASE_REGIONS) { |
||||
printf("%d erase regions found, only %d used\n", |
||||
num_erase_regions, NUM_ERASE_REGIONS); |
||||
break; |
||||
} |
||||
tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); |
||||
erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; |
||||
tmp >>= 16; |
||||
erase_region_count = (tmp & 0xffff) +1; |
||||
for(j = 0; j< erase_region_count; j++) { |
||||
info->start[sect_cnt] = sector; |
||||
sector += (erase_region_size * size_ratio); |
||||
info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); |
||||
sect_cnt++; |
||||
} |
||||
} |
||||
|
||||
info->sector_count = sect_cnt; |
||||
/* multiply the size by the number of chips */ |
||||
info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; |
||||
info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); |
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); |
||||
info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); |
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); |
||||
info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); |
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); |
||||
info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; |
||||
info->flash_id = FLASH_MAN_CFI; |
||||
} |
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); |
||||
return(info->size); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) |
||||
{ |
||||
|
||||
cfiptr_t ctladdr; |
||||
cfiptr_t cptr; |
||||
int flag; |
||||
|
||||
ctladdr.cp = flash_make_addr(info, 0, 0); |
||||
cptr.cp = (uchar *)dest; |
||||
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
flag = ((cptr.cp[0] & cword.c) == cword.c); |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
flag = ((cptr.wp[0] & cword.w) == cword.w); |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
flag = ((cptr.lp[0] & cword.l) == cword.l); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
if(!flag) |
||||
return 2; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
#ifdef INTEL_COMMANDS |
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); |
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); |
||||
#else |
||||
flash_unlock_seq(info); |
||||
flash_write_cmd(info, 0, 0x555, AMD_CMD_WRITE); |
||||
#endif |
||||
|
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
cptr.cp[0] = cword.c; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
cptr.wp[0] = cword.w; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
cptr.lp[0] = cword.l; |
||||
break; |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if(flag) |
||||
enable_interrupts(); |
||||
|
||||
return flash_full_status_check(info, 0, info->write_tout, "write"); |
||||
} |
||||
|
||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE |
||||
|
||||
/* loop through the sectors from the highest address
|
||||
* when the passed address is greater or equal to the sector address |
||||
* we have a match |
||||
*/ |
||||
static int find_sector(flash_info_t *info, ulong addr) |
||||
{ |
||||
int sector; |
||||
for(sector = info->sector_count - 1; sector >= 0; sector--) { |
||||
if(addr >= info->start[sector]) |
||||
break; |
||||
} |
||||
return sector; |
||||
} |
||||
|
||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) |
||||
{ |
||||
|
||||
int sector; |
||||
int cnt; |
||||
int retcode; |
||||
volatile cfiptr_t src; |
||||
volatile cfiptr_t dst; |
||||
|
||||
src.cp = cp; |
||||
dst.cp = (uchar *)dest; |
||||
sector = find_sector(info, dest); |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); |
||||
if((retcode = flash_status_check(info, sector, info->buffer_write_tout, |
||||
"write to buffer")) == ERR_OK) { |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
cnt = len; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
cnt = len >> 1; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
cnt = len >> 2; |
||||
break; |
||||
default: |
||||
return ERR_INVAL; |
||||
break; |
||||
} |
||||
flash_write_cmd(info, sector, 0, (uchar)cnt-1); |
||||
while(cnt-- > 0) { |
||||
switch(info->portwidth) { |
||||
case FLASH_CFI_8BIT: |
||||
*dst.cp++ = *src.cp++; |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
*dst.wp++ = *src.wp++; |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
*dst.lp++ = *src.lp++; |
||||
break; |
||||
default: |
||||
return ERR_INVAL; |
||||
break; |
||||
} |
||||
} |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); |
||||
retcode = flash_full_status_check(info, sector, info->buffer_write_tout, |
||||
"buffer write"); |
||||
} |
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
||||
return retcode; |
||||
} |
||||
#endif /* CFG_USE_FLASH_BUFFER_WRITE */ |
@ -0,0 +1,122 @@ |
||||
/* |
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Modified by Yuli Barcohen <yuli@arabellasw.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc8260/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
@ -0,0 +1,308 @@ |
||||
/*
|
||||
* (C) Copyright 2001-2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2003 Arabella Software Ltd. |
||||
* Yuli Barcohen <yuli@arabellasw.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <mpc8260.h> |
||||
#include <asm/m8260_pci.h> |
||||
#include <i2c.h> |
||||
#include <spd.h> |
||||
#include <miiphy.h> |
||||
|
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
*/ |
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
|
||||
/* Port A */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ |
||||
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ |
||||
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ |
||||
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ |
||||
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ |
||||
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ |
||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ |
||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ |
||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ |
||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ |
||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ |
||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ |
||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ |
||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ |
||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
||||
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
||||
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */ |
||||
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ |
||||
/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ |
||||
/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ |
||||
/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ |
||||
/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ |
||||
/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ |
||||
/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ |
||||
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ |
||||
/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ |
||||
}, |
||||
|
||||
/* Port B */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
||||
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
||||
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
||||
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
||||
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
||||
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
||||
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
||||
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
}, |
||||
|
||||
/* Port C */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ |
||||
/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ |
||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */ |
||||
/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ |
||||
/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ |
||||
/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ |
||||
/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ |
||||
/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ |
||||
/* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
||||
/* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ |
||||
/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ |
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ |
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ |
||||
/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ |
||||
/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ |
||||
/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ |
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */ |
||||
/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ |
||||
/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ |
||||
/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ |
||||
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */ |
||||
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */ |
||||
/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ |
||||
/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ |
||||
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ |
||||
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ |
||||
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ |
||||
/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ |
||||
/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ |
||||
/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ |
||||
/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ |
||||
}, |
||||
|
||||
/* Port D */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
||||
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
||||
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
||||
/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ |
||||
/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ |
||||
/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ |
||||
/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ |
||||
/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ |
||||
/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ |
||||
/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ |
||||
/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ |
||||
/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ |
||||
/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ |
||||
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ |
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ |
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
||||
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
||||
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
||||
/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ |
||||
/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ |
||||
/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ |
||||
/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ |
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
} |
||||
}; |
||||
|
||||
#ifdef CFG_NVRAM_ACCESS_ROUTINE |
||||
void *nvram_read(void *dest, long src, size_t count) |
||||
{ |
||||
return memcpy(dest, (const void *)src, count); |
||||
} |
||||
|
||||
void nvram_write(long dest, const void *src, size_t count) |
||||
{ |
||||
vu_char *p1 = (vu_char *)(CFG_EEPROM + 0x1555); |
||||
vu_char *p2 = (vu_char *)(CFG_EEPROM + 0x0AAA); |
||||
vu_char *d = (vu_char *)dest; |
||||
const uchar *s = (const uchar *)src; |
||||
|
||||
/* Unprotect the EEPROM */ |
||||
*p1 = 0xAA; |
||||
*p2 = 0x55; |
||||
*p1 = 0x80; |
||||
*p1 = 0xAA; |
||||
*p2 = 0x55; |
||||
*p1 = 0x20; |
||||
udelay(10000); |
||||
|
||||
/* Write the data to the EEPROM */ |
||||
while (count--) { |
||||
*d++ = *s++; |
||||
while (*(d - 1) != *(s - 1)) |
||||
/* wait */; |
||||
} |
||||
|
||||
/* Protect the EEPROM */ |
||||
*p1 = 0xAA; |
||||
*p2 = 0x55; |
||||
*p1 = 0xA0; |
||||
udelay(10000); |
||||
} |
||||
#endif /* CFG_NVRAM_ACCESS_ROUTINE */ |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
vu_char *bcsr = (vu_char *)CFG_BCSR; |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8260_t *memctl = &immap->im_memctl; |
||||
vu_char *ramaddr; |
||||
uchar c = 0xFF; |
||||
long int msize = CFG_SDRAM_SIZE; |
||||
uint psdmr = CFG_PSDMR; |
||||
int i; |
||||
|
||||
if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */ |
||||
immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; |
||||
immap->im_siu_conf.sc_siumcr = |
||||
(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) |
||||
| SIUMCR_LBPC01; |
||||
} |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
immap->im_siu_conf.sc_ppc_acr = 0x03; |
||||
immap->im_siu_conf.sc_ppc_alrh = 0x30126745; |
||||
immap->im_siu_conf.sc_tescr1 = 0x00004000; |
||||
|
||||
memctl->memc_mptpr = CFG_MPTPR; |
||||
|
||||
#ifdef CFG_LSDRAM_BASE |
||||
/*
|
||||
Initialise local bus SDRAM only if the pins |
||||
are configured as local bus pins and not as PCI. |
||||
*/ |
||||
if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { |
||||
memctl->memc_lsrt = CFG_LSRT; |
||||
memctl->memc_or4 = 0xFFC01480; |
||||
memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; |
||||
memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; |
||||
ramaddr = (vu_char *)CFG_LSDRAM_BASE; |
||||
*ramaddr = c; |
||||
memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR; |
||||
for (i = 0; i < 8; i++) |
||||
*ramaddr = c; |
||||
memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_MRW; |
||||
*ramaddr = c; |
||||
memctl->memc_lsdmr = CFG_LSDMR | PSDMR_RFEN; |
||||
} |
||||
#endif /* CFG_LSDRAM_BASE */ |
||||
|
||||
/* Initialise 60x bus SDRAM */ |
||||
memctl->memc_psrt = CFG_PSRT; |
||||
memctl->memc_or2 = 0xFC0028C0; |
||||
memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; |
||||
/*
|
||||
* The mode data for Mode Register Write command must appear on |
||||
* the address lines during a mode-set cycle. It is driven by |
||||
* the memory controller, in single PowerQUICC II mode, |
||||
* according to PSDMR[CL] and PSDMR[BL] fields. In |
||||
* 60x-compatible mode, software must drive the correct value on |
||||
* the address lines. BL=0 because for 64-bit port size burst |
||||
* length must be 4. |
||||
*/ |
||||
ramaddr = (vu_char *)(CFG_SDRAM_BASE | |
||||
((psdmr & PSDMR_CL_MSK) << 7) | 0x10); |
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ |
||||
*ramaddr = c; |
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ |
||||
for (i = 0; i < 8; i++) |
||||
*ramaddr = c; |
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ |
||||
*ramaddr = c; |
||||
memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ |
||||
*ramaddr = c; |
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
/* Return total 60x bus SDRAM size */ |
||||
return msize * 1024 * 1024; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
vu_char *bcsr = (vu_char *)CFG_BCSR; |
||||
|
||||
printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40); |
||||
return 0; |
||||
} |
@ -0,0 +1,283 @@ |
||||
/*
|
||||
* Copyright (C) 2003 Arabella Software Ltd. |
||||
* Yuli Barcohen <yuli@arabellasw.com> |
||||
* |
||||
* U-Boot configuration for Zephyr Engineering ZPC.1900 board. |
||||
* This port was developed and tested on Revision C board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
||||
#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */ |
||||
#define CPU_ID_STR "MPC8265" |
||||
|
||||
#undef DEBUG |
||||
|
||||
#undef CONFIG_BOARD_PRE_INIT /* Don't call board_pre_init */ |
||||
|
||||
/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* Select serial console configuration |
||||
* |
||||
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC /* Console is on SMC */ |
||||
#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ |
||||
#undef CONFIG_CONS_NONE /* It's not on external UART */ |
||||
#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ |
||||
|
||||
/*
|
||||
* Select ethernet configuration |
||||
* |
||||
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, |
||||
* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for |
||||
* SCC, 1-3 for FCC) |
||||
* |
||||
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines |
||||
* must be defined elsewhere (as for the console), or CFG_CMD_NET must |
||||
* be removed from CONFIG_COMMANDS to remove support for networking. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* No external Ethernet */ |
||||
|
||||
#ifdef CONFIG_ETHER_ON_FCC |
||||
|
||||
#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */ |
||||
|
||||
#if (CONFIG_ETHER_INDEX == 2) |
||||
/*
|
||||
* - Rx clock is CLK13 |
||||
* - Tx clock is CLK14 |
||||
* - Select bus for bd/buffers (see 28-13) |
||||
* - Full duplex |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) |
||||
|
||||
#endif /* CONFIG_ETHER_INDEX */ |
||||
|
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ |
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications |
||||
*/ |
||||
#define MDIO_PORT 2 /* Port C */ |
||||
#define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
||||
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) |
||||
#define MDIO_READ ((iop->pdat & 0x00400000) != 0) |
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ |
||||
else iop->pdat &= ~0x00400000 |
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ |
||||
else iop->pdat &= ~0x00200000 |
||||
|
||||
#define MIIDELAY udelay(1) |
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC */ |
||||
|
||||
#ifndef CONFIG_8260_CLKIN |
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ |
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_BMP | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DOC | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_FDC | \
|
||||
CFG_CMD_FDOS | \
|
||||
CFG_CMD_HWFLOW | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_KGDB | \
|
||||
CFG_CMD_MMC | \
|
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PCMCIA | \
|
||||
CFG_CMD_SCSI | \
|
||||
CFG_CMD_SPI | \
|
||||
CFG_CMD_USB | \
|
||||
CFG_CMD_VFD ) ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp" |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ |
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ |
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ |
||||
#endif |
||||
|
||||
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ |
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
#define CFG_FLASH_BASE 0xFFE00000 |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
||||
#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_DEFAULT_IMMR 0x0F010000 |
||||
|
||||
#define CFG_IMMR 0xF0000000 |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_SIZE 64 |
||||
#define CFG_FLSIMM_BASE 0xFC000000 |
||||
#define CFG_LSDRAM_BASE 0xFE000000 |
||||
#define CFG_BCSR 0xFEA00000 |
||||
#define CFG_EEPROM 0xFEB00000 |
||||
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
||||
|
||||
#define BCSR_PCI_MODE 0x01 |
||||
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/* Hard reset configuration word */ |
||||
#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 |\ |
||||
HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\
|
||||
HRCW_APPC10 |\
|
||||
HRCW_MODCK_H0101 \
|
||||
) /* 0x14820205 */ |
||||
/* No slaves */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
#if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM) |
||||
#define CFG_ENV_IS_IN_NVRAM 1 |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
# define CFG_ENV_SECT_SIZE 0x10000 |
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE) |
||||
#else |
||||
# define CFG_ENV_ADDR (CFG_EEPROM + 0x400) |
||||
# define CFG_ENV_SIZE 0x200 |
||||
# define CFG_NVRAM_ACCESS_ROUTINE |
||||
#endif |
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
#define CFG_HID0_INIT 0 |
||||
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) |
||||
|
||||
#define CFG_HID2 0 |
||||
|
||||
#define CFG_SIUMCR 0x42200000 |
||||
#define CFG_SYPCR 0xFFFFFFC3 |
||||
#define CFG_BCR 0x90400000 |
||||
#define CFG_SCCR SCCR_DFBRG01 |
||||
|
||||
#define CFG_RMR RMR_CSRE |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
#define CFG_RCCR 0 |
||||
|
||||
#define CFG_PSDMR 0x014EB45A |
||||
#define CFG_PSRT 0x0C |
||||
#define CFG_LSDMR 0x008AB552 |
||||
#define CFG_LSRT 0x0E |
||||
#define CFG_MPTPR 0x4000 |
||||
|
||||
#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 |
||||
#define CFG_OR0_PRELIM 0xFFE00856 |
||||
#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 |
||||
#define CFG_OR5_PRELIM 0xFFFF03F6 |
||||
#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801 |
||||
#define CFG_OR6_PRELIM 0xFE000856 |
||||
#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 |
||||
#define CFG_OR7_PRELIM 0xFFFF83F6 |
||||
|
||||
#define CFG_RESET_ADDRESS 0xC0000000 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue