Signed-off-by: Matthew Fettke <mfettke@videon-central.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> Acked-by: John Rigby <jrigby@freescale.com>master
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o mii.o
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$(LIB): .depend $(OBJS) |
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$(AR) crv $@ $(OBJS)
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xffe00000
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@ -0,0 +1,112 @@ |
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/*
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* (C) Copyright 2000-2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/immap.h> |
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#define PERIOD 13 /* system bus period in ns */ |
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#define SDRAM_TREFI 7800 /* in ns */ |
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int checkboard(void) |
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{ |
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puts("Board: "); |
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puts("Freescale MCF5275 EVB\n"); |
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return 0; |
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}; |
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long int initdram(int board_type) |
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{ |
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volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); |
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volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); |
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gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */ |
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/* Set up chip select */ |
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sdp->sdbar0 = CFG_SDRAM_BASE; |
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sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V; |
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/* Set up timing */ |
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sdp->sdcfg1 = 0x83711630; |
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sdp->sdcfg2 = 0x46770000; |
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/* Enable clock */ |
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sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE; |
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/* Set precharge */ |
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sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; |
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/* Dummy write to start SDRAM */ |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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/* Send LEMR */ |
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sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR |
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| MCF_SDRAMC_SDMR_AD(0x0) |
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| MCF_SDRAMC_SDMR_CMD; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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/* Send LMR */ |
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sdp->sdmr = 0x058d0000; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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/* Stop sending commands */ |
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sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); |
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/* Set precharge */ |
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sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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/* Stop manual precharge, send 2 IREF */ |
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sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL); |
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sdp->sdcr |= MCF_SDRAMC_SDCR_IREF; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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/* Write mode register, clear reset DLL */ |
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sdp->sdmr = 0x018d0000; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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/* Stop sending commands */ |
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sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); |
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sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN); |
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/* Turn on auto refresh, lock SDMR */ |
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sdp->sdcr = |
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MCF_SDRAMC_SDCR_CKE |
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| MCF_SDRAMC_SDCR_REF |
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| MCF_SDRAMC_SDCR_MUX(1) |
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/* 1 added to round up */ |
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| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) |
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| MCF_SDRAMC_SDCR_DQS_OE(0x3); |
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return CFG_SDRAM_SIZE * 1024 * 1024; |
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}; |
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int testdram(void) |
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{ |
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/* TODO: XXX XXX XXX */ |
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printf("DRAM test not implemented!\n"); |
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return (0); |
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} |
@ -0,0 +1,319 @@ |
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/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/fec.h> |
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#include <asm/immap.h> |
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#include <config.h> |
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#include <net.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) |
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#undef MII_DEBUG |
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#undef ET_DEBUG |
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int fecpin_setclear(struct eth_device *dev, int setclear) |
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{ |
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struct fec_info_s *info = (struct fec_info_s *) dev->priv; |
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volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; |
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if (setclear) { |
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/* Enable Ethernet pins */ |
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if (info->iobase == CFG_FEC0_IOBASE) { |
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gpio->par_feci2c |= 0x0F00; |
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gpio->par_fec0hl |= 0xC0; |
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} else { |
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gpio->par_feci2c |= 0x00A0; |
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gpio->par_fec1hl |= 0xC0; |
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} |
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} else { |
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if (info->iobase == CFG_FEC0_IOBASE) { |
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gpio->par_feci2c &= ~0x0F00; |
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gpio->par_fec0hl &= ~0xC0; |
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} else { |
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gpio->par_feci2c &= ~0x00A0; |
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gpio->par_fec1hl &= ~0xC0; |
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} |
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} |
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return 0; |
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} |
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#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) |
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#include <miiphy.h> |
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/* Make MII read/write commands for the FEC. */ |
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#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) |
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#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) |
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/* PHY identification */ |
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#define PHY_ID_LXT970 0x78100000 /* LXT970 */ |
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#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ |
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#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ |
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#define PHY_ID_QS6612 0x01814400 /* QS6612 */ |
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#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ |
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#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ |
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#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ |
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#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ |
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#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ |
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#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ |
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#define STR_ID_LXT970 "LXT970" |
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#define STR_ID_LXT971 "LXT971" |
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#define STR_ID_82555 "Intel82555" |
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#define STR_ID_QS6612 "QS6612" |
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#define STR_ID_AMD79C784 "AMD79C784" |
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#define STR_ID_LSI80225 "LSI80225" |
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#define STR_ID_LSI80225B "LSI80225/B" |
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#define STR_ID_DP83848VV "N83848" |
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#define STR_ID_DP83849 "N83849" |
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#define STR_ID_KS8721BL "KS8721BL" |
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/****************************************************************************
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* mii_init -- Initialize the MII for MII command without ethernet |
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* This function is a subset of eth_init |
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**************************************************************************** |
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*/ |
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void mii_reset(struct fec_info_s *info) |
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{ |
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volatile fec_t *fecp = (fec_t *) (info->miibase); |
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int i; |
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fecp->ecr = FEC_ECR_RESET; |
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for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { |
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udelay(1); |
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} |
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if (i == FEC_RESET_DELAY) { |
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printf("FEC_RESET_DELAY timeout\n"); |
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} |
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} |
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/* send command to phy using mii, wait for result */ |
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uint mii_send(uint mii_cmd) |
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{ |
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struct fec_info_s *info; |
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struct eth_device *dev; |
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volatile fec_t *ep; |
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uint mii_reply; |
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int j = 0; |
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/* retrieve from register structure */ |
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dev = eth_get_dev(); |
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info = dev->priv; |
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ep = (fec_t *) info->miibase; |
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ep->mmfr = mii_cmd; /* command to phy */ |
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/* wait for mii complete */ |
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while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { |
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udelay(1); |
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j++; |
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} |
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if (j >= MCFFEC_TOUT_LOOP) { |
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printf("MII not complete\n"); |
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return -1; |
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} |
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mii_reply = ep->mmfr; /* result from phy */ |
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ep->eir = FEC_EIR_MII; /* clear MII complete */ |
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#ifdef ET_DEBUG |
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printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", |
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__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); |
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#endif |
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return (mii_reply & 0xffff); /* data read from phy */ |
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} |
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#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ |
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#if defined(CFG_DISCOVER_PHY) |
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int mii_discover_phy(struct eth_device *dev) |
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{ |
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#define MAX_PHY_PASSES 11 |
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struct fec_info_s *info = dev->priv; |
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int phyaddr, pass; |
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uint phyno, phytype; |
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if (info->phyname_init) |
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return info->phy_addr; |
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phyaddr = -1; /* didn't find a PHY yet */ |
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for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { |
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if (pass > 1) { |
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/* PHY may need more time to recover from reset.
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* The LXT970 needs 50ms typical, no maximum is |
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* specified, so wait 10ms before try again. |
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* With 11 passes this gives it 100ms to wake up. |
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*/ |
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udelay(10000); /* wait 10ms */ |
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} |
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for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { |
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phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); |
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#ifdef ET_DEBUG |
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printf("PHY type 0x%x pass %d type\n", phytype, pass); |
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#endif |
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if (phytype != 0xffff) { |
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phyaddr = phyno; |
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phytype <<= 16; |
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phytype |= |
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mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); |
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switch (phytype & 0xffffffff) { |
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case PHY_ID_KS8721BL: |
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strcpy(info->phy_name, |
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STR_ID_KS8721BL); |
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info->phyname_init = 1; |
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break; |
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default: |
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strcpy(info->phy_name, "unknown"); |
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info->phyname_init = 1; |
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break; |
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} |
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#ifdef ET_DEBUG |
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printf("PHY @ 0x%x pass %d type ", phyno, pass); |
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switch (phytype & 0xffffffff) { |
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case PHY_ID_KS8721BL: |
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printf(STR_ID_KS8721BL); |
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break; |
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default: |
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printf("0x%08x\n", phytype); |
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break; |
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} |
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#endif |
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} |
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} |
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} |
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if (phyaddr < 0) |
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printf("No PHY device found.\n"); |
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return phyaddr; |
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} |
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#endif /* CFG_DISCOVER_PHY */ |
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void mii_init(void) __attribute__((weak,alias("__mii_init"))); |
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void __mii_init(void) |
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{ |
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volatile fec_t *fecp; |
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struct fec_info_s *info; |
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struct eth_device *dev; |
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int miispd = 0, i = 0; |
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u16 autoneg = 0; |
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/* retrieve from register structure */ |
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dev = eth_get_dev(); |
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info = dev->priv; |
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fecp = (fec_t *) info->miibase; |
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fecpin_setclear(dev, 1); |
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mii_reset(info); |
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/* We use strictly polling mode only */ |
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fecp->eimr = 0; |
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/* Clear any pending interrupt */ |
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fecp->eir = 0xffffffff; |
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/* Set MII speed */ |
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miispd = (gd->bus_clk / 1000000) / 5; |
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fecp->mscr = miispd << 1; |
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info->phy_addr = mii_discover_phy(dev); |
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#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) |
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while (i < MCFFEC_TOUT_LOOP) { |
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autoneg = 0; |
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miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); |
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i++; |
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if ((autoneg & AUTONEGLINK) == AUTONEGLINK) |
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break; |
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udelay(500); |
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} |
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if (i >= MCFFEC_TOUT_LOOP) { |
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printf("Auto Negotiation not complete\n"); |
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} |
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/* adapt to the half/full speed settings */ |
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info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; |
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info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); |
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} |
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/*****************************************************************************
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* Read and write a MII PHY register, routines used by MII Utilities |
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* |
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* FIXME: These routines are expected to return 0 on success, but mii_send |
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* does _not_ return an error code. Maybe 0xFFFF means error, i.e. |
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* no PHY connected... |
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* For now always return 0. |
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* FIXME: These routines only work after calling eth_init() at least once! |
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* Otherwise they hang in mii_send() !!! Sorry! |
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*****************************************************************************/ |
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int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, |
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unsigned short *value) |
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{ |
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short rdreg; /* register working value */ |
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#ifdef MII_DEBUG |
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printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); |
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#endif |
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rdreg = mii_send(mk_mii_read(addr, reg)); |
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*value = rdreg; |
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#ifdef MII_DEBUG |
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printf("0x%04x\n", *value); |
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#endif |
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return 0; |
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} |
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int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, |
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unsigned short value) |
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{ |
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short rdreg; /* register working value */ |
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#ifdef MII_DEBUG |
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printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); |
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#endif |
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rdreg = mii_send(mk_mii_write(addr, reg, value)); |
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#ifdef MII_DEBUG |
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printf("0x%04x\n", value); |
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#endif |
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return 0; |
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} |
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#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ |
@ -0,0 +1,141 @@ |
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/* |
||||
* (C) Copyright 2000-2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(m68k) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mcf52x2/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/string.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .; |
||||
common/environment.o(.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
__got_start = .; |
||||
*(.got) |
||||
__got_end = .; |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
_sbss = .; |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
_ebss = .; |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,223 @@ |
||||
/*
|
||||
* Configuation settings for the Motorola MC5275EVB board. |
||||
* |
||||
* By Arthur Shipkowski <art@videon-central.com> |
||||
* Copyright (C) 2005 Videon Central, Inc. |
||||
* |
||||
* Based off of M5272C3 board code by Josef Baumgartner |
||||
* <josef.baumgartner@telex.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef _M5275EVB_H |
||||
#define _M5275EVB_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_MCF52x2 /* define processor family */ |
||||
#define CONFIG_M5275 /* define processor type */ |
||||
#define CONFIG_M5275EVB /* define board type */ |
||||
|
||||
#define CONFIG_MCFTMR |
||||
|
||||
#define CONFIG_MCFUART |
||||
#define CFG_UART_PORT (0) |
||||
#define CONFIG_BAUDRATE 19200 |
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash |
||||
*/ |
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM |
||||
#define CFG_ENV_OFFSET 0x4000 |
||||
#define CFG_ENV_SECT_SIZE 0x2000 |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_IS_EMBEDDED 1 |
||||
#else |
||||
#define CFG_ENV_ADDR 0xffe04000 |
||||
#define CFG_ENV_SECT_SIZE 0x2000 |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/* Available command configuration */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_DHCP |
||||
|
||||
#undef CONFIG_CMD_LOADS |
||||
#undef CONFIG_CMD_LOADB |
||||
|
||||
#define CONFIG_MCFFEC |
||||
#ifdef CONFIG_MCFFEC |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_MII 1 |
||||
#define CFG_DISCOVER_PHY |
||||
#define CFG_RX_ETH_BUFFER 8 |
||||
#define CFG_FAULT_ECHO_LINK_DOWN |
||||
#define CFG_FEC0_PINMUX 0 |
||||
#define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE |
||||
#define CFG_FEC1_PINMUX 0 |
||||
#define CFG_FEC1_MIIBASE CFG_FEC1_IOBASE |
||||
#define MCFFEC_TOUT_LOOP 50000 |
||||
#define CONFIG_HAS_ETH1 |
||||
/* If CFG_DISCOVER_PHY is not defined - hardcoded */ |
||||
#ifndef CFG_DISCOVER_PHY |
||||
#define FECDUPLEX FULL |
||||
#define FECSPEED _100BASET |
||||
#else |
||||
#ifndef CFG_FAULT_ECHO_LINK_DOWN |
||||
#define CFG_FAULT_ECHO_LINK_DOWN |
||||
#endif |
||||
#endif |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CONFIG_HARD_I2C /* I2C with hw support */ |
||||
#undef CONFIG_SOFT_I2C |
||||
#define CFG_I2C_SPEED 80000 |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_OFFSET 0x00000300 |
||||
#define CFG_IMMR CFG_MBAR |
||||
|
||||
#ifdef CONFIG_MCFFEC |
||||
#define CONFIG_ETHADDR 00:06:3b:01:41:55 |
||||
#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60 |
||||
#endif |
||||
|
||||
#define CFG_PROMPT "-> " |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
|
||||
#if (CONFIG_CMD_KGDB) |
||||
# define CFG_CBSIZE 1024 |
||||
#else |
||||
# define CFG_CBSIZE 256 |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
#define CFG_MAXARGS 16 |
||||
#define CFG_BARGSIZE CFG_CBSIZE |
||||
|
||||
#define CFG_LOAD_ADDR 0x800000 |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
#define CONFIG_BOOTCOMMAND "bootm ffe40000" |
||||
#define CFG_MEMTEST_START 0x400 |
||||
#define CFG_MEMTEST_END 0x380000 |
||||
|
||||
#define CFG_HZ 1000 |
||||
#define CFG_CLK 150000000 |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
#define CFG_MBAR 0x40000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0x20000000 |
||||
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ |
||||
#define CFG_GBL_DATA_SIZE 1000 /* bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ |
||||
#define CFG_FLASH_BASE 0xffe00000 |
||||
|
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM |
||||
#define CFG_MONITOR_BASE 0x20000 |
||||
#else |
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN 0x20000 |
||||
#define CFG_MALLOC_LEN (256 << 10) |
||||
#define CFG_BOOTPARAMS_LEN 64*1024 |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization ?? |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial mmap for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ |
||||
#define CFG_FLASH_ERASE_TOUT 1000 |
||||
|
||||
#define CFG_FLASH_CFI 1 |
||||
#define CFG_FLASH_CFI_DRIVER 1 |
||||
#define CFG_FLASH_SIZE 0x200000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory bank definitions |
||||
*/ |
||||
#define CFG_AR0_PRELIM (CFG_FLASH_BASE >> 16) |
||||
#define CFG_CR0_PRELIM 0x1980 |
||||
#define CFG_MR0_PRELIM 0x001F0001 |
||||
|
||||
#define CFG_AR1_PRELIM 0x3000 |
||||
#define CFG_CR1_PRELIM 0x1900 |
||||
#define CFG_MR1_PRELIM 0x00070001 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Port configuration |
||||
*/ |
||||
#define CFG_FECI2C 0x0FA0 |
||||
|
||||
#endif /* _M5275EVB_H */ |
Loading…
Reference in new issue