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@ -183,6 +183,70 @@ typedef struct vidinfo { |
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u_long mmio; /* Memory mapped registers */ |
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} vidinfo_t; |
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#elif defined(CONFIG_EXYNOS_FB) |
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enum { |
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FIMD_RGB_INTERFACE = 1, |
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FIMD_CPU_INTERFACE = 2, |
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}; |
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typedef struct vidinfo { |
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ushort vl_col; /* Number of columns (i.e. 640) */ |
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ushort vl_row; /* Number of rows (i.e. 480) */ |
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ushort vl_width; /* Width of display area in millimeters */ |
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ushort vl_height; /* Height of display area in millimeters */ |
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/* LCD configuration register */ |
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u_char vl_freq; /* Frequency */ |
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u_char vl_clkp; /* Clock polarity */ |
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u_char vl_oep; /* Output Enable polarity */ |
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u_char vl_hsp; /* Horizontal Sync polarity */ |
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u_char vl_vsp; /* Vertical Sync polarity */ |
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u_char vl_dp; /* Data polarity */ |
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u_char vl_bpix; /* Bits per pixel */ |
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/* Horizontal control register. Timing from data sheet */ |
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u_char vl_hspw; /* Horz sync pulse width */ |
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u_char vl_hfpd; /* Wait before of line */ |
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u_char vl_hbpd; /* Wait end of line */ |
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/* Vertical control register. */ |
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u_char vl_vspw; /* Vertical sync pulse width */ |
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u_char vl_vfpd; /* Wait before of frame */ |
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u_char vl_vbpd; /* Wait end of frame */ |
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u_char vl_cmd_allow_len; /* Wait end of frame */ |
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void (*cfg_gpio)(void); |
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void (*backlight_on)(unsigned int onoff); |
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void (*reset_lcd)(void); |
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void (*lcd_power_on)(void); |
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void (*cfg_ldo)(void); |
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void (*enable_ldo)(unsigned int onoff); |
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void (*mipi_power)(void); |
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void (*backlight_reset)(void); |
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unsigned int win_id; |
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unsigned int init_delay; |
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unsigned int power_on_delay; |
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unsigned int reset_delay; |
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unsigned int interface_mode; |
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unsigned int mipi_enabled; |
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unsigned int cs_setup; |
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unsigned int wr_setup; |
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unsigned int wr_act; |
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unsigned int wr_hold; |
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/* parent clock name(MPLL, EPLL or VPLL) */ |
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unsigned int pclk_name; |
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/* ratio value for source clock from parent clock. */ |
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unsigned int sclk_div; |
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unsigned int dual_lcd_enabled; |
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} vidinfo_t; |
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void init_panel_info(vidinfo_t *vid); |
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#else |
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typedef struct vidinfo { |
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