Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>master
Bill Richardson
12 years ago
committed by
Simon Glass
parent
468ebf190a
commit
55ae10f8db
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/*
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* Copyright (c) 2012, Google Inc. All rights reserved. |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _X86_GPIO_H_ |
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#define _X86_GPIO_H_ |
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#include <asm-generic/gpio.h> |
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#endif /* _X86_GPIO_H_ */ |
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/*
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* Copyright (c) 2012 The Chromium OS Authors. |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed |
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* through the PCI bus. Each PCI device has 256 bytes of configuration space, |
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* consisting of a standard header and a device-specific set of registers. PCI |
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* bus 0, device 31, function 0 gives us access to the chipset GPIOs (among |
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* other things). Within the PCI configuration space, the GPIOBASE register |
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* tells us where in the device's I/O region we can find more registers to |
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* actually access the GPIOs. |
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* |
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* PCI bus/device/function 0:1f:0 => PCI config registers |
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* PCI config register "GPIOBASE" |
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* PCI I/O space + [GPIOBASE] => start of GPIO registers |
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* GPIO registers => gpio pin function, direction, value |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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#include <asm/gpio.h> |
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#include <asm/io.h> |
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/* Where in config space is the register that points to the GPIO registers? */ |
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#define PCI_CFG_GPIOBASE 0x48 |
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/*
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* There are often more than 32 GPIOs, depending on the ICH version. |
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* For now, we just support bank 0 because it's the same for all. |
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*/ |
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#define GPIO_MAX 31 |
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/* Within the I/O space, where are the registers to control the GPIOs? */ |
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#define OFS_GPIO_USE_SEL 0x00 |
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#define OFS_GPIO_IO_SEL 0x04 |
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#define OFS_GP_LVL 0x0C |
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static pci_dev_t dev; /* handle for 0:1f:0 */ |
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static u32 gpiobase; /* offset into I/O space */ |
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static int found_it_once; /* valid GPIO device? */ |
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static int in_use[GPIO_MAX]; /* "lock" for access to pins */ |
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static int gpio_init(void) |
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{ |
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u8 tmpbyte; |
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u16 tmpword; |
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u32 tmplong; |
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/* Have we already done this? */ |
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if (found_it_once) |
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return 0; |
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/* Where should it be? */ |
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dev = PCI_BDF(0, 0x1f, 0); |
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/* Is the device present? */ |
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pci_read_config_word(dev, PCI_VENDOR_ID, &tmpword); |
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if (tmpword != PCI_VENDOR_ID_INTEL) { |
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debug("%s: wrong VendorID\n", __func__); |
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return -1; |
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} |
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/*
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* We'd like to check the Device ID too, but pretty much any |
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* value is either a) correct with slight differences, or b) |
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* correct but undocumented. We'll have to check other things |
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* instead... |
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*/ |
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/* I/O should already be enabled (it's a RO bit). */ |
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pci_read_config_word(dev, PCI_COMMAND, &tmpword); |
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if (!(tmpword & PCI_COMMAND_IO)) { |
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debug("%s: device IO not enabled\n", __func__); |
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return -1; |
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} |
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/* Header Type must be normal (bits 6-0 only; see spec.) */ |
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &tmpbyte); |
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if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { |
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debug("%s: invalid Header type\n", __func__); |
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return -1; |
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} |
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/* Base Class must be a bridge device */ |
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pci_read_config_byte(dev, PCI_CLASS_CODE, &tmpbyte); |
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if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { |
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debug("%s: invalid class\n", __func__); |
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return -1; |
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} |
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/* Sub Class must be ISA */ |
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pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &tmpbyte); |
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if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { |
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debug("%s: invalid subclass\n", __func__); |
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return -1; |
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} |
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/* Programming Interface must be 0x00 (no others exist) */ |
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pci_read_config_byte(dev, PCI_CLASS_PROG, &tmpbyte); |
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if (tmpbyte != 0x00) { |
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debug("%s: invalid interface type\n", __func__); |
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return -1; |
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} |
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/*
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* GPIOBASE moved to its current offset with ICH6, but prior to |
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* that it was unused (or undocumented). Check that it looks |
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* okay: not all ones or zeros, and mapped to I/O space (bit 0). |
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*/ |
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pci_read_config_dword(dev, PCI_CFG_GPIOBASE, &tmplong); |
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if (tmplong == 0x00000000 || tmplong == 0xffffffff || |
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!(tmplong & 0x00000001)) { |
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debug("%s: unexpected GPIOBASE value\n", __func__); |
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return -1; |
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} |
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/*
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* Okay, I guess we're looking at the right device. The actual |
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* GPIO registers are in the PCI device's I/O space, starting |
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* at the offset that we just read. Bit 0 indicates that it's |
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* an I/O address, not a memory address, so mask that off. |
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*/ |
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gpiobase = tmplong & 0xfffffffe; |
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/* Finally. These are the droids we're looking for. */ |
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found_it_once = 1; |
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return 0; |
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} |
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int gpio_request(unsigned gpio, const char *label /* UNUSED */) |
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{ |
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u32 tmplong; |
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/* Are we doing it wrong? */ |
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if (gpio > GPIO_MAX || in_use[gpio]) { |
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debug("%s: gpio unavailable\n", __func__); |
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return -1; |
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} |
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/* Is the hardware ready? */ |
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if (gpio_init()) { |
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debug("%s: gpio_init failed\n", __func__); |
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return -1; |
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} |
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/*
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* Make sure that the GPIO pin we want isn't already in use for some |
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* built-in hardware function. We have to check this for every |
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* requested pin. |
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*/ |
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tmplong = inl(gpiobase + OFS_GPIO_USE_SEL); |
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if (!(tmplong & (1UL << gpio))) { |
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debug("%s: reserved for internal use\n", __func__); |
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return -1; |
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} |
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in_use[gpio] = 1; |
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return 0; |
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} |
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int gpio_free(unsigned gpio) |
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{ |
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if (gpio > GPIO_MAX || !in_use[gpio]) { |
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debug("%s: gpio unavailable\n", __func__); |
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return -1; |
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} |
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in_use[gpio] = 0; |
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return 0; |
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} |
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int gpio_direction_input(unsigned gpio) |
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{ |
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u32 tmplong; |
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if (gpio > GPIO_MAX || !in_use[gpio]) { |
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debug("%s: gpio unavailable\n", __func__); |
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return -1; |
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} |
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tmplong = inl(gpiobase + OFS_GPIO_IO_SEL); |
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tmplong |= (1UL << gpio); |
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outl(gpiobase + OFS_GPIO_IO_SEL, tmplong); |
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return 0; |
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} |
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int gpio_direction_output(unsigned gpio, int value) |
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{ |
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u32 tmplong; |
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if (gpio > GPIO_MAX || !in_use[gpio]) { |
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debug("%s: gpio unavailable\n", __func__); |
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return -1; |
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} |
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tmplong = inl(gpiobase + OFS_GPIO_IO_SEL); |
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tmplong &= ~(1UL << gpio); |
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outl(gpiobase + OFS_GPIO_IO_SEL, tmplong); |
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return 0; |
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} |
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int gpio_get_value(unsigned gpio) |
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{ |
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u32 tmplong; |
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if (gpio > GPIO_MAX || !in_use[gpio]) { |
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debug("%s: gpio unavailable\n", __func__); |
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return -1; |
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} |
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tmplong = inl(gpiobase + OFS_GP_LVL); |
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return (tmplong & (1UL << gpio)) ? 1 : 0; |
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} |
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int gpio_set_value(unsigned gpio, int value) |
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{ |
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u32 tmplong; |
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if (gpio > GPIO_MAX || !in_use[gpio]) { |
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debug("%s: gpio unavailable\n", __func__); |
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return -1; |
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} |
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tmplong = inl(gpiobase + OFS_GP_LVL); |
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if (value) |
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tmplong |= (1UL << gpio); |
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else |
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tmplong &= ~(1UL << gpio); |
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outl(gpiobase + OFS_GP_LVL, tmplong); |
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return 0; |
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} |
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