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Driver/DDR: Moving Freescale DDR driver to a common driver

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Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
master
York Sun 11 years ago
parent ac6880782d
commit 5614e71b49
170 changed files with 416 additions and 408 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 1
      Makefile
  2. 41
      README
  3. 6
      arch/powerpc/cpu/mpc83xx/Makefile
  4. 4
      arch/powerpc/cpu/mpc83xx/ecc.c
  5. 45
      arch/powerpc/cpu/mpc85xx/Makefile
  6. 16
      arch/powerpc/cpu/mpc85xx/cpu.c
  7. 2
      arch/powerpc/cpu/mpc85xx/mp.c
  8. 3
      arch/powerpc/cpu/mpc86xx/Makefile
  9. 6
      arch/powerpc/cpu/mpc8xxx/Makefile
  10. 29
      arch/powerpc/cpu/mpc8xxx/ddr/Makefile
  11. 6
      arch/powerpc/include/asm/config.h
  12. 13
      arch/powerpc/include/asm/config_mpc85xx.h
  13. 2
      arch/powerpc/include/asm/config_mpc86xx.h
  14. 6
      arch/powerpc/include/asm/immap_83xx.h
  15. 6
      arch/powerpc/include/asm/immap_85xx.h
  16. 4
      arch/powerpc/include/asm/immap_86xx.h
  17. 4
      board/exmeritus/hww1u1a/ddr.c
  18. 4
      board/exmeritus/hww1u1a/hww1u1a.c
  19. 6
      board/freescale/b4860qds/ddr.c
  20. 4
      board/freescale/bsc9131rdb/ddr.c
  21. 4
      board/freescale/bsc9131rdb/spl_minimal.c
  22. 4
      board/freescale/bsc9132qds/bsc9132qds.c
  23. 4
      board/freescale/bsc9132qds/ddr.c
  24. 4
      board/freescale/bsc9132qds/spl_minimal.c
  25. 4
      board/freescale/c29xpcie/ddr.c
  26. 4
      board/freescale/corenet_ds/ddr.c
  27. 2
      board/freescale/corenet_ds/eth_p4080.c
  28. 2
      board/freescale/corenet_ds/p3041ds_ddr.c
  29. 2
      board/freescale/corenet_ds/p4080ds_ddr.c
  30. 2
      board/freescale/corenet_ds/p5020ds_ddr.c
  31. 2
      board/freescale/corenet_ds/p5040ds_ddr.c
  32. 2
      board/freescale/mpc8349emds/Makefile
  33. 4
      board/freescale/mpc8349emds/ddr.c
  34. 6
      board/freescale/mpc8349emds/mpc8349emds.c
  35. 4
      board/freescale/mpc8536ds/ddr.c
  36. 2
      board/freescale/mpc8536ds/mpc8536ds.c
  37. 4
      board/freescale/mpc8540ads/ddr.c
  38. 4
      board/freescale/mpc8540ads/mpc8540ads.c
  39. 4
      board/freescale/mpc8541cds/ddr.c
  40. 2
      board/freescale/mpc8541cds/mpc8541cds.c
  41. 4
      board/freescale/mpc8544ds/ddr.c
  42. 2
      board/freescale/mpc8544ds/mpc8544ds.c
  43. 4
      board/freescale/mpc8548cds/ddr.c
  44. 2
      board/freescale/mpc8548cds/mpc8548cds.c
  45. 4
      board/freescale/mpc8555cds/ddr.c
  46. 2
      board/freescale/mpc8555cds/mpc8555cds.c
  47. 4
      board/freescale/mpc8560ads/ddr.c
  48. 4
      board/freescale/mpc8560ads/mpc8560ads.c
  49. 4
      board/freescale/mpc8568mds/ddr.c
  50. 2
      board/freescale/mpc8568mds/mpc8568mds.c
  51. 4
      board/freescale/mpc8569mds/ddr.c
  52. 4
      board/freescale/mpc8569mds/mpc8569mds.c
  53. 4
      board/freescale/mpc8572ds/ddr.c
  54. 2
      board/freescale/mpc8572ds/mpc8572ds.c
  55. 2
      board/freescale/mpc8610hpcd/Makefile
  56. 4
      board/freescale/mpc8610hpcd/ddr.c
  57. 2
      board/freescale/mpc8610hpcd/mpc8610hpcd.c
  58. 2
      board/freescale/mpc8641hpcn/Makefile
  59. 4
      board/freescale/mpc8641hpcn/ddr.c
  60. 2
      board/freescale/mpc8641hpcn/mpc8641hpcn.c
  61. 4
      board/freescale/p1010rdb/ddr.c
  62. 4
      board/freescale/p1010rdb/spl_minimal.c
  63. 4
      board/freescale/p1022ds/ddr.c
  64. 2
      board/freescale/p1022ds/p1022ds.c
  65. 2
      board/freescale/p1022ds/spl_minimal.c
  66. 4
      board/freescale/p1023rdb/ddr.c
  67. 2
      board/freescale/p1023rdb/p1023rdb.c
  68. 4
      board/freescale/p1023rds/p1023rds.c
  69. 2
      board/freescale/p1_p2_rdb/ddr.c
  70. 4
      board/freescale/p1_p2_rdb_pc/ddr.c
  71. 2
      board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
  72. 2
      board/freescale/p1_p2_rdb_pc/spl_minimal.c
  73. 4
      board/freescale/p1_twr/ddr.c
  74. 2
      board/freescale/p1_twr/p1_twr.c
  75. 4
      board/freescale/p2020come/ddr.c
  76. 6
      board/freescale/p2020ds/ddr.c
  77. 4
      board/freescale/p2020ds/p2020ds.c
  78. 4
      board/freescale/p2041rdb/ddr.c
  79. 4
      board/freescale/t1040qds/ddr.c
  80. 4
      board/freescale/t104xrdb/ddr.c
  81. 4
      board/freescale/t4qds/ddr.c
  82. 2
      board/freescale/t4qds/eth.c
  83. 2
      board/gdsys/p1022/controlcenterd.c
  84. 4
      board/gdsys/p1022/ddr.c
  85. 4
      board/keymile/kmp204x/ddr.c
  86. 2
      board/sbc8548/Makefile
  87. 6
      board/sbc8548/ddr.c
  88. 2
      board/sbc8548/sbc8548.c
  89. 2
      board/sbc8641d/Makefile
  90. 4
      board/sbc8641d/ddr.c
  91. 2
      board/sbc8641d/sbc8641d.c
  92. 2
      board/socrates/Makefile
  93. 4
      board/socrates/ddr.c
  94. 4
      board/socrates/sdram.c
  95. 2
      board/stx/stxgp3/Makefile
  96. 4
      board/stx/stxgp3/ddr.c
  97. 2
      board/stx/stxgp3/stxgp3.c
  98. 2
      board/stx/stxssa/Makefile
  99. 4
      board/stx/stxssa/ddr.c
  100. 2
      board/stx/stxssa/stxssa.c
  101. Some files were not shown because too many files have changed in this diff Show More

1
Makefile
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@ -267,6 +267,7 @@ LIBS-y += drivers/power/ \
drivers/power/battery/
LIBS-y += drivers/spi/
LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/
LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
LIBS-y += drivers/serial/
LIBS-y += drivers/usb/eth/
LIBS-y += drivers/usb/gadget/

41
README
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@ -423,16 +423,47 @@ The following options need to be configured:
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
CONFIG_SYS_FSL_DDR_EMU
Specify emulator support for DDR. Some DDR features such as
deskew training are not available.
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
values is arch specific.
CONFIG_SYS_FSL_DDR
Freescale DDR driver in use. This type of DDR controller is
found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
SoCs.
CONFIG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_DDR_EMU
Specify emulator support for DDR. Some DDR features such as
deskew training are not available.
CONFIG_SYS_FSL_DDRC_GEN1
Freescale DDR1 controller.
CONFIG_SYS_FSL_DDRC_GEN2
Freescale DDR2 controller.
CONFIG_SYS_FSL_DDRC_GEN3
Freescale DDR3 controller.
CONFIG_SYS_FSL_DDR1
Board config to use DDR1. It can be enabled for SoCs with
Freescale DDR1 or DDR2 controllers, depending on the board
implemetation.
CONFIG_SYS_FSL_DDR2
Board config to use DDR2. It can be eanbeld for SoCs with
Freescale DDR2 or DDR3 controllers, depending on the board
implementation.
CONFIG_SYS_FSL_DDR3
Board config to use DDR3. It can be enabled for SoCs with
Freescale DDR3 controllers.
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
@ -3182,7 +3213,7 @@ FIT uImage format:
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
Set for the SPL on PPC mpc8xxx targets, support for
arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
drivers/ddr/fsl/libddr.o in SPL binary.
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in

6
arch/powerpc/cpu/mpc83xx/Makefile
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@ -38,11 +38,11 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
# Stub implementations of cache management functions for USB
obj-y += cache.o
ifdef CONFIG_FSL_DDR2
obj-$(CONFIG_MPC8349) += ../mpc85xx/ddr-gen2.o
ifdef CONFIG_SYS_FSL_DDR2
obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o
else
obj-y += spd_sdram.o
endif
obj-$(CONFIG_FSL_DDR2) += law.o
obj-$(CONFIG_SYS_FSL_DDR2) += law.o
endif # not minimal

4
arch/powerpc/cpu/mpc83xx/ecc.c
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@ -15,7 +15,7 @@
void ecc_print_status(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef CONFIG_FSL_DDR2
#ifdef CONFIG_SYS_FSL_DDR2
ccsr_ddr_t *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;
@ -99,7 +99,7 @@ void ecc_print_status(void)
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef CONFIG_FSL_DDR2
#ifdef CONFIG_SYS_FSL_DDR2
ccsr_ddr_t *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;

45
arch/powerpc/cpu/mpc85xx/Makefile
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@ -29,51 +29,6 @@ obj-$(CONFIG_MP) += release.o
obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
obj-$(CONFIG_CPM2) += commproc.o
# supports ddr1
obj-$(CONFIG_MPC8540) += ddr-gen1.o
obj-$(CONFIG_MPC8560) += ddr-gen1.o
obj-$(CONFIG_MPC8541) += ddr-gen1.o
obj-$(CONFIG_MPC8555) += ddr-gen1.o
# supports ddr1/2
obj-$(CONFIG_MPC8548) += ddr-gen2.o
obj-$(CONFIG_MPC8568) += ddr-gen2.o
obj-$(CONFIG_MPC8544) += ddr-gen2.o
# supports ddr1/2/3
obj-$(CONFIG_PPC_C29X) += ddr-gen3.o
obj-$(CONFIG_MPC8572) += ddr-gen3.o
obj-$(CONFIG_MPC8536) += ddr-gen3.o
obj-$(CONFIG_MPC8569) += ddr-gen3.o
obj-$(CONFIG_P1010) += ddr-gen3.o
obj-$(CONFIG_P1011) += ddr-gen3.o
obj-$(CONFIG_P1012) += ddr-gen3.o
obj-$(CONFIG_P1013) += ddr-gen3.o
obj-$(CONFIG_P1014) += ddr-gen3.o
obj-$(CONFIG_P1020) += ddr-gen3.o
obj-$(CONFIG_P1021) += ddr-gen3.o
obj-$(CONFIG_P1022) += ddr-gen3.o
obj-$(CONFIG_P1023) += ddr-gen3.o
obj-$(CONFIG_P1024) += ddr-gen3.o
obj-$(CONFIG_P1025) += ddr-gen3.o
obj-$(CONFIG_P2010) += ddr-gen3.o
obj-$(CONFIG_P2020) += ddr-gen3.o
obj-$(CONFIG_PPC_P2041) += ddr-gen3.o
obj-$(CONFIG_PPC_P3041) += ddr-gen3.o
obj-$(CONFIG_PPC_P4080) += ddr-gen3.o
obj-$(CONFIG_PPC_P5020) += ddr-gen3.o
obj-$(CONFIG_PPC_P5040) += ddr-gen3.o
obj-$(CONFIG_PPC_T4240) += ddr-gen3.o
obj-$(CONFIG_PPC_T4160) += ddr-gen3.o
obj-$(CONFIG_PPC_B4420) += ddr-gen3.o
obj-$(CONFIG_PPC_B4860) += ddr-gen3.o
obj-$(CONFIG_BSC9131) += ddr-gen3.o
obj-$(CONFIG_BSC9132) += ddr-gen3.o
obj-$(CONFIG_PPC_T1040) += ddr-gen3.o
obj-$(CONFIG_PPC_T1042) += ddr-gen3.o
obj-$(CONFIG_PPC_T1020) += ddr-gen3.o
obj-$(CONFIG_PPC_T1022) += ddr-gen3.o
obj-$(CONFIG_CPM2) += ether_fcc.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_CORENET) += liodn.o

16
arch/powerpc/cpu/mpc85xx/cpu.c
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@ -22,7 +22,7 @@
#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
@ -453,21 +453,21 @@ static void dump_spd_ddr_reg(void)
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
#endif
default:

2
arch/powerpc/cpu/mpc85xx/mp.c
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@ -11,7 +11,7 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;

3
arch/powerpc/cpu/mpc86xx/Makefile
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@ -16,9 +16,6 @@ obj-$(CONFIG_MP) += release.o
obj-y += cpu.o
obj-y += cpu_init.o
# 8610 & 8641 are identical w/regards to DDR
obj-$(CONFIG_MPC8610) += ddr-8641.o
obj-$(CONFIG_MPC8641) += ddr-8641.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-y += interrupts.o
obj-$(CONFIG_MP) += mp.o

6
arch/powerpc/cpu/mpc8xxx/Makefile
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@ -31,9 +31,3 @@ obj-$(CONFIG_SYS_SRIO) += srio.o
obj-$(CONFIG_FSL_LAW) += law.o
endif
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/
else
obj-y += ddr/
endif

29
arch/powerpc/cpu/mpc8xxx/ddr/Makefile
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@ -1,29 +0,0 @@
#
# Copyright 2008-2011 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# Version 2 as published by the Free Software Foundation.
#
obj-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
obj-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
obj-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
ifdef CONFIG_DDR_SPD
SPD := y
endif
ifdef CONFIG_SPD_EEPROM
SPD := y
endif
ifdef SPD
obj-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
obj-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
obj-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o
endif
obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o

6
arch/powerpc/include/asm/config.h
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@ -9,10 +9,16 @@
#ifdef CONFIG_MPC85xx
#include <asm/config_mpc85xx.h>
#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC86xx
#include <asm/config_mpc86xx.h>
#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC83xx
#define CONFIG_SYS_FSL_DDR
#endif
#ifndef HWCONFIG_BUFFER_SIZE

13
arch/powerpc/include/asm/config_mpc85xx.h
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@ -40,17 +40,20 @@
#elif defined(CONFIG_MPC8540)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8541)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8544)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@ -59,6 +62,7 @@
#elif defined(CONFIG_MPC8548)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@ -77,17 +81,20 @@
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8560)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8568)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
@ -738,4 +745,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
#endif
#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
!defined(CONFIG_SYS_FSL_DDRC_GEN3)
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
#endif /* _ASM_MPC85xx_CONFIG_H_ */

2
arch/powerpc/include/asm/config_mpc86xx.h
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@ -7,6 +7,8 @@
#ifndef _ASM_MPC86xx_CONFIG_H_
#define _ASM_MPC86xx_CONFIG_H_
#define CONFIG_SYS_FSL_DDR_86XX
/* SoC specific defines for Freescale MPC86xx processors */
#if defined(CONFIG_MPC8610)

6
arch/powerpc/include/asm/immap_83xx.h
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@ -279,7 +279,7 @@ typedef struct qesba83xx {
/*
* DDR Memory Controller Memory Map
*/
#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
typedef struct ccsr_ddr {
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
u8 res1[4];
@ -739,7 +739,7 @@ typedef struct immap {
u8 dll_ddr[0x100];
u8 dll_lbc[0x100];
u8 res1[0xE00];
#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
#else
ddr83xx_t ddr; /* DDR Memory Controller Memory */
@ -1029,7 +1029,7 @@ typedef struct immap {
#endif
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
#define CONFIG_SYS_MPC83xx_DMA_ADDR \

6
arch/powerpc/include/asm/immap_85xx.h
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@ -3048,11 +3048,11 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
#define CONFIG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
#define CONFIG_SYS_FSL_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
#define CONFIG_SYS_FSL_DDR3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)

4
arch/powerpc/include/asm/immap_86xx.h
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@ -1253,9 +1253,9 @@ typedef struct immap {
extern immap_t *immr;
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000

4
board/exmeritus/hww1u1a/ddr.c
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@ -9,8 +9,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

4
board/exmeritus/hww1u1a/hww1u1a.c
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@ -13,7 +13,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
@ -89,7 +89,7 @@ int checkboard(void)
* and delay a while before we continue.
*/
if (mpc85xx_gpio_get(GPIO_RESETS)) {
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
puts("Debugger detected... extra device reset enabled!\n");

6
board/freescale/b4860qds/ddr.c
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@ -9,11 +9,11 @@
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <fsl_ddr.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
DECLARE_GLOBAL_DATA_PTR;

4
board/freescale/bsc9131rdb/ddr.c
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@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>

4
board/freescale/bsc9131rdb/spl_minimal.c
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@ -10,7 +10,7 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);

4
board/freescale/bsc9132qds/bsc9132qds.c
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@ -20,7 +20,7 @@
#include <asm/fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#ifdef CONFIG_PCI
#include <pci.h>
@ -134,7 +134,7 @@ void dsp_ddr_configure(void)
*to the DSP DDR controller as connected DDR memories are similar.
*/
ccsr_ddr_t __iomem *pa_ddr =
(ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
(ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_ddr_t temp_ddr;
ccsr_ddr_t __iomem *dsp_ddr =
(ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;

4
board/freescale/bsc9132qds/ddr.c
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@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>

4
board/freescale/bsc9132qds/spl_minimal.c
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@ -10,14 +10,14 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
#if CONFIG_DDR_CLK_FREQ == 100000000
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);

4
board/freescale/c29xpcie/ddr.c
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@ -6,8 +6,8 @@
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include "cpld.h"

4
board/freescale/corenet_ds/ddr.c
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@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;

2
board/freescale/corenet_ds/eth_p4080.c
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@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>

2
board/freescale/corenet_ds/p3041ds_ddr.c
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@ -7,7 +7,7 @@
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}

2
board/freescale/corenet_ds/p4080ds_ddr.c
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@ -7,7 +7,7 @@
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104

2
board/freescale/corenet_ds/p5020ds_ddr.c
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@ -7,7 +7,7 @@
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}

2
board/freescale/corenet_ds/p5040ds_ddr.c
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@ -7,7 +7,7 @@
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}

2
board/freescale/mpc8349emds/Makefile
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@ -7,4 +7,4 @@
obj-y += mpc8349emds.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_FSL_DDR2) += ddr.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o

4
board/freescale/mpc8349emds/ddr.c
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@ -6,8 +6,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;

6
board/freescale/mpc8349emds/mpc8349emds.c
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@ -12,8 +12,8 @@
#include <i2c.h>
#include <spi.h>
#include <miiphy.h>
#ifdef CONFIG_FSL_DDR2
#include <asm/fsl_ddr_sdram.h>
#ifdef CONFIG_SYS_FSL_DDR2
#include <fsl_ddr_sdram.h>
#else
#include <spd_sdram.h>
#endif
@ -57,7 +57,7 @@ phys_size_t initdram (int board_type)
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
#ifndef CONFIG_FSL_DDR2
#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
ddr_enable_ecc(msize);

4
board/freescale/mpc8536ds/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/freescale/mpc8536ds/mpc8536ds.c
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@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <spd.h>

4
board/freescale/mpc8540ads/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

4
board/freescale/mpc8540ads/mpc8540ads.c
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@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
@ -168,7 +168,7 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

4
board/freescale/mpc8541cds/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/freescale/mpc8541cds/mpc8541cds.c
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@ -11,7 +11,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <libfdt.h>

4
board/freescale/mpc8544ds/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/freescale/mpc8544ds/mpc8544ds.c
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@ -11,7 +11,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>

4
board/freescale/mpc8548cds/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/freescale/mpc8548cds/mpc8548cds.c
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@ -12,7 +12,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
#include <libfdt.h>

4
board/freescale/mpc8555cds/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/freescale/mpc8555cds/mpc8555cds.c
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@ -9,7 +9,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <libfdt.h>

4
board/freescale/mpc8560ads/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

4
board/freescale/mpc8560ads/mpc8560ads.c
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@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <miiphy.h>
@ -373,7 +373,7 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

4
board/freescale/mpc8568mds/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/freescale/mpc8568mds/mpc8568mds.c
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@ -12,7 +12,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <i2c.h>

4
board/freescale/mpc8569mds/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

4
board/freescale/mpc8569mds/mpc8569mds.c
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@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <spd_sdram.h>
@ -231,7 +231,7 @@ int checkboard (void)
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);

4
board/freescale/mpc8572ds/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;

2
board/freescale/mpc8572ds/mpc8572ds.c
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@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>

2
board/freescale/mpc8610hpcd/Makefile
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@ -4,6 +4,6 @@
#
obj-y += mpc8610hpcd.o
obj-$(CONFIG_FSL_DDR2) += ddr.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
obj-y += law.o
obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o

4
board/freescale/mpc8610hpcd/ddr.c
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@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/freescale/mpc8610hpcd/mpc8610hpcd.c
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@ -10,7 +10,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <i2c.h>
#include <asm/io.h>

2
board/freescale/mpc8641hpcn/Makefile
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@ -7,4 +7,4 @@
obj-y += mpc8641hpcn.o
obj-y += law.o
obj-$(CONFIG_FSL_DDR2) += ddr.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o

4
board/freescale/mpc8641hpcn/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;

2
board/freescale/mpc8641hpcn/mpc8641hpcn.c
Unescape View File

@ -9,7 +9,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>

4
board/freescale/p1010rdb/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>

4
board/freescale/p1010rdb/spl_minimal.c
Unescape View File

@ -10,7 +10,7 @@
#include <nand.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#include <asm/global_data.h>
@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 ddr_ratio;
unsigned long ddr_freq_mhz;

4
board/freescale/p1022ds/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;

2
board/freescale/p1022ds/p1022ds.c
Unescape View File

@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>

2
board/freescale/p1022ds/spl_minimal.c
Unescape View File

@ -9,7 +9,7 @@
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
const static u32 sysclk_tbl[] = {

4
board/freescale/p1023rdb/ddr.c
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@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>

2
board/freescale/p1023rdb/p1023rdb.c
Unescape View File

@ -16,7 +16,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <libfdt.h>
#include <fdt_support.h>

4
board/freescale/p1023rds/p1023rds.c
Unescape View File

@ -16,7 +16,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <libfdt.h>
#include <fdt_support.h>
@ -58,7 +58,7 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);

2
board/freescale/p1_p2_rdb/ddr.c
Unescape View File

@ -8,7 +8,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>

4
board/freescale/p1_p2_rdb_pc/ddr.c
Unescape View File

@ -10,8 +10,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>

2
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
Unescape View File

@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>

2
board/freescale/p1_p2_rdb_pc/spl_minimal.c
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@ -10,7 +10,7 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;

4
board/freescale/p1_twr/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>

2
board/freescale/p1_twr/p1_twr.c
Unescape View File

@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>

4
board/freescale/p2020come/ddr.c
Unescape View File

@ -5,8 +5,8 @@
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

6
board/freescale/p2020ds/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
@ -37,7 +37,7 @@ static const struct board_specific_parameters dimm0[] = {
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
#ifdef CONFIG_FSL_DDR2
#ifdef CONFIG_SYS_FSL_DDR2
{2, 549, 4, 0x1f, 2, 0},
{2, 680, 4, 0x1f, 3, 0},
{2, 850, 4, 0x1f, 4, 0},

4
board/freescale/p2020ds/p2020ds.c
Unescape View File

@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
@ -68,7 +68,7 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

4
board/freescale/p2041rdb/ddr.c
Unescape View File

@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
struct board_specific_parameters {

4
board/freescale/t1040qds/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"

4
board/freescale/t104xrdb/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"

4
board/freescale/t4qds/ddr.c
Unescape View File

@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"

2
board/freescale/t4qds/eth.c
Unescape View File

@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>

2
board/gdsys/p1022/controlcenterd.c
Unescape View File

@ -29,7 +29,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>

4
board/gdsys/p1022/ddr.c
Unescape View File

@ -12,8 +12,8 @@
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
unsigned int ctrl_num)

4
board/keymile/kmp204x/ddr.c
Unescape View File

@ -11,8 +11,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/sbc8548/Makefile
Unescape View File

@ -11,4 +11,4 @@
obj-y += sbc8548.o
obj-y += law.o
obj-y += tlb.o
obj-$(CONFIG_FSL_DDR2) += ddr.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o

6
board/sbc8548/ddr.c
Unescape View File

@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
@ -91,7 +91,7 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
*/
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
out_be32(&ddr->cs0_bnds, 0x0000007f);
out_be32(&ddr->cs1_bnds, 0x008000ff);

2
board/sbc8548/sbc8548.c
Unescape View File

@ -15,7 +15,7 @@
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <netdev.h>

2
board/sbc8641d/Makefile
Unescape View File

@ -7,4 +7,4 @@
obj-y += sbc8641d.o
obj-y += law.o
obj-$(CONFIG_FSL_DDR2) += ddr.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o

4
board/sbc8641d/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/sbc8641d/sbc8641d.c
Unescape View File

@ -18,7 +18,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <libfdt.h>
#include <fdt_support.h>

2
board/socrates/Makefile
Unescape View File

@ -12,4 +12,4 @@ obj-y += law.o
obj-y += tlb.o
obj-y += nand.o
obj-y += sdram.o
obj-$(CONFIG_FSL_DDR2) += ddr.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o

4
board/socrates/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

4
board/socrates/sdram.c
Unescape View File

@ -8,7 +8,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
@ -24,7 +24,7 @@
*/
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
/*
* Disable memory controller.

2
board/stx/stxgp3/Makefile
Unescape View File

@ -9,4 +9,4 @@ obj-y += stxgp3.o
obj-y += law.o
obj-y += tlb.o
obj-y += flash.o
obj-$(CONFIG_FSL_DDR1) += ddr.o
obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o

4
board/stx/stxgp3/ddr.c
Unescape View File

@ -8,8 +8,8 @@
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/stx/stxgp3/stxgp3.c
Unescape View File

@ -18,7 +18,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#include <spd_sdram.h>

2
board/stx/stxssa/Makefile
Unescape View File

@ -8,4 +8,4 @@
obj-y += stxssa.o
obj-y += law.o
obj-y += tlb.o
obj-$(CONFIG_FSL_DDR1) += ddr.o
obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o

4
board/stx/stxssa/ddr.c
Unescape View File

@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,

2
board/stx/stxssa/stxssa.c
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@ -19,7 +19,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#include <spd_sdram.h>

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