powerpc/86xx: Enable common SRIO init code

Add the needed defines and code to utilize the common 8xxx srio init
code to setup LAWs and modify device tree if we have SRIO enabled on a
board.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
master
Kumar Gala 14 years ago
parent e5fe96b1ab
commit 5655136208
  1. 7
      arch/powerpc/cpu/mpc86xx/cpu_init.c
  2. 7
      arch/powerpc/cpu/mpc86xx/fdt.c
  3. 4
      arch/powerpc/include/asm/immap_86xx.h

@ -1,5 +1,5 @@
/*
* Copyright 2004,2009-2010 Freescale Semiconductor, Inc.
* Copyright 2004,2009-2011 Freescale Semiconductor, Inc.
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
@ -34,6 +34,7 @@
#include <asm/fsl_serdes.h>
#include <asm/mp.h>
extern void srio_init(void);
void setup_bats(void);
DECLARE_GLOBAL_DATA_PTR;
@ -80,6 +81,10 @@ int cpu_init_r(void)
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
#ifdef CONFIG_SYS_SRIO
srio_init();
#endif
#if defined(CONFIG_MP)
setup_mp();
#endif

@ -1,5 +1,5 @@
/*
* Copyright 2008,2010 Freescale Semiconductor, Inc.
* Copyright 2008, 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -14,6 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
void ft_cpu_setup(void *blob, bd_t *bd)
{
@ -58,4 +59,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_fixup_num_cores(blob);
#endif
#ifdef CONFIG_SYS_SRIO
ft_srio_setup(blob);
#endif
}

@ -1,7 +1,7 @@
/*
* MPC86xx Internal Memory Map
*
* Copyright 2004 Freescale Semiconductor
* Copyright 2004, 2011 Freescale Semiconductor
* Jeff Brown (Jeffrey@freescale.com)
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
@ -1205,6 +1205,8 @@ typedef struct ccsr_gur {
#define MPC86xx_DEVDISR_PCI1 0x80000000
#define MPC86xx_DEVDISR_PCIE1 0x40000000
#define MPC86xx_DEVDISR_PCIE2 0x20000000
#define MPC86xx_DEVDISR_SRIO 0x00080000
#define MPC86xx_DEVDISR_RMSG 0x00040000
#define MPC86xx_DEVDISR_CPU0 0x00008000
#define MPC86xx_DEVDISR_CPU1 0x00004000
#define MPC86xx_RSTCR_HRST_REQ 0x00000002

Loading…
Cancel
Save