Add DDR driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>lime2-spi
Tien Fong Chee
7 years ago
committed by
Marek Vasut
parent
53faef1e3f
commit
5658a299bd
@ -0,0 +1,741 @@ |
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/*
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* Copyright (C) 2017 Intel Corporation <www.intel.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <errno.h> |
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#include <fdtdec.h> |
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#include <malloc.h> |
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#include <wait_bit.h> |
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#include <watchdog.h> |
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#include <asm/io.h> |
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#include <asm/arch/fpga_manager.h> |
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#include <asm/arch/misc.h> |
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#include <asm/arch/reset_manager.h> |
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#include <asm/arch/sdram.h> |
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#include <linux/kernel.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static void sdram_mmr_init(void); |
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static u64 sdram_size_calc(void); |
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/* FAWBANK - Number of Bank of a given device involved in the FAW period. */ |
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#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1) |
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#define ARRIA_DDR_CONFIG(A, B, C, R) \ |
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(((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) |
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#define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config) |
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#define DDR_REG_SEQ2CORE 0xFFD0507C |
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#define DDR_REG_CORE2SEQ 0xFFD05078 |
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#define DDR_READ_LATENCY_DELAY 40 |
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#define DDR_SIZE_2GB_HEX 0x80000000 |
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#define DDR_MAX_TRIES 0x00100000 |
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#define IO48_MMR_DRAMSTS 0xFFCFA0EC |
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#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110 |
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#define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114 |
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#define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118 |
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#define SEQ2CORE_MASK 0xF |
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#define CORE2SEQ_INT_REQ 0xF |
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#define SEQ2CORE_INT_RESP_BIT 3 |
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static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = |
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(void *)SOCFPGA_SDR_ADDRESS; |
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static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = |
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(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; |
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static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram |
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*socfpga_noc_fw_ddr_mpu_fpga2sdram_base = |
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(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS; |
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static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base = |
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(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; |
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static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = |
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(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; |
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/* The following are the supported configurations */ |
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static u32 ddr_config[] = { |
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/* Chip - Row - Bank - Column Style */ |
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/* All Types */ |
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ARRIA_DDR_CONFIG(0, 3, 10, 12), |
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ARRIA_DDR_CONFIG(0, 3, 10, 13), |
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ARRIA_DDR_CONFIG(0, 3, 10, 14), |
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ARRIA_DDR_CONFIG(0, 3, 10, 15), |
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ARRIA_DDR_CONFIG(0, 3, 10, 16), |
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ARRIA_DDR_CONFIG(0, 3, 10, 17), |
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/* LPDDR x16 */ |
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ARRIA_DDR_CONFIG(0, 3, 11, 14), |
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ARRIA_DDR_CONFIG(0, 3, 11, 15), |
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ARRIA_DDR_CONFIG(0, 3, 11, 16), |
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ARRIA_DDR_CONFIG(0, 3, 12, 15), |
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/* DDR4 Only */ |
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ARRIA_DDR_CONFIG(0, 4, 10, 14), |
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ARRIA_DDR_CONFIG(0, 4, 10, 15), |
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ARRIA_DDR_CONFIG(0, 4, 10, 16), |
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ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */ |
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/* Chip - Bank - Row - Column Style */ |
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ARRIA_DDR_CONFIG(1, 3, 10, 12), |
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ARRIA_DDR_CONFIG(1, 3, 10, 13), |
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ARRIA_DDR_CONFIG(1, 3, 10, 14), |
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ARRIA_DDR_CONFIG(1, 3, 10, 15), |
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ARRIA_DDR_CONFIG(1, 3, 10, 16), |
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ARRIA_DDR_CONFIG(1, 3, 10, 17), |
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ARRIA_DDR_CONFIG(1, 3, 11, 14), |
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ARRIA_DDR_CONFIG(1, 3, 11, 15), |
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ARRIA_DDR_CONFIG(1, 3, 11, 16), |
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ARRIA_DDR_CONFIG(1, 3, 12, 15), |
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/* DDR4 Only */ |
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ARRIA_DDR_CONFIG(1, 4, 10, 14), |
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ARRIA_DDR_CONFIG(1, 4, 10, 15), |
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ARRIA_DDR_CONFIG(1, 4, 10, 16), |
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ARRIA_DDR_CONFIG(1, 4, 10, 17), |
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}; |
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static int match_ddr_conf(u32 ddr_conf) |
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{ |
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int i; |
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for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) { |
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if (ddr_conf == ddr_config[i]) |
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return i; |
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} |
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return 0; |
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} |
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/* Check whether SDRAM is successfully Calibrated */ |
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static int is_sdram_cal_success(void) |
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{ |
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return readl(&socfpga_ecc_hmc_base->ddrcalstat); |
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} |
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static unsigned char ddr_get_bit(u32 ereg, unsigned char bit) |
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{ |
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u32 reg = readl(ereg); |
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return (reg & BIT(bit)) ? 1 : 0; |
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} |
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static unsigned char ddr_wait_bit(u32 ereg, u32 bit, |
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u32 expected, u32 timeout_usec) |
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{ |
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u32 tmr; |
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for (tmr = 0; tmr < timeout_usec; tmr += 100) { |
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udelay(100); |
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WATCHDOG_RESET(); |
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if (ddr_get_bit(ereg, bit) == expected) |
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return 0; |
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} |
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return 1; |
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} |
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static int emif_clear(void) |
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{ |
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u32 i = DDR_MAX_TRIES; |
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u8 ret = 0; |
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writel(0, DDR_REG_CORE2SEQ); |
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do { |
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ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, |
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SEQ2CORE_MASK, 1, 50, 0); |
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} while (ret && (--i > 0)); |
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return !i; |
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} |
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static int emif_reset(void) |
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{ |
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u32 c2s, s2c; |
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c2s = readl(DDR_REG_CORE2SEQ); |
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s2c = readl(DDR_REG_SEQ2CORE); |
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debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", |
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c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0), |
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readl(IO48_MMR_NIOS2_RESERVE1), |
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readl(IO48_MMR_NIOS2_RESERVE2), |
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readl(IO48_MMR_DRAMSTS)); |
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if ((s2c & SEQ2CORE_MASK) && emif_clear()) { |
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debug("failed emif_clear()\n"); |
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return -EPERM; |
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} |
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writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); |
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if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) { |
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debug("emif_reset failed to see interrupt acknowledge\n"); |
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return -EPERM; |
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} else { |
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debug("emif_reset interrupt acknowledged\n"); |
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} |
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if (emif_clear()) { |
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debug("emif_clear() failed\n"); |
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return -EPERM; |
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} |
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debug("emif_reset interrupt cleared\n"); |
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debug("nr0=%08x nr1=%08x nr2=%08x\n", |
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readl(IO48_MMR_NIOS2_RESERVE0), |
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readl(IO48_MMR_NIOS2_RESERVE1), |
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readl(IO48_MMR_NIOS2_RESERVE2)); |
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return 0; |
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} |
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static int ddr_setup(void) |
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{ |
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int i, j, ddr_setup_complete = 0; |
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/* Try 3 times to do a calibration */ |
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for (i = 0; (i < 3) && !ddr_setup_complete; i++) { |
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WATCHDOG_RESET(); |
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/* A delay to wait for calibration bit to set */ |
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for (j = 0; (j < 10) && !ddr_setup_complete; j++) { |
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mdelay(500); |
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ddr_setup_complete = is_sdram_cal_success(); |
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} |
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if (!ddr_setup_complete) |
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if (emif_reset()) |
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puts("Error: Failed to reset EMIF\n"); |
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} |
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/* After 3 times trying calibration */ |
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if (!ddr_setup_complete) { |
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puts("Error: Could Not Calibrate SDRAM\n"); |
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return -EPERM; |
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} |
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return 0; |
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} |
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/* Function to startup the SDRAM*/ |
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static int sdram_startup(void) |
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{ |
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/* Release NOC ddr scheduler from reset */ |
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socfpga_reset_deassert_noc_ddr_scheduler(); |
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/* Bringup the DDR (calibration and configuration) */ |
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return ddr_setup(); |
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} |
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static u64 sdram_size_calc(void) |
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{ |
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u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); |
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u64 size = BIT(((dramaddrw & |
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IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >> |
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IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) + |
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((dramaddrw & |
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IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> |
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IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) + |
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((dramaddrw & |
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IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> |
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IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + |
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((dramaddrw & |
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IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> |
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IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) + |
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(dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK)); |
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size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) & |
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ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK)); |
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debug("SDRAM size=%llu", size); |
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return size; |
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} |
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/* Function to initialize SDRAM MMR and NOC DDR scheduler*/ |
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static void sdram_mmr_init(void) |
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{ |
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u32 update_value, io48_value; |
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u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0); |
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u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1); |
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u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); |
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u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0); |
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u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1); |
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u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2); |
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u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3); |
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u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4); |
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u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9); |
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u32 ddrioctl; |
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/*
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* Configure the DDR IO size [0xFFCFB008] |
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* niosreserve0: Used to indicate DDR width & |
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* bit[7:0] = Number of data bits (0x20 for 32bit) |
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* bit[8] = 1 if user-mode OCT is present |
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* bit[9] = 1 if warm reset compiled into EMIF Cal Code |
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* bit[10] = 1 if warm reset is on during generation in EMIF Cal |
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* niosreserve1: IP ADCDS version encoded as 16 bit value |
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* bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, |
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* 3=EAP, 4-6 are reserved) |
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* bit[5:3] = Service Pack # (e.g. 1) |
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* bit[9:6] = Minor Release # |
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* bit[14:10] = Major Release # |
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*/ |
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if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) { |
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update_value = readl(&socfpga_io48_mmr_base->niosreserve0); |
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writel(((update_value & 0xFF) >> 5), |
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&socfpga_ecc_hmc_base->ddrioctrl); |
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} |
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ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl); |
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/* Set the DDR Configuration [0xFFD12400] */ |
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io48_value = ARRIA_DDR_CONFIG( |
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((ctrlcfg1 & |
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IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >> |
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IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT), |
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((dramaddrw & |
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IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> |
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IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + |
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((dramaddrw & |
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IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> |
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IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT), |
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(dramaddrw & |
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IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK), |
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((dramaddrw & |
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IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> |
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IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT)); |
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update_value = match_ddr_conf(io48_value); |
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if (update_value) |
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writel(update_value, |
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&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf); |
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/*
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* Configure DDR timing [0xFFD1240C] |
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* RDTOMISS = tRTP + tRP + tRCD - BL/2 |
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* WRTOMISS = WL + tWR + tRP + tRCD and |
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* WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... |
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* First part of equation is in memory clock units so divide by 2 |
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* for HMC clock units. 1066MHz is close to 1ns so use 15 directly. |
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* WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD |
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*/ |
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u32 ctrlcfg0_cfg_ctrl_burst_len = |
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(ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >> |
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IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT; |
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u32 caltim0_cfg_act_to_rdwr = caltim0 & |
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IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK; |
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u32 caltim0_cfg_act_to_act = |
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(caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >> |
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IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT; |
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u32 caltim0_cfg_act_to_act_db = |
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(caltim0 & |
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IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >> |
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IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT; |
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u32 caltim1_cfg_rd_to_wr = |
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(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >> |
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IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT; |
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u32 caltim1_cfg_rd_to_rd_dc = |
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(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >> |
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IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT; |
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u32 caltim1_cfg_rd_to_wr_dc = |
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(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >> |
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IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT; |
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u32 caltim2_cfg_rd_to_pch = |
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(caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >> |
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IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT; |
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u32 caltim3_cfg_wr_to_rd = |
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(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >> |
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IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT; |
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u32 caltim3_cfg_wr_to_rd_dc = |
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(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >> |
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IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT; |
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u32 caltim4_cfg_pch_to_valid = |
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(caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >> |
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IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT; |
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u32 caltim9_cfg_4_act_to_act = caltim9 & |
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IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK; |
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update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid + |
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caltim0_cfg_act_to_rdwr - |
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(ctrlcfg0_cfg_ctrl_burst_len >> 2)); |
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io48_value = ((((socfpga_io48_mmr_base->dramtiming0 & |
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ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 + |
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(ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) - |
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/* Up to here was in memory cycles so divide by 2 */ |
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caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr + |
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caltim4_cfg_pch_to_valid); |
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writel(((caltim0_cfg_act_to_act << |
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ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) | |
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(update_value << |
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ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) | |
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(io48_value << |
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ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) | |
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((ctrlcfg0_cfg_ctrl_burst_len >> 2) << |
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ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) | |
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(caltim1_cfg_rd_to_wr << |
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ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) | |
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(caltim3_cfg_wr_to_rd << |
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ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) | |
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(((ddrioctl == 1) ? 1 : 0) << |
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ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)), |
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&socfpga_noc_ddr_scheduler_base-> |
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ddr_t_main_scheduler_ddrtiming); |
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/* Configure DDR mode [0xFFD12410] [precharge = 0] */ |
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writel(((ddrioctl ? 0 : 1) << |
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ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB), |
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&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode); |
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/* Configure the read latency [0xFFD12414] */ |
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writel(((socfpga_io48_mmr_base->dramtiming0 & |
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ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) + |
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DDR_READ_LATENCY_DELAY, |
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&socfpga_noc_ddr_scheduler_base-> |
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ddr_t_main_scheduler_readlatency); |
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/*
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* Configuring timing values concerning activate commands |
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* [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR] |
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*/ |
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writel(((caltim0_cfg_act_to_act_db << |
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ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) | |
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(caltim9_cfg_4_act_to_act << |
||||
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) | |
||||
(ARRIA10_SDR_ACTIVATE_FAWBANK << |
||||
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)), |
||||
&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate); |
||||
|
||||
/*
|
||||
* Configuring timing values concerning device to device data bus |
||||
* ownership change [0xFFD1243C] |
||||
*/ |
||||
writel(((caltim1_cfg_rd_to_rd_dc << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) | |
||||
(caltim1_cfg_rd_to_wr_dc << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) | |
||||
(caltim3_cfg_wr_to_rd_dc << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)), |
||||
&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev); |
||||
|
||||
/* Enable or disable the SDRAM ECC */ |
||||
if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) { |
||||
setbits_le32(&socfpga_ecc_hmc_base->eccctrl, |
||||
(ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); |
||||
clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, |
||||
(ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK)); |
||||
setbits_le32(&socfpga_ecc_hmc_base->eccctrl2, |
||||
(ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); |
||||
} else { |
||||
clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, |
||||
(ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); |
||||
clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2, |
||||
(ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); |
||||
} |
||||
} |
||||
|
||||
struct firewall_entry { |
||||
const char *prop_name; |
||||
const u32 cfg_addr; |
||||
const u32 en_addr; |
||||
const u32 en_bit; |
||||
}; |
||||
#define FW_MPU_FPGA_ADDRESS \ |
||||
((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
|
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS) |
||||
|
||||
#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \ |
||||
(SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
|
||||
offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR)) |
||||
|
||||
#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \ |
||||
(SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
|
||||
offsetof(struct socfpga_noc_fw_ddr_l3, ADDR)) |
||||
|
||||
const struct firewall_entry firewall_table[] = { |
||||
{ |
||||
"mpu0", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"mpu1", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"mpu2", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"mpu3", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-0", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-1", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-2", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-3", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-4", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-5", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-6", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-7", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram0-0", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram0region0addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram0-1", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram0region1addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram0-2", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram0region2addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram0-3", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram0region3addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram1-0", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram1region0addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram1-1", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram1region1addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram1-2", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram1region2addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram1-3", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram1region3addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram2-0", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram2region0addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram2-1", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram2region1addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram2-2", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram2region2addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram2-3", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram2region3addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK |
||||
}, |
||||
|
||||
}; |
||||
|
||||
static int of_sdram_firewall_setup(const void *blob) |
||||
{ |
||||
int child, i, node, ret; |
||||
u32 start_end[2]; |
||||
char name[32]; |
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC); |
||||
if (node < 0) |
||||
return -ENXIO; |
||||
|
||||
child = fdt_first_subnode(blob, node); |
||||
if (child < 0) |
||||
return -ENXIO; |
||||
|
||||
/* set to default state */ |
||||
writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable); |
||||
writel(0, &socfpga_noc_fw_ddr_l3_base->enable); |
||||
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(firewall_table); i++) { |
||||
sprintf(name, "%s", firewall_table[i].prop_name); |
||||
ret = fdtdec_get_int_array(blob, child, name, |
||||
start_end, 2); |
||||
if (ret) { |
||||
sprintf(name, "altr,%s", firewall_table[i].prop_name); |
||||
ret = fdtdec_get_int_array(blob, child, name, |
||||
start_end, 2); |
||||
if (ret) |
||||
continue; |
||||
} |
||||
|
||||
writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) | |
||||
(start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB), |
||||
firewall_table[i].cfg_addr); |
||||
setbits_le32(firewall_table[i].en_addr, |
||||
firewall_table[i].en_bit); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int ddr_calibration_sequence(void) |
||||
{ |
||||
WATCHDOG_RESET(); |
||||
|
||||
/* Check to see if SDRAM cal was success */ |
||||
if (sdram_startup()) { |
||||
puts("DDRCAL: Failed\n"); |
||||
return -EPERM; |
||||
} |
||||
|
||||
puts("DDRCAL: Success\n"); |
||||
|
||||
WATCHDOG_RESET(); |
||||
|
||||
/* initialize the MMR register */ |
||||
sdram_mmr_init(); |
||||
|
||||
/* assigning the SDRAM size */ |
||||
u64 size = sdram_size_calc(); |
||||
|
||||
/*
|
||||
* If size is less than zero, this is invalid/weird value from |
||||
* calculation, use default Config size. |
||||
* Up to 2GB is supported, 2GB would be used if more than that. |
||||
*/ |
||||
if (size <= 0) |
||||
gd->ram_size = PHYS_SDRAM_1_SIZE; |
||||
else if (DDR_SIZE_2GB_HEX <= size) |
||||
gd->ram_size = DDR_SIZE_2GB_HEX; |
||||
else |
||||
gd->ram_size = (u32)size; |
||||
|
||||
/* setup the dram info within bd */ |
||||
dram_init_banksize(); |
||||
|
||||
if (of_sdram_firewall_setup(gd->fdt_blob)) |
||||
puts("FW: Error Configuring Firewall\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void dram_bank_mmu_setup(int bank) |
||||
{ |
||||
bd_t *bd = gd->bd; |
||||
int i; |
||||
|
||||
debug("%s: bank: %d\n", __func__, bank); |
||||
for (i = bd->bi_dram[bank].start >> 20; |
||||
i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; |
||||
i++) { |
||||
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
||||
set_section_dcache(i, DCACHE_WRITETHROUGH); |
||||
#else |
||||
set_section_dcache(i, DCACHE_WRITEBACK); |
||||
#endif |
||||
} |
||||
|
||||
/* same as above but just that we would want cacheable for ocram too */ |
||||
i = CONFIG_SYS_INIT_RAM_ADDR >> 20; |
||||
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
||||
set_section_dcache(i, DCACHE_WRITETHROUGH); |
||||
#else |
||||
set_section_dcache(i, DCACHE_WRITEBACK); |
||||
#endif |
||||
} |
||||
Loading…
Reference in new issue