sh: Add support SuperH SH7751/SH7751R

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
master
Nobuhiro Iwamatsu 16 years ago
parent 3313e0e262
commit 5669332781
  1. 1
      drivers/serial/serial_sh.c
  2. 11
      include/asm-sh/cpu_sh4.h
  3. 4
      include/asm-sh/cpu_sh7750.h

@ -55,6 +55,7 @@
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0xFF
#elif defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7722)
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)

@ -30,14 +30,15 @@
#define CACHE_OC_NUM_ENTRIES 512
#define CACHE_OC_ENTRY_SHIFT 5
#if defined (CONFIG_CPU_SH7750)
#include <asm/cpu_sh7750.h>
#if defined (CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751)
# include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
#include <asm/cpu_sh7722.h>
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7780)
#include <asm/cpu_sh7780.h>
# include <asm/cpu_sh7780.h>
#else
#error "Unknown SH4 variant"
# error "Unknown SH4 variant"
#endif
#endif /* _ASM_CPU_SH4_H_ */

@ -25,10 +25,10 @@
#ifdef CONFIG_CPU_TYPE_R
#define CACHE_OC_NUM_WAYS 2
#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
#else
#define CACHE_OC_NUM_WAYS 1
#define CCR_CACHE_INIT 0x0000090b
#define CCR_CACHE_INIT 0x0000090B
#endif
/* OCN */

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